The car is becoming something far more complex than a machine that carries people from one place to another. It is evolving into an intelligent, connected computing platform—an active node in the Internet of Everything, capable of sensing its surroundings, interpreting rapidly changing conditions and making decisions in environments where mistakes can have immediate and serious consequences. A new Perspective in Nature Reviews Electrical Engineering argues that the future of autonomous driving will depend not only on better algorithms or more powerful processors, but on whether engineers can redesign the entire relationship between hardware and software.
As driving responsibilities move from human motorists to artificial intelligence, autonomous vehicles must process enormous quantities of data in real time. Cameras, radar, lidar, ultrasonic sensors, high-precision positioning systems and internal vehicle monitors continuously generate information. That data must be fused into a coherent representation of the vehicle’s surroundings, interpreted by machine-learning models and converted into safe actions such as braking, steering or changing lanes. Unlike many conventional computing applications, autonomous driving cannot simply tolerate delays, interruptions or occasional incorrect results. The system must respond within strict time limits while maintaining a high level of reliability under changing weather, traffic and road conditions.
This combination of computational intensity and safety requirements is placing unprecedented pressure on automotive chips. Advanced perception and decision-making models increasingly rely on deep neural networks, which require large numbers of mathematical operations, especially matrix multiplications and memory accesses. Processing these models demands substantial parallel computing capacity, yet the vehicle must also operate within tight limits on energy consumption, heat generation, physical space and cost. A data centre can add cooling equipment and electrical power to support an artificial-intelligence workload. A vehicle has far less flexibility: its computing platform must fit inside a compact system, survive vibration and temperature changes, consume limited energy and remain dependable for years.
The Perspective identifies a widening gap between the computational demands of autonomous driving and the physical limits of conventional chip technologies. For decades, improvements in semiconductor manufacturing allowed engineers to place more transistors on smaller chips, helping increase performance while reducing energy use per operation. That progress, often associated with the continuation of Moore’s law, is becoming more difficult and expensive. As transistor dimensions approach physical and manufacturing limits, simply shrinking components no longer guarantees the same gains in speed, efficiency or affordability. At the same time, autonomous-driving software is becoming more complex, creating a problem that cannot be solved by scaling conventional processors alone.
The authors argue that the answer will require hardware–software codesign, in which algorithms and chips are developed together rather than treated as separate layers. In a traditional approach, software is written for a general-purpose processor, and hardware is expected to execute it efficiently enough. Codesign reverses that assumption by examining how the structure of an algorithm can be adapted to the strengths of a particular computing architecture, while the architecture is optimized for the algorithm’s most demanding operations. For autonomous vehicles, this could mean designing specialized processing units for neural-network inference, sensor fusion, planning and control, while simultaneously modifying models to reduce unnecessary computation without compromising safety.
One important challenge is the balance between flexibility and efficiency. General-purpose central processing units can execute a wide range of tasks, making them adaptable when software changes. However, they are often less efficient than specialized hardware for repetitive workloads such as convolution, attention mechanisms or large-scale tensor operations. Graphics processing units and neural-processing accelerators can perform many operations in parallel, improving throughput, but they may consume significant energy and introduce new programming and verification challenges. Domain-specific architectures offer another path, tailoring the data paths, memory organization and arithmetic units of a chip to the requirements of autonomous-driving workloads. Their advantage is efficiency; their risk is that they may become outdated as algorithms evolve.
Memory is at the centre of this problem. In many artificial-intelligence systems, moving data between memory and processing units consumes as much or more energy than performing the calculations themselves. Autonomous-driving chips must repeatedly access sensor streams, neural-network parameters, intermediate feature maps and decision-making data. If these values travel long distances across a chip, the resulting communication consumes time and power. Engineers are therefore exploring architectures that place memory closer to computation, reducing data movement and improving the energy efficiency of inference. The Perspective highlights emerging memory technologies and new ways of integrating logic and memory as potential tools for overcoming what is increasingly described as the “memory wall.”
New materials and three-dimensional integration could further reshape the design of these systems. Advanced semiconductor materials may offer improved electrical, thermal or optical properties compared with conventional silicon-based approaches, potentially supporting faster switching or more efficient communication. Heterogeneous integration allows different types of components—such as logic, memory, sensors and specialized accelerators—to be combined in a single package or system. Monolithic three-dimensional integration goes further by building multiple active device layers vertically, shortening connections and increasing computing density. In principle, this approach could place processing resources and memory much closer together, but it also introduces difficult problems involving heat removal, manufacturing yield, reliability and testing.
Safety makes the design challenge even more demanding. An autonomous-driving chip must do more than deliver high benchmark scores; it must provide predictable and verifiable behaviour. Critical functions may need to continue operating even if a component fails, while noncritical workloads may have to be deprioritized when computing resources become constrained. Hardware and software must support fault detection, redundancy, secure updates and real-time scheduling. Neural networks themselves can be difficult to interpret and formally verify, particularly when they are exposed to rare or unfamiliar situations. This means chip designers, automotive engineers and artificial-intelligence researchers must consider safety mechanisms from the earliest stages of architecture development rather than adding them after performance targets have been met.
Cost will ultimately determine how widely advanced autonomous systems can be deployed. Premium vehicles may accommodate expensive processors, extensive sensor suites and redundant computing platforms, but mass-market vehicles require a very different economic equation. A commercially viable chip must provide enough performance for demanding workloads while remaining affordable to manufacture, integrate and maintain. It must also support software updates over a vehicle’s long service life, even as models and safety requirements change. The authors suggest that future success will depend on balancing computational capability with energy efficiency, reliability, programmability and manufacturing practicality—not on maximizing any single specification.
The emerging contest over autonomous-driving chips is therefore becoming a contest over complete computing ecosystems. Semiconductor manufacturers, vehicle companies, artificial-intelligence developers and materials researchers will need to work across traditional industry boundaries. The next generation of intelligent vehicles may rely on a combination of specialized accelerators, advanced memory, three-dimensional integration and software optimized for the precise architecture on which it runs. Such systems could make it possible to process richer sensor data, execute more capable models and respond more quickly without exceeding the physical and economic limits of the vehicle. The central message of the Perspective is clear: autonomous driving will not be unlocked by one faster chip. It will require a coordinated transformation of materials, devices, architectures, algorithms and safety engineering into a single intelligent platform.
Subject of Research: Autonomous driving chips and hardware–software codesign for safe, real-time, energy-efficient intelligent vehicles
Article Title: Autonomous driving chips
Article References: Lu, Q., Wu, S., Liu, Y. et al. “Autonomous driving chips.” Nature Reviews Electrical Engineering (2026). https://doi.org/10.1038/s44287-026-00319-1
Image Credits: AI Generated
DOI: 10.1038/s44287-026-00319-1
Keywords: autonomous driving, automotive semiconductors, artificial intelligence, hardware–software codesign, domain-specific architectures, neural-network accelerators, advanced memory, three-dimensional integration, edge computing, vehicle safety
