A new silicon photonic architecture could make optical convolution far denser and more adaptable, offering a potential path toward faster hardware for artificial intelligence, machine vision, and high-throughput signal processing. Developed by Professor Yikai Su’s research team at Shanghai Jiao Tong University, the system uses a spatiotemporal photonic interleaving network, or SPIN, to perform convolution by coordinating optical signals across both time and wavelength. The approach is designed to overcome one of the central obstacles in integrated photonics: increasing computational capacity without multiplying the number of optical paths, control circuits, and waveguides on a chip.
Convolution is a fundamental operation in image recognition and neural networks. It involves sliding a small numerical kernel across an image and calculating weighted sums that reveal features such as edges, contours, and textures. Electronic processors can perform these calculations efficiently, but their performance is increasingly limited by the movement of data between memory, processing units, and communication interfaces. Photonic processors offer a different strategy. Because multiple optical signals can travel simultaneously through the same physical system using separate wavelengths, time slots, or spatial channels, light can carry and process large volumes of data in parallel.
Existing photonic approaches, however, involve significant compromises. Mach-Zehnder interferometer meshes can implement programmable matrix operations, but large meshes require extensive chip area, electrical control, and calibration. Microring-resonator systems are more compact, yet their optical responses can shift with temperature and manufacturing imperfections. Diffractive optical elements and metasurfaces may achieve exceptional density, but their functions are often fixed after fabrication. SPIN addresses these limitations by combining wavelength multiplexing with shared time delays, allowing one optical structure to perform multiple convolution operations while retaining reconfigurability.
At the heart of the architecture is a recursive tree made from cascaded optical interleavers. The input is first serialized into a high-speed waveform and broadcast across multiple wavelength carriers. Each carrier then passes through a carefully selected sequence of delay segments. These delays shift portions of the waveform relative to one another, creating the aligned sliding windows required for convolution. Once the optical samples are synchronized, programmable weighting elements apply the kernel coefficients. The weighted signals are then combined through incoherent optical summation, and the resulting signed value is recovered electronically by subtracting a baseline contribution.
The most important advance lies in how the network reuses delay resources. In a conventional architecture, every pair of operands may require its own independent delay path. As the kernel becomes larger, the number and length of those paths can grow rapidly, producing a quadratic increase in total waveguide length. SPIN instead places longer delays near the beginning of its interleaver tree, where they can be shared by many downstream wavelength channels. According to the researchers, this changes the waveguide-length scaling from O(K²) to O(K log₂ K), where K represents the number of convolution operands. The number of actively controlled weighting elements scales approximately linearly, as O(K).
The team demonstrated the concept experimentally using a proof-of-concept chip fabricated on a commercial 220-nanometer silicon-on-insulator platform. The device contains a three-stage cascaded interleaver network supporting eight wavelength channels. Operating at 49 gigabaud, the chip processed representative 2 × 2 convolutions applied to handwritten digits from the MNIST dataset. The optical output waveforms closely matched digital reference calculations, producing correlation coefficients above 0.98. When reconstructed as image feature maps, the results clearly emphasized the contours and structural boundaries of the digits.
The researchers also showed that the same physical core could support multiple optical tasks through wavelength-domain resource allocation. In one demonstration, 16 optical carriers were divided into wavelength groups, allowing different image batches and convolution operations to share the SPIN hardware. This is significant because photonic accelerators must often balance several competing forms of parallelism. Available wavelengths can be assigned to increase kernel size, process more image patches at once, support different kernel geometries, or run several tasks simultaneously. SPIN’s architecture allows these choices to be made through optical routing and configuration rather than by fabricating a separate circuit for every workload.
To test structural flexibility, the researchers implemented a 2 × 4 convolution kernel on natural images from the USC-SIPI database. Unlike a fixed diffractive optical processor, the SPIN system can alter its convolution pattern by changing how wavelength channels and delay segments are used. This programmability could make the architecture useful in applications where image-processing tasks change frequently, including machine vision, autonomous systems, scientific imaging, and communications signal analysis.
The projected capacity is also notable. If the available optical spectrum is fully utilized, the authors estimate that a single SPIN core could approach 29.7 tera operations per second. Reaching that figure in a complete system will require careful integration of modulators, photodetectors, frequency-comb or multiwavelength light sources, calibration electronics, and high-speed data interfaces. Optical losses, wavelength stability, thermal drift, and the conversion between optical and electrical signals will remain important engineering challenges. Even so, the experimental results suggest that shared spatiotemporal routing can provide a practical way to raise photonic computing density without relying on ever-larger arrays of independent optical paths. By moving part of the scaling burden from physical space into the wavelength domain, SPIN points toward compact, high-throughput, and reconfigurable optical processors for the next generation of artificial intelligence hardware.
Subject of Research: Not applicable
Article Title: Scalable spatiotemporal interleaving network for high-density integrated photonic convolution
News Publication Date: 23-Jul-2026
Web References: Opto-Electronic Science article
References: DOI: 10.29026/oes.2026.260018
Keywords
Integrated photonics, optical computing, photonic convolution, artificial intelligence, machine vision, wavelength multiplexing, silicon photonics, spatiotemporal interleaving, neural networks, optical accelerators
