ReSNNance turns Python spiking neural networks into working FPGA circuits automatically

Spiking neural networks promise to bring the frugal elegance of biological brains to edge devices, but turning a trained spiking model into a working circuit has long demanded two rare skill sets at once: deep neuromorphic-computing knowledge and hardware-description expertise. A team at Universidad Politécnica de Madrid has now built a bridge across that divide. Their open-source framework, ReSNNance, automatically converts high-level Python descriptions of spiking neural networks into synthesizable VHDL, the hardware language that field-programmable gate arrays (FPGAs) understand. The work, published in Frontiers in Neuroscience, demonstrates the complete workflow on an AMD Zynq UltraScale+ FPGA, where two spiking networks for MNIST digit classification were translated, verified and implemented without a single line of hand-written hardware code.

Spiking neural networks differ fundamentally from the conventional artificial neural networks behind today’s machine-learning boom. Instead of passing continuous values between layers, they communicate through discrete spike events and incorporate temporal dynamics into their neuron models, a scheme far closer to biological neural processing. Because their activity is sparse, event-driven hardware can skip unnecessary computation and data movement, which makes them attractive for real-time inference on energy-constrained devices. Yet the Madrid team is careful about the hype: the efficiency advantages depend strongly on network architecture, encoding method, workload and implementation platform, and cannot simply be assumed for every application. Real energy savings, they stress, must be demonstrated with physical implementations rather than inferred from spike sparsity alone.

The gap between software and silicon is where most spiking projects stall. A broad ecosystem of libraries, many built on PyTorch, can simulate and train spiking networks, but moving a trained model onto hardware typically requires a separate design flow. Engineers must decide on data representation, neuron and synapse organization, memory allocation, communication schemes and temporal execution before a synthesizable circuit emerges. Existing frameworks that partially automate this translation differ in their input representations, supported neuron models, synthesis methodologies and dependence on vendor-specific tools, leaving a need for accessible workflows that keep the software model connected to the generated hardware while allowing the result to be inspected and customized at the hardware-description level.

ReSNNance attacks this problem with a Python-based workflow. Users define the network architecture, neuron parameters, numerical precision and target configuration, and the framework generates the corresponding hardware modules, parameter files and interconnections. Internally, a network is represented as a Model composed of an ordered sequence of Layer objects, each linked to a parameterized VHDL template. During compilation, the toolchain maps the network topology, trained weights and additional parameters onto these templates and stitches the modules together sequentially using a network-level template, producing a standalone synthesizable implementation. The Jinja template engine substitutes network parameters and structural information into the hardware templates, and the framework can even generate build environments for synthesis with AMD Vivado and simulation with GHDL.

The current implementation supports sequential feed-forward networks built from fully connected Dense layers, two-dimensional Conv2D layers and average-pooling layers, all based on a simplified fixed-point leaky integrate-and-fire (LIF) neuron whose decay behavior is configured through an integer parameter. A distinctive feature is the input-conversion layer, which transforms non-spiking inputs such as images into spike trains through discrete-time stochastic rate encoding. The circuit stores 8-bit fixed-point input values in RAM and, at each simulation time step, performs a Bernoulli trial: a pseudorandom number generated by a low-resource linear feedback shift register (LFSR) is compared against a probability threshold proportional to the input pixel value, producing a spike whenever the random value falls below the threshold. This scheme approximates a homogeneous Poisson process while consuming minimal hardware resources.

Connecting the framework to the training world required solving a subtle software-hardware mismatch. Networks are trained in SpikingJelly, a PyTorch-based environment for defining, training and simulating spiking models, but the standard SpikingJelly LIF neuron does not directly reproduce the update order and parameterization of the simplified LIF neuron in the ReSNNance hardware templates. SpikingJelly expresses decay with a real-valued time constant, whereas the hardware uses an integer parameter, and the order in which synaptic integration and membrane-potential decay are applied differs. The team therefore developed a hardware-equivalent neuron class, RsnnNode, that inherits from the SpikingJelly base node and implements the hardware-compatible update through its neuronal_charge function, ensuring the software model follows the same numerical update employed by the generated VHDL. A corresponding BlockContainer pairs each synaptic layer with an RsnnNode and provides a conversion function that generates the ReSNNance layer representation, carrying over trained weights, neuron parameters and connectivity information.

Before synthesis, the generated hardware was functionally verified through VHDL simulation using self-checking testbenches. Deterministic input spike trains and quantized parameters were applied to both the ReSNNance software model and the generated VHDL implementation, and their output spike trains were compared cycle by cycle over 25 simulation time steps across representative layer sizes, convolutional kernels and numerical formats. No mismatches were observed between software and VHDL output spike trains for any evaluated configuration, a result the authors regard as essential evidence that the automatic translation preserves the trained model’s behavior exactly.

The first case study, a spiking LeNet-5 convolutional network, demonstrated the seamless integration of fully connected, convolutional and pooling hardware modules into a complete architecture. Weights were quantized to signed 8-, 6- and 4-bit representations, revealing clear design trade-offs. Reducing precision from 8 to 6 bits cut look-up table and flip-flop utilization by roughly 12 percent with only a 0.20 percentage-point drop in accuracy, from 99.06 to 98.86 percent. At 4 bits, resource utilization fell by about 35 percent for LUTs and 26 percent for flip-flops while the maximum operating frequency rose by nearly 23 percent to 356.9 MHz, at the cost of a 0.89 percentage-point accuracy reduction. Remarkably, none of the configurations required dedicated DSP blocks or block RAM: because synaptic contributions are accumulated upon spike arrival rather than computed through multiply-accumulate operations, the event-driven architecture eliminates the need for dedicated arithmetic resources, mapping weights and neuron states to distributed logic instead.

The second case study pushed the framework to its limits with a large fully connected network containing 1,237,152 weights, arranged as 784-784-784-10 to match the MNIST input dimensions. Hidden layers were added progressively until the available FPGA resources were exhausted. At 8-bit precision, the implementation occupied 88.50 percent of the device’s look-up tables while maintaining 98.52 percent classification accuracy. Quantization again proved powerful: dropping to 4-bit weights halved LUT utilization and raised the maximum operating frequency to 192.4 MHz with only a 0.34 percentage-point accuracy penalty. Power analysis, based on switching activity captured from post-implementation simulation with real MNIST samples, showed logic power falling from 750 milliwatts at 8-bit precision to 307 milliwatts at 4 bits, while static device power remained nearly constant at around 620 milliwatts. Complete inference over 25 simulation time steps required just 416.7 microseconds for this network, and 3675.7 microseconds for the LeNet-5 pipeline.

Compared with existing FPGA-based spiking frameworks such as NeuroFlow, SyncNN, E3NE and Spiker+, ReSNNance stands out for compiling models directly from a Python front-end into plain synthesizable VHDL without relying on high-level synthesis or hand-crafted RTL libraries, and for being the only evaluated framework whose implementations rely exclusively on distributed memory. The authors acknowledge limitations: the current version supports only sequential feed-forward architectures with a simplified LIF neuron, recurrent connections and alternative neuron models are not addressed, and all results were obtained on a single FPGA device with the AMD Vivado toolchain. The practical network size remains constrained by the resources, routing capacity and timing characteristics of the target device. Still, the modular organization provides a basis for incorporating additional hardware templates, neuron models, layer types and memory architectures without changing the core software-to-VHDL approach. For researchers exploring neuromorphic edge computing, ReSNNance offers a practical path from software-defined spiking models to functional silicon, with the generated VHDL remaining readable and configurable so hardware designers can inspect, modify and integrate the circuits into larger systems.

Subject of Research: Neuromorphic Computing

Article Title: ReSNNance: an HDL generation framework for spiking neural networks

Article References: López-Asunción, S., Bermúdez-Martín, C., Ituero, P., & Lopez-Vallejo, M. (2026). ReSNNance: an HDL generation framework for spiking neural networks. Frontiers in Neuroscience, 20, Article 1958451. https://doi.org/10.3389/fnins.2026.1958451

Image Credits: AI Generated

DOI: 10.3389/fnins.2026.1958451

Keywords: spiking neural networks, FPGA, VHDL, neuromorphic computing, edge computing, ReSNNance, hardware generation, generation, framework, spiking, neural, networks