Researchers at KAIST have unveiled a groundbreaking solution to one of the most persistent challenges in semiconductor technology: the electrical bottleneck caused by contact resistance. This phenomenon, which occurs at the interface where metal electrodes meet semiconductors, significantly hampers device performance and increases power consumption. By engineering a novel, monolithic structure in a two-dimensional (2D) material, the team has for the first time directly observed uninterrupted charge transport, promising a revolutionary leap in semiconductor efficiency.
The research team, co-led by Professors Seungbum Hong and Kibum Kang from KAIST, in collaboration with Professor Sung Beom Cho’s group at Sungkyunkwan University, focused on developing a continuous interface within an ultrathin 2D material. Their innovative approach diverges from conventional methods that place metal contacts directly on top of semiconductors, which inherently produce high contact resistance. Instead, the team synthesized a seamless structure combining semi-metallic and semiconducting regions in a single atomic layer of platinum diselenide (PtSe₂).
This semi-metallic-to-semiconducting transition within the same atomic plane eliminates the abrupt material boundary responsible for scattering and resistance. The monolithic architecture allows electrons to flow freely across the internal interface without the disruptions typical of metal–semiconductor junctions. Using atomic force microscopy (AFM) equipped for nanoscale electrical measurements, the researchers visualized current pathways at an unprecedented resolution, confirming that charge transport remained smooth and continuous.
The ability to directly image and verify unobstructed charge movement across the semi-metallic and semiconducting domains is a first in the field. This experimental evidence substantiates the hypothesis that a monolithic interface can bypass the electrical bottlenecks that have long constrained device miniaturization and efficiency. Moreover, the team demonstrated stable electrical control by modulating the semiconducting region with an applied electric field, an essential feature for practical device applications.
The implications of this discovery are profound. As semiconductor devices continue to shrink and integrate into complex systems such as artificial intelligence processors and ultra-low-power electronics, mitigating contact resistance is critical. The KAIST-led innovation lays the groundwork for next-generation semiconductors that could operate with significantly enhanced speed, reduced energy loss, and improved scalability.
Published in the July 2026 issue of the journal Matter, this study sets a new benchmark for materials science and nanotechnology research. The work not only advances fundamental understanding of 2D material interfaces but also opens a promising path for engineering efficient and reliable semiconductor contacts at the atomic scale. Such progress is poised to accelerate the development of cutting-edge electronics that meet the demands of tomorrow’s technologies.
This research was supported by the STEAM Research Program and the Nanomaterials Technology Development Program of the Ministry of Science and ICT and the National Research Foundation of Korea, underscoring the strategic importance of advancing semiconducting materials through innovative fundamental studies.
Subject of Research: Semiconductor physics and two-dimensional materials
Article Title: Nanoscale imaging of charge transport across the semimetal-semiconductor interface in monolithic platinum diselenide
News Publication Date: 1-Jul-2026
Web References: 10.1016/j.matt.2026.102873
Image Credits: KAIST
Keywords
Two-dimensional materials, Semiconductor devices, Contact resistance, Charge transport, Platinum diselenide, Atomic force microscopy, Nanotechnology, Semiconductor interfaces, Electrical bottleneck, Monolithic structure
