Stacking semiconductor chips like skyscrapers to enhance performance

A team of researchers from POSTECH (Pohang University of Science and Technology) in South Korea has unveiled a groundbreaking technique for stacking more than ten ultrathin semiconductor chips, each approximately one-fifth the thickness of a human hair. Led by Professor Seok Kim and Ph.D. candidate Uhyeon Kim, in collaboration with Dr. Hohyun Keum of the Korea Institute of Industrial Technology (KITECH), the group developed an innovative process combining transfer printing and in-situ metallic bonding that achieves an integration density nearly four times greater than current commercial high-bandwidth memory (HBM) solutions.

Artificial intelligence applications—from ChatGPT to autonomous vehicles—require the handling of massive data streams at unprecedented speeds, challenging engineers to overcome the physical limits of chip design. Rather than expanding chip area laterally, semiconductor engineers are stacking chips vertically, much like constructing high-rise apartments instead of sprawling single-story buildings in crowded urban areas. The HBM technology pivotal to AI accelerator performance stacks multiple memory chips, yet reliably stacking such ultrathin chips has posed a significant fabrication challenge.

Chips thinner than several tens of micrometers become fragile and prone to bending, warping, and fractures, complicating their assembly. The difficulty intensifies with each additional layer, as the delicate chips resist alignment and structural integrity, similar to how rice paper wrinkles easily compared to thick cardboard. Conventional packaging methods like flip-chip bonding and grinding-based thinning struggle with precision and damage control at these thickness scales.

To address these challenges, the POSTECH-KITECH team harnessed the stable mechanics of transfer printing—precisely placing chips on target substrates—and simultaneously performed in-situ metallic bonding during transfer. This integrated approach consolidates chip placement, bonding, and electrical interconnectedness into a single low-temperature, low-pressure process, minimizing warpage and interlayer misalignment.

The researchers validated their method with ultrathin silicon chips around 14 micrometers thick featuring vertical electrical signal paths and lateral redistribution wiring, optimizing them for multilayer stacking. They demonstrated stacking upwards of ten chips while maintaining exceptional alignment accuracy and significant suppression of structural warping, an achievement that surpasses the integration density of conventional 12-layer HBM.

With an integration density about four times higher than existing solutions, this technology holds promise for a new generation of AI semiconductors and memory devices. Beyond memory, the method’s precision and scalability could influence heterogeneous chiplet systems and emerging micro-LED display manufacturing, indicating broad technological impact.

Prof. Seok Kim highlighted the potential for this development to serve as a cornerstone in next-generation AI and memory architectures demanding extreme integration densities. Dr. Hohyun Keum underscored its applicability across semiconductor and display fabrication, emphasizing the micrometer-scale precision alignment and bonding innovations.

Supported by Korea’s National Research Foundation through dedicated semiconductor R&D programs, this advance signals a transformative leap in overcoming physical limits of vertical chip integration, setting the stage for high-performance, compact electronic systems crucial for future AI-driven technologies.

Keywords

Ultra-thin chips, Transfer printing, In-situ bonding, High-bandwidth memory, Vertical integration, Semiconductor packaging, AI accelerators, Microelectronics, Chip stacking, Semiconductor manufacturing