Artificial intelligence is moving off the cloud and onto the devices people use every day, but that shift comes with a stubborn engineering problem: edge devices often do not have the energy, memory or processing power required to run sophisticated AI efficiently. Researchers at the University of Massachusetts Amherst have now demonstrated a system that tackles the problem from both directions at once, redesigning the AI algorithm and the hardware that executes it. In a proof-of-concept language-identification task, their platform achieved 95.24 percent accuracy while reducing computing resources by 90 percent. The result represents one of the strongest demonstrations yet of hyperdimensional computing implemented on an emerging hardware platform, and could point toward a new generation of low-power AI systems capable of processing information locally.
Edge computing refers to the practice of analyzing data near the point where it is generated rather than sending everything to a remote data center. Smartphones, cameras, vehicle interfaces, navigation systems, smart speakers, home automation hubs and industrial sensors increasingly rely on this approach because local processing can reduce delays, limit data transfers and improve privacy. Yet the benefits come with strict physical constraints. Unlike a data center, an edge device may operate with a small battery, limited memory and a compact processor that cannot dissipate much heat. Every calculation consumes energy, and repeated movement of information between memory and a separate processing unit can become one of the largest sources of waste. These limitations are especially significant for applications involving human language, where a device may need to identify, translate or interpret spoken or written words in real time.
The UMass Amherst team, led by Qiangfei Xia, the Dev and Linda Gupta Professor of Electrical and Computer Engineering and head of the university’s Nanodevices and Integrated Systems Lab, pursued a strategy known as hardware-algorithm co-design. Conventional AI development typically begins with an algorithm and then deploys it on commercially available processors, forcing the hardware to accommodate the computational demands of the software. Xia’s group instead designed the computing method and the physical system together. That allowed the researchers to select an algorithm suited to the unusual properties of their hardware while building circuitry specifically to perform the operations the algorithm needs. The approach is important because emerging devices are not simply cheaper or smaller versions of conventional processors; they behave differently, and those differences can become useful when the system is designed around them.
At the center of the platform is hyperdimensional computing, or HDC, a brain-inspired approach that represents information with high-dimensional mathematical patterns rather than relying exclusively on precise numerical values. In a typical HDC system, words, symbols or other features are encoded as long vectors containing many elements. Information is then manipulated through operations such as binding, bundling and similarity comparison. Because the representation is distributed across many dimensions, the system can often tolerate noise or small errors without losing the identity of the underlying pattern. This makes HDC attractive for edge applications, where exact numerical calculations may be expensive but rapid classification is essential. For language identification, the system can transform features extracted from written text into high-dimensional representations and compare them with patterns associated with different languages.
The hardware executing these operations is an analog in-memory computing system built from memristive crossbar arrays. A memristor is an electronic component whose conductance can be adjusted and retained, allowing it to function as a compact form of nonvolatile memory. In a crossbar array, memristors are arranged at the intersections of perpendicular electrical lines. When voltages are applied to the rows, the resulting currents on the columns naturally perform multiply-and-accumulate operations according to the conductance values stored in the devices. Instead of repeatedly moving data between a memory chip and a processor, the system carries out computation where the data reside. This can substantially reduce communication overhead, energy consumption and latency, which are major bottlenecks in conventional von Neumann computer architectures.
The researchers also exploited a property that is normally regarded as a weakness of memristive hardware: intrinsic device variability. Individual memristors do not behave with perfectly identical conductance values, and their electrical responses can contain a degree of randomness. For many computing applications, that variability must be minimized or corrected. Xia’s team used it as a source of useful randomness for encoding language features. The natural variations in the memristive array help generate high-dimensional patterns without requiring a separate, energy-intensive random-number-generation process. In effect, the researchers turned an imperfection in the physical devices into a computational resource. This is a defining feature of the work: rather than forcing emerging hardware to imitate idealized digital components, the system incorporates the hardware’s real-world behavior into the design of the algorithm.
In testing, the resulting system identified languages with 95.24 percent accuracy and used 90 percent fewer computing resources than the relevant conventional approach, according to the researchers. The demonstration involved written language, but its broader significance lies in showing that encoding and inference can be performed together on a compact memristive system-on-chip. Language identification is a demanding but clearly defined task: the device must extract patterns from text, represent them in a form suitable for comparison and determine which language most closely matches the input. Performing those stages close to the data source could allow future devices to respond more quickly while reducing the need to transmit sensitive information to the cloud. The same architecture could potentially support other classification and recognition tasks in which approximate, robust pattern matching is more valuable than high-precision numerical calculation.
The achievement builds on a sequence of developments in Xia’s laboratory, beginning with experiments on small memristive crossbar arrays. The central idea emerged in 2019, when Daniel Belkin, then an undergraduate research fellow at UMass Amherst, began studying one of these arrays. Progress toward a practical language-processing demonstration required improvements across several layers of the technology, including analog memristor devices, circuits that integrate memristors with conventional CMOS electronics, crossbar-array architecture and machine-learning methods. The researchers say that only after the technology reached the system-on-chip level did it become feasible to demonstrate language processing in an integrated platform. The same chip has also been used in earlier work involving radio-frequency signal processing and smart sensing, suggesting that a single memristive architecture may be adaptable to multiple edge-AI applications.
The next challenge is to determine how far the system can move beyond written text. Xia and his collaborators believe that the platform could eventually process spoken languages, opening a path toward more energy-efficient natural-language processing in phones, vehicles, smart speakers and robots. A speech-capable version would need to handle additional steps, including acoustic feature extraction, temporal variation and background noise, but the underlying principle would remain the same: encode information into high-dimensional patterns and process those patterns directly inside analog memory. The project also highlights the increasingly interdisciplinary nature of AI hardware development. The collaboration brought together researchers from UMass Amherst, the University of Tennessee Knoxville, the University of Southern California and TetraMem Inc., combining expertise in devices, circuits, algorithms, architecture and systems. The work is published in Nature Communications, while Xia and J. Joshua Yang disclose that they are co-founders and paid consultants of TetraMem.
Subject of Research: Not applicable
Article Title: Hyperdimensional in-memory computing with analogue memristive crossbar arrays
Web References: https://doi.org/10.1038/s41467-026-76067-5
References: Nature Communications, DOI: 10.1038/s41467-026-76067-5
Image Credits: Alexia Cota
Keywords
Artificial intelligence, edge AI, hyperdimensional computing, analog in-memory computing, memristors, memristive crossbar arrays, language identification, low-power computing, neuromorphic hardware, University of Massachusetts Amherst
