Memory Chip Becomes Ultrafast Ising Machine for Hard Optimization Problems

A chip that looks, in many respects, like an ordinary memory device has just demonstrated one of the fastest and most energy-efficient approaches yet to a class of problems that plague engineers across the computing industry. Writing in Nature Electronics, a team led by Weisheng Zhao of Beihang University reports a spintronic Ising machine built from CMOS-integrated magnetoresistive random-access memory, or MRAM, whose individual spins can be updated in as little as 0.3 nanoseconds. With 96,000 spins on a single chip, the machine tackles combinatorial optimization problems that grow exponentially harder as they scale, offering a hardware path around the limitations of conventional processors.

Combinatorial optimization is everywhere in modern technology. Designing a chip’s wiring layout, routing vehicles through a delivery network, scheduling flights, and assigning radio frequencies all belong to this family of problems, in which the goal is to find the best configuration from an astronomically large set of possibilities. Many of these tasks are NP-hard, meaning that no known algorithm can solve them efficiently as they grow. Classical computers, built on the von Neumann architecture that separates memory from processing, grind through such problems by evaluating candidate solutions one after another, and the cost quickly becomes prohibitive.

Ising machines take an entirely different approach. They are physical systems engineered to mimic the Ising model, a mathematical framework from statistical physics in which each of many interacting binary variables, called spins, settles into a state that minimizes the total energy of the system. Because any combinatorial optimization problem can be mapped onto such an energy-minimization landscape, a well-engineered Ising machine can let physics do the searching: spins flip stochastically, interact with their neighbors, and collectively relax toward low-energy configurations that correspond to good, and sometimes optimal, solutions. The concept has been realized in quantum annealers, optical platforms built from lasers and fibers, and various electronic chips, each with its own trade-offs between speed, scale, and programmability.

The new machine, which the researchers call VSIM, stands out for the speed at which its spins can change state. At the heart of each spin is a magnetic tunnel junction, the same nanoscale element that stores bits in MRAM. Rather than switching deterministically between two stable states as memory cells do, the device exploits the voltage-controlled magnetic anisotropy effect, in which an applied voltage alters the energy barrier that separates the two magnetic orientations. By tuning the width of a voltage pulse, the team can dial the probability that a single pulse flips the junction anywhere from zero to one hundred percent. That probabilistic switching is exactly what an Ising machine needs, because stochastic spin updates allow the system to escape local energy minima where deterministic algorithms become trapped.

The numbers are striking. Spin updates take between 0.3 and 1 nanosecond, firmly in the sub-nanosecond regime that has eluded most alternative platforms, and each update consumes less than 40 femtojoules per spin. Because the magnetic tunnel junctions are integrated directly with CMOS circuitry, the machine combines the density and manufacturability of standard semiconductor technology with the intrinsic randomness of nanoscale magnetism. The write currents involved are low, another consequence of the voltage-based control mechanism, and the all-to-all connectivity on the chip means any spin can in principle influence any other, which matters greatly for faithfully encoding the interaction structure of real optimization problems.

To demonstrate that the machine is more than a laboratory curiosity, the team mapped two problems drawn directly from electronic design automation, the software domain that underpins the entire semiconductor industry. The first is global routing, the task of deciding how to connect millions of circuit components across a chip’s wiring grid while minimizing wire length and congestion. The second is layer assignment, which determines which of several metal layers each wire segment should occupy. Both are commercially critical steps in chip design, and both were encoded as Ising Hamiltonians and solved on the hardware. In an era when chip design complexity is straining conventional design automation tools, hardware solvers aimed squarely at this workflow have obvious practical appeal.

Benchmarked against standard Max-cut test problems, a canonical yardstick in the Ising machine literature, the chip delivered high-quality solutions at a system-level energy efficiency of 1.92 times ten to the fifth solutions per second per watt. That figure reflects not just the raw speed of the magnetic tunnel junctions but the whole pipeline: an FPGA board configures the couplings, drives the annealing schedule, and reads out the final spin configuration. The researchers also examined how robustly the machine performs in the face of device-to-device variation, an unavoidable reality of nanoscale fabrication, finding that solution quality holds up well provided the single-pulse switching probability stays above roughly sixty percent.

The work lands in a crowded and fast-moving field. Quantum annealers have demonstrated computations on thousands of superconducting qubits, coherent Ising machines built from optical fiber loops have handled 100,000-spin problems, and a parade of CMOS-based annealing chips has appeared at recent circuits conferences. Spintronic approaches, in which the spin itself is the stochastic element, have generally been limited to far smaller arrays. What distinguishes this demonstration is the combination of scale, at 96,000 spins, with sub-nanosecond update speed and full CMOS integration, a trio of attributes that no single previous platform has offered simultaneously.

There remain caveats and open questions. The reported demonstrations, while industrially relevant, are specific problem instances, and scaling the machine to the problem sizes encountered in full-scale chip design will require larger arrays, better coupling precision, and careful management of annealing schedules. The metrics used to compare heterogeneous Ising machines, spanning quantum, optical, and electronic implementations, are themselves still being debated by the community. And like all physics-based solvers, Ising machines provide high-quality solutions rather than guaranteed optima, which may or may not suffice depending on the application.

Even so, the demonstration points toward a future in which the memory devices inside every processor become active computational elements. The voltage-controlled magnetic tunnel junction at the center of this work is already the storage element of a commercial memory technology, which means the path from laboratory demonstration to embedded accelerator runs through established fabrication infrastructure rather than exotic physics. If spintronic Ising machines can keep pace in scale, they could take their place alongside GPUs and dedicated AI accelerators as specialized hardware for the optimization workloads that quietly underpin modern technology. The team has released its source data and code to the community, an invitation for researchers worldwide to stress-test this new class of machine against the hardest problems they can find.

Subject of Research: A CMOS-integrated spintronic Ising machine using magnetoresistive memory for fast, energy-efficient combinatorial optimization

Article Title: An Ising machine for combinatorial optimization based on sub-nanosecond CMOS-integrated magnetoresistive random-access memory

Article References: An Ising machine for combinatorial optimization based on sub-nanosecond CMOS-integrated magnetoresistive random-access memory. (n.d.). https://doi.org/10.1038/s41928-026-01700-6

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01700-6

Keywords: Ising machine, combinatorial optimization, spintronics, MRAM, magnetic tunnel junction, voltage-controlled magnetic anisotropy, Nature Electronics, electronic design automation, global routing, Max-cut, probabilistic computing, CMOS integration