Negative Voltage Unlocks Energy-Efficient 2D Memory and In-Memory Computing

Engineers at Purdue University’s Elmore Family School of Electrical and Computer Engineering have proposed a new family of nonvolatile memory cells built on two-dimensional piezoelectric transistors, and the designs report unusually large energy savings over both conventional SRAM and earlier piezoelectric memory concepts. The work, carried out by Jeffry Victor and Sumeet Kumar Gupta and accepted for publication in Frontiers in Electronics in the journal’s Nano- and Microelectronics section, centers on a device known as the piezoelectric field-effect transistor, or PeFET. The central claim of the study is that the PeFET’s unique structure allows memory designers to escape a long-standing trade-off: until now, improving energy efficiency or adding computing capability to the memory came at the cost of how densely the cells could be integrated.

The PeFET combines a piezoelectric or ferroelectric capacitor with a transistor whose channel is made from a two-dimensional material. The ferroelectric layer stores the bit: its electric polarization can be flipped between two stable states, and it holds that state without power, which is what makes the device nonvolatile. Reading the bit exploits a second property of the device. During read, mechanical strain induced in the two-dimensional channel shifts the channel’s bandgap, changing how easily current flows through the transistor. The memory cell therefore integrates bit storage and a strain-based read mechanism in one compact structure, a combination the authors identify as the source of its appeal for high-density, energy-efficient memory.

Earlier PeFET-based memory designs had already shown immense promise as denser and more energy-efficient alternatives to the six-transistor SRAM cells used in on-chip storage. But the Purdue team argues that these earlier designs left significant efficiency unrealized, and that the limitations trace back to how the cells were operated. According to the authors, prior PeFET memories had to sacrifice integration density to improve energy efficiency, or to augment the memory with in-memory computing, the capability of performing arithmetic directly inside the memory array. The new proposal, which the authors call negative-voltage-enabled, or NeVo, designs, attacks the problem by applying negative voltage in a way that significantly reduces the major energy-consuming components of the memory cycle. The researchers present two flavors of PeFET memory built on this principle.

In the authors’ analysis, the proposed cells reduce read energy to 0.08 times that of a conventional 6T-SRAM cell and to 0.03 times that of prior PeFET-based nonvolatile memories. On the write side, the designs reach 0.19 times the energy of 6T-SRAM and 0.53 times that of earlier PeFET designs. Those figures, presented by the authors as design-level results, indicate that the negative-voltage technique addresses the very components that limited the efficiency of previous generations of the technology. The study also identifies the key reasons for the limited energy efficiency of the previous PeFET designs, using those insights to guide the new cell architectures.

The same cells are then recruited for computing. The study shows that the NeVo memories can implement in-memory computing primitives, including addition, subtraction, and multiply-and-accumulate. For these computing tasks, the authors report energy consumption of 0.03 times that of prior PeFET-based designs. Because the approach builds computing on the same cells that achieve high density and high energy efficiency, the authors argue it delivers all three properties simultaneously rather than optimizing one at the expense of the others. The keywords accompanying the article, which include two-dimensional transition metal dichalcogenides, ferroelectrics, strain, deep neural networks, and multiply-and-accumulate, reflect the breadth of the device physics and the intended applications.

As with any design-stage proposal, the reported energy factors come from the authors’ own analysis rather than from fabricated chips, and the final formatted version of the paper is slated to appear soon in Frontiers in Electronics. The article was received on 28 May 2026 and accepted on 14 September 2026, and it is published open access under a Creative Commons Attribution license. The authors note that all claims in the article are solely their own and do not necessarily represent those of their affiliated organizations or the publisher.

Subject of Research: Negative-voltage-enabled energy efficient nonvolatile memories and in-memory computing based on 2D piezoelectric transistors

Article Title: Negative-voltage-enabled energy efficient nonvolatile memories and in-memory computing based on 2D piezoelectric transistors

Article References: Victor, J., & Gupta, S. K. (2026). Negative-voltage-enabled energy efficient nonvolatile memories and in-memory computing based on 2D piezoelectric transistors. Frontiers in Electronics, 7, Article 1894159. https://doi.org/10.3389/felec.2026.1894159

Image Credits: AI Generated

DOI: 10.3389/felec.2026.1894159

Keywords: Negative-voltage-enabled, energy, efficient, nonvolatile, memories, in-memory, computing, based, piezoelectric, transistors, scientific research