In a remarkable stride forward for the future of computing technology, a group of scientists from Peking University, China, has unveiled a groundbreaking reconfigurable integrated photonic chip designed to revolutionize how we process data in the era of artificial intelligence. This innovative chip combines versatility with scalability to operate multiple neural network architectures — including fully connected neural networks (FCNN), convolutional neural networks (CNN), and photonic gated recurrent neural networks (PGRNN) — on a single integrated platform. The experiment not only demonstrates high computational efficiency but also bridges the gap between static and dynamic temporal data processing, heralding a new class of multifunctional photonic computing systems.
The explosion of data and the increasing need for low-power, high-throughput computational systems have pushed researchers to explore photonic computing as a viable alternative to traditional electronic processors. Photonic chips exploit the properties of light to perform computations at extraordinary speeds and with reduced energy consumption. However, integrating various neural network models into a scalable and flexible photonic hardware platform has remained a daunting challenge—until now. The team led by Professor Xiaoyong Hu has succeeded in developing a unified and reconfigurable photonic architecture, featuring microring resonator (MRR) arrays and Mach-Zehnder interferometer (MZI) arrays, which collectively support diverse computational tasks without necessitating separate hardware for each neural network type.
Central to their approach is the use of a fully integrated single soliton optical frequency comb as the light source, providing a broad spectrum of coherent wavelengths with a free spectral range (FSR) of 100 GHz. This frequency comb serves as the backbone of optical multiplexing, offering numerous wavelength channels for simultaneous processing. The MRRs exploit a cross-waveguide coupling design that uniquely permits each unit to toggle between handling static inputs for feedforward computations and dynamic inputs vital for temporal reasoning tasks, all within the same physical device. This dual-input capability dramatically enhances throughput as compared to conventional MRR designs that typically handle only a single input mode.
The flexibility of this architecture is illustrated by its ability to configure itself dynamically for specific neural network tasks. When implementing FCNN models, the resonance wavelengths of MRRs are electrically modulated to encode the network weights, while wavelength detuning introduces the corresponding biases. This allows the wavelength-specific modulation of signals to perform simultaneous multiplication and bias addition entirely in the optical domain. The resultant output signal, capturing the computed neuron activations, is directly detected at the chip’s photodetectors, preserving the advantages of high-speed optical processing with minimal latency.
For convolutional neural networks, the chip leverages the MRR arrays as photonic convolution kernels with scalable multi-channel capability. This design facilitates optically implemented convolutions across multiple wavelengths, thereby accelerating image feature extraction—a core operation in image classification and other computer vision tasks. The team demonstrated this capability by constructing an Inception-like architecture that combines CNN layers with fully connected layers, achieving remarkable classification accuracies of 92.93% on the MNIST dataset and 56.57% on the more challenging CIFAR-10 dataset.
Temporal data processing, which is essential for sequential data such as speech or natural language, is handled through the photonic gated recurrent neural networks (PGRNN). The innovative cross-waveguide MRR configuration accepts concurrent inputs from current and previous states of the network via dual ports, thereby embodying the recurrent nature of the algorithm in physical form. By assigning distinct free spectral ranges (FSRs) to different signal components, the chip avoids crosstalk that typically plagues multi-channel optical systems. This approach proved effective in handling sentiment analysis tasks, achieving an accuracy of 80.81% on the IMDB movie review dataset, and in complex speech recognition setups employing a combination of CNN, PGRNN, and FCNN modules.
The integrated soliton microcomb chip is a pivotal element of this system, generating stable frequency combs with precise and widely spaced frequency lines. This singular optical source simplifies the system by obviating the need for multiple lasers, while ensuring coherence and stability necessary for sensitive photonic computations. Furthermore, the electrical tuning of MRR resonances within arrays enables rapid and flexible reconfiguration of the chip, adapting it to various task requirements from static image recognition to dynamic temporal sequence modeling.
In addition to the demonstrated performance benchmarks, the researchers stress the unparalleled area efficiency of the chip architecture. By enabling dual-path computation within individual MRRs, their design effectively doubles the processing density compared to traditional photonic systems. With an area efficiency reaching 2.45 trillion operations per second per square millimeter (TOPS/mm²) at an operating frequency of 10 GHz, this integrated photonic chip arguably sets a new standard for compact and powerful optical processing units.
This work also advances the frontier of multimodal data processing on photonic hardware. By seamlessly combining FCNN, CNN, and PGRNN architectures, the chip supports complex workflows that mimic human-like cognition, capable of simultaneous image classification, sentiment analysis, and speech recognition. Such versatility not only elevates photonic neural networks from isolated model implementations to holistic computing platforms but also paves the way for new applications in artificial intelligence, edge computing, and real-time signal processing.
Moreover, the approach outlined in this research addresses key scalability concerns that have hampered earlier photonic computing efforts. The use of fully integrated and electrically tunable MRRs in arrays facilitates large-scale implementations without sacrificing computational precision or speed. Coupled with low-power soliton microcomb sources, the chip promises energy-efficient, high-throughput performance that could tackle the ever-growing computational demands of next-generation AI hardware.
The significance of this integrated photonic computing platform extends beyond purely scientific achievement. It delivers a compelling model for the future evolution of computing systems, one where photonics and electronics converge seamlessly to provide unprecedented computational capabilities. This leap is timely, considering the plateauing scalability of traditional silicon-based electronics and the inevitable shift towards hardware accelerators optimized for AI workloads.
In summary, this pioneering research by Professor Xiaoyong Hu and colleagues presents a fully reconfigurable versatile photonic chip that integrates frequency comb technology with advanced MRR and MZI arrays. It achieves high-performance computing across neural network architectures while maintaining compactness and low power consumption. Its ability to handle both static and dynamic tasks, combined with superior area efficiency and scalability, positions it as a potential cornerstone for next-generation photonic AI processors. As photonic technology continues to mature, devices like this may soon bridge the gap between theoretical potential and practical, real-world applications in intelligent systems.
Subject of Research: Integrated photonic computing chips for versatile neural network implementations
Article Title: Reconfigurable Versatile Integrated Photonic Computing Chip
News Publication Date: Not specified in the source text
Web References: https://doi.org/10.1186/s43593-025-00098-6
References: Hu, X., Wang, Y., Liao, K., et al. (2025). Reconfigurable Versatile Integrated Photonic Computing Chip. eLight. https://doi.org/10.1186/s43593-025-00098-6
Image Credits: Yufei Wang, Kun Liao et al.
