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Engineers Design Flexible Language Model Framework for Commercial Chip Design Tools

November 13, 2026
in Science News
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Engineers Design Flexible Language Model Framework for Commercial Chip Design Tools

Engineers Design Flexible Language Model Framework for Commercial Chip Design Tools

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Large language models are expanding their footprint across electronic design automation by augmenting foundational stages of hardware development, including schematic design, simulation, netlist synthesis, and physical place-and-route workflows. Existing methods primarily focus these optimizations within isolated open-source EDA tools and often lack the flexibility to handle multiple domains, such as analogue, digital, and radio-frequency design.

To overcome these integration boundaries, modern semiconductor development environments must reliably interface with proprietary commercial electronic design automation tools. Practical industrial application demands strict adherence to tool-specific operating rules, dynamic assimilation of design outcomes, and continuous compatibility with complex multi-stage workflows.

Addressing this challenge, researchers have introduced a versatile framework that coordinates large language models to produce functional files compatible with commercial design environments. The methodology utilizes detailed power-performance-area reports generated by synthesis tools to systematically drive iterative design optimizations.

The system accomplishes this integration by guiding language models using explicit tool constraints alongside continuous feedback extracted from intermediate design outputs. This directed feedback loop ensures generated files strictly satisfy tool-specific operational rules while converging toward specified user criteria. The practical capabilities of the framework were evaluated across varied physical domains through dedicated case studies focusing on operational transconductance amplifiers, microstrip patch antennas, and field-programmable gate array circuits.

Subject of Research: Language model assisted electronic design automation framework

Article Title: A flexible language model-assisted electronic design automation framework

Article References: Sestito, C., Kontou, P., Verma, P., Dixit, A., Keros, A. D., O’Boyle, M., Bouganis, C.-S., & Prodromakis, T. (2026). A flexible language model-assisted electronic design automation framework. Scientific Reports. https://doi.org/10.1038/s41598-026-75880-8

Image Credits: AI Generated

DOI: 10.1038/s41598-026-75880-8

Keywords: Electronic design automation, Large language models, Commercial EDA tools, Netlist synthesis, Place-and-route, Hardware design, Operational transconductance amplifiers, Microstrip patch antennas, FPGA circuits, Power-performance-area optimization, Analogue circuit design, Digital circuit design, Radio-frequency design, Schematic design, Tool constraints, Feedback-driven optimization

Cite Scienmag News

Scienmag. (November 13, 2026). Engineers Design Flexible Language Model Framework for Commercial Chip Design Tools. https://scienmag.com/engineers-design-flexible-language-model-framework-for-commercial-chip-design-tools/

Scienmag. "Engineers Design Flexible Language Model Framework for Commercial Chip Design Tools." Scienmag, 13 November 2026, https://scienmag.com/engineers-design-flexible-language-model-framework-for-commercial-chip-design-tools/. Accessed 13 November 2026.

Scienmag. "Engineers Design Flexible Language Model Framework for Commercial Chip Design Tools." Scienmag. November 13, 2026. https://scienmag.com/engineers-design-flexible-language-model-framework-for-commercial-chip-design-tools/

Tags: Analogue circuit designCommercial EDA toolsDigital circuit designelectronic design automationFeedback-driven optimizationFPGA circuitsHardware designlarge language modelsMicrostrip patch antennasNetlist synthesisOperational transconductance amplifiersPlace-and-routePower-performance-area optimizationRadio-frequency designSchematic designTool constraints
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