New Optimization Model Prevents Capacity Overestimation in 3D-Stacked HBM Manufacturing

As artificial intelligence reshapes global computing, the memory chips that feed AI accelerators have become some of the most sought-after components in the semiconductor industry. High-Bandwidth Memory, or HBM, is manufactured by stacking multiple DRAM dies into a single three-dimensional package connected through silicon vias, a technique that delivers extraordinary data throughput but also introduces manufacturing complexity far beyond conventional memory production. A new study published in Frontiers in Materials presents a mixed-integer optimization framework that explicitly accounts for the layered structure of HBM during production planning, addressing a subtle but costly flaw in earlier planning models.

The research, conducted by Jeong Woo Kim of the Department of Business Administration at Sunmoon University in the Republic of Korea, focuses on a problem that has largely escaped attention in semiconductor production planning: the conversion of die-level output into package-level capacity. In traditional memory manufacturing, a single wafer yields many individual chips that are packaged and tested one at a time. HBM breaks this linear relationship. Because each finished package contains four, eight, twelve, or sixteen stacked DRAM dies, the number of usable packages is always a fraction of the number of dies produced. Planning models that treat this conversion as a simple one-to-one mapping systematically overestimate how many packages a factory can deliver.

To correct this, the study embeds a discrete stacking factor, denoted Sj, directly into a multi-period mixed-integer linear programming model. The stacking factor is restricted to the commercial HBM configurations of 4, 8, 12, and 16 layers, excluding single- and double-layer structures that represent conventional commodity DRAM rather than true three-dimensional stacked memory. By dividing net die output by the stacking factor for each product code, the model ensures that the die-to-package conversion reflects physical reality. This prevents the over-allocation of resources at the packaging stage, a miscalculation that can lead to wasted energy, misused equipment, and unfulfilled customer orders in high-density stacking facilities.

The framework also refines the treatment of turn-around time, the interval between wafer input and the availability of finished dies. Because HBM fabrication involves roughly 200 to 300 process steps across photolithography, etching, and electrical die sorting, total turn-around times range from 30 to 45 days. When this exceeds the length of a single monthly planning period, naive models can mistakenly assume that wafers input in one month are available for packaging in the same month. The proposed model introduces a ceiling-function-based mechanism that calculates how many prior periods must elapse before a wafer becomes available as work-in-process, preserving physical flow consistency across extended lead times and preventing the model from counting inventory that does not yet exist.

Beyond the baseline formulation, the study develops two extension models that address different operational priorities. The first minimizes production disruption by penalizing month-to-month deviations from the previous confirmed production quantity, smoothing output when customer demand fluctuates. The second minimizes the number of unfulfilled product codes, using a priority-weighted penalty to concentrate shortages into fewer periods rather than spreading small deficits across many months. Together, the three formulations give manufacturers a menu of production policies: maximize demand fulfillment, minimize disruption, or minimize the count of unsatisfied orders, each subject to the same stacking and capacity constraints.

To validate the approach, the study applied the models to a simulated six-month production environment with three manufacturing lines and fourteen distinct HBM configurations derived from four wafer types. The baseline model, solved using the CPLEX optimization solver on a standard desktop computer, produced a total of 554,163 chips over the planning horizon while accurately converting die-level output into package-level demand fulfillment. Product codes based on wafer 4, which carries the highest net die yield of 500 dies per wafer, accounted for approximately 77.2 percent of total output, while low-volume configurations based on wafer 3 contributed less than one percent each.

Under simulated demand fluctuation, where customer requests were randomly scaled between 0.7 and 1.7 times their baseline values, the disruption-minimizing extension revealed a striking asymmetry. Wafer-2-based configurations, which represented about 20.9 percent of total output, absorbed 70.7 percent of total production disruption. In contrast, wafer-4 configurations, despite dominating output, experienced only 4.2 percent of total disruption. This suggests that high-volume configurations benefit from inherent production stability, while low-volume, high-layer products are disproportionately vulnerable to demand volatility, a finding with direct implications for how manufacturers allocate flexible capacity.

Shortage analysis further highlighted the role of specialized stacking facilities. Shortages concentrated in a small number of high-layer code-month combinations, coinciding with saturation of the advanced stacking equipment required for products with eight or more layers. The largest single shortage, 14,353 chips for configuration 2-5 in month four, occurred precisely when specialized facility capacity was exhausted. When the shortage-minimizing extension was applied, the total number of unfulfilled code-month instances dropped from twelve to between six and eight, a reduction of 30 to 50 percent, by consolidating multi-period shortages into fewer, larger deficits rather than distributing them thinly across consecutive months.

The study acknowledges several limitations. Physical sub-processes specific to HBM assembly, including through-silicon-via yield loss, hybrid-bonding alignment tolerances, thermal-compression bonding cycle times, and known-good-die pre-screening, were not explicitly modeled. These mechanisms primarily affect the net die and turn-around-time parameters rather than the structural formulation of the optimization model, meaning they could be incorporated in future work without changing the core framework. The author also notes that as the scale of the problem grows with additional wafer types, production lines, or planning periods, hybridizing the exact CPLEX-based formulation with metaheuristic or machine-learning methods could improve computational tractability.

The broader significance of this work lies in bridging a gap between two research communities. Recent studies on HBM have focused intensely on thermal dissipation, hybrid bonding, and structural configuration, demonstrating that stack configuration non-linearly affects manufacturing yield and process stability. Yet these physical and materials-science insights have rarely been translated into macro-level production planning. By embedding commercial stacking constraints directly into a unified manufacturing logistics model, this research offers a template for how the semiconductor industry can plan production with higher fidelity, ensuring that the promise of three-dimensional stacked memory is matched by equally sophisticated planning on the factory floor.

Subject of Research: Optimization of production planning for 3D-stacked high-bandwidth memory manufacturing

Article Title: Stacking-factor-integrated production planning for 3D-Stacked high-bandwidth memory manufacturing: an optimization approach

Article References: Kim, J. W. (2026). Stacking-factor-integrated production planning for 3D-Stacked high-bandwidth memory manufacturing: an optimization approach. Frontiers in Materials, 13, Article 1926885. https://doi.org/10.3389/fmats.2026.1926885

Image Credits: AI Generated

DOI: 10.3389/fmats.2026.1926885

Keywords: HBM, 3D stacking, semiconductor manufacturing, mixed-integer optimization, production planning, through-silicon via, DRAM, AI chips, capacity planning, CPLEX, supply chain, turn-around time