Magnetic memory chips could crack notoriously hard optimization problems

Combinatorial optimization problems are among the most stubborn challenges in modern computing. From routing delivery fleets and scheduling airline crews to designing integrated circuits and folding proteins, these problems require finding the best possible arrangement out of an astronomically large number of possible configurations. As the number of variables grows, the number of candidate solutions explodes combinatorially, and even the most powerful conventional processors can take impractically long to search exhaustively. Now, as discussed in a News and Views perspective by Hantao Zhang, William A. Borders and Mark D. Stiles published in Nature Electronics, an integrated array of magnetic tunnel junctions, the same nanoscale devices that store bits in modern spin-transfer torque magnetic random-access memory, has been shown to solve model optimization problems based on the Ising model quickly and with low energy consumption.

The Ising model, borrowed from statistical physics, describes a collection of spins that can each point up or down, with interactions that either favor alignment or anti-alignment between neighboring spins. Finding the lowest-energy spin configuration of such a system is mathematically equivalent to a broad class of hard combinatorial problems, a correspondence that Andrew Lucas laid out systematically in a widely cited 2014 paper in Frontiers of Physics. Because of this equivalence, researchers have long been interested in building physical systems, so-called Ising machines, whose natural dynamics drive them toward low-energy states, allowing the hardware itself to perform the search that would otherwise demand enormous computational effort from conventional digital machines.

Several approaches to Ising machines have been explored over the past decade. In 2016, two landmark demonstrations appeared in Science: a team led by T. Inagaki and colleagues at NTT built a coherent Ising machine using a network of optical parametric oscillators, while Peter McMahon and collaborators at Stanford University demonstrated a similar photonic architecture with improved scaling and solution quality. These photonic systems showed that physical analog hardware could indeed compete with digital algorithms on certain problem instances, sparking a worldwide effort to find faster, cheaper and more compact physical substrates for Ising-style computation.

Magnetic devices entered this race for compelling reasons. A magnetic tunnel junction consists of two ferromagnetic layers separated by a thin insulating barrier, and its resistance depends on the relative orientation of the two magnetizations, parallel or antiparallel. Those two resistance states map naturally onto the two states of an Ising spin, up or down. Furthermore, each magnetic tunnel junction is, in effect, a tiny bar magnet with genuine thermal fluctuations, a property that Kerem Camsari, Rafatul Faria, Brian Sutton and Supriyo Datta exploited in 2017 in Physical Review X to propose stochastic units called p-bits, probabilistic bits that fluctuate between states with tunable bias and can implement powerful sampling-based optimization and inference algorithms when networked together.

The work highlighted in the new perspective, an article by S. Li and colleagues in Nature Electronics, advances this program by using voltage-controlled magnetic anisotropy to switch and modulate the magnetic tunnel junctions in an integrated array. Voltage-controlled magnetic anisotropy, first demonstrated prominently by W.-G. Wang, M. Li, S. Hageman and C. L. Chien in Nature Materials in 2012, allows the magnetic anisotropy of an ultrathin ferromagnetic film, and hence its energy barrier and preferred magnetization direction, to be tuned by applying a voltage across an adjacent gate dielectric. Because this mechanism acts through an electric field rather than a current, it promises dramatically lower energy per operation than current-based switching schemes, addressing one of the central bottlenecks for scaling magnetic logic and memory technologies.

In the architecture described by the perspective, the integrated array of magnetic tunnel junctions serves as a physical realization of Ising spins, while the coupling between spins, the analog of the exchange interactions in the Ising model, encodes the structure of the optimization problem being solved. By driving the array with appropriate voltage control, the system explores the configuration space and relaxes toward low-energy states that correspond to good, and in favorable cases optimal, solutions of the encoded problem. Crucially, the perspective emphasizes that this can be done quickly and with low energy consumption, two figures of merit that determine whether such hardware can move beyond laboratory demonstrations and into practical use for real workloads in logistics, finance, drug discovery and chip design.

The new report builds on a series of recent advances in magnetic Ising and probabilistic computing hardware. In 2023, Y. Shao and colleagues published work in Nanotechnology on magnetic tunnel junction-based approaches to Ising computation, and in 2024, J. Si and collaborators reported in Nature Communications on magnetic tunnel junction arrays for such applications. More recently, in 2026, M. A. Iftakher and colleagues described related stochastic magnetic computing concepts in Nature Communications. Together, these studies trace a rapid trajectory from single-device physics toward integrated, array-scale systems, and the Li and colleagues work reported in Nature Electronics represents an important consolidation of that progress into a functional, integrated platform for model optimization problems.

What makes the magnetic approach particularly attractive is its compatibility with existing semiconductor manufacturing. Magnetic tunnel junctions are already embedded in billions of consumer devices as memory cells, and the materials and process technology for fabricating them at scale is mature. A computing architecture that repurposes these devices as stochastic optimization elements could, in principle, be fabricated alongside conventional CMOS circuitry, opening a path toward hybrid chips in which a conventional processor offloads hard combinatorial kernels to a dense magnetic Ising fabric. The low switching energies enabled by voltage-controlled magnetic anisotropy further strengthen the case, since the energy cost of each spin update is a key determinant of overall system efficiency at scale.

Challenges nonetheless remain before magnetic Ising machines can challenge state-of-the-art algorithms and specialized processors on production-scale problems. The quality of solutions found by physical relaxations depends on the fidelity of the implemented couplings, the stability and controllability of the stochastic dynamics, the number of spins that can be integrated, and the efficiency of reading out and verifying results. Problems of practical interest often involve far more variables than any near-term chip can host, requiring embedding techniques that inflate problem size, and the performance of Ising machines against the best classical solvers continues to be debated. The authors of the perspective, who are affiliated with the George Washington University and the Physical Measurement Laboratory of the National Institute of Standards and Technology, note that demonstrating clear, reproducible advantages on benchmark problems will be essential for the field’s credibility.

Even so, the demonstration that an integrated array of magnetic tunnel junctions can rapidly and efficiently solve Ising-model optimization problems marks a significant milestone at the intersection of magnetism, memory technology and unconventional computing. It suggests that the devices built to remember bits may also be enlisted to search for them, turning the physics of nanoscale magnetism into a computational resource. As the hardware matures and couples more tightly with conventional electronics, magnetic Ising machines could become a practical accelerator for some of the hardest, most economically consequential computational problems that society routinely faces.

Subject of Research: Using integrated arrays of magnetic tunnel junctions with voltage-controlled magnetic anisotropy to accelerate Ising-model-based combinatorial optimization.

Article Title: Magnetic memory accelerates combinatorial optimization

Article References: Zhang, H., Borders, W. A., & Stiles, M. D. (2026). Magnetic memory accelerates combinatorial optimization. Nature Electronics. https://doi.org/10.1038/s41928-026-01713-1

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01713-1

Keywords: magnetic tunnel junctions, Ising machines, combinatorial optimization, voltage-controlled magnetic anisotropy, Nature Electronics, probabilistic computing, spintronics, low-power computing, p-bits, statistical physics, MRAM, unconventional computing