In a breakthrough that brings sixth-generation wireless closer to reality, engineers have shrunk a terahertz-band radio front end onto a single silicon chip, solving a stubborn physics problem with an elegant, mass-producible design. The achievement marks the first time a fully integrated two-dimensional phased array operating above 200 gigahertz—complete with on-chip antennas spaced at half the wavelength—has been realized entirely in standard complementary metal-oxide-semiconductor (CMOS) technology.
Wireless systems crave ever-higher carrier frequencies to unlock wider bandwidths and accelerate data rates. The 300 GHz band, perched at the threshold of the terahertz region, offers abundant spectrum while largely avoiding the molecular absorption peaks that cripple higher frequencies. Yet such high frequencies suffer severe free-space path loss: a signal’s power diminishes dramatically over even modest distances. To compensate, engineers turn to phased arrays—collections of antenna elements that individually steer and shape a radio beam by precisely controlling the phase of each signal. By focusing energy toward the intended receiver, the array recovers the link budget and maintains communication.
Building a phased-array transceiver at 300 GHz, however, pushes every boundary. At these sub-millimeter wavelengths, adjacent antenna elements must sit within roughly half a wavelength of one another to avoid spurious grating lobes that scatter energy in unwanted directions. For a 300 GHz signal, that means roughly 500 micrometers—a space so tight that the antennas, phase shifters, amplifiers, frequency doublers, triplers, and mixers must all coexist on the same die with almost no wasted area. Doing this in a low-power, bidirectional fashion while using the cost-effective 65‑nm CMOS process that drives consumer electronics has long been considered a grand challenge.
Now a team led by Professor Kenichi Okada at the Institute of Science Tokyo has cracked the problem. At the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits in Honolulu, they unveiled a 4×4 bi-directional phased-array transceiver that operates across the 240–270 GHz band. Each of the sixteen elements is a self-contained front end, packing a phase shifter, a frequency doubler, a sub-terahertz injection-locked tripler that generates the carrier directly from a lower-frequency reference, a sub-harmonic mixer, and an on-chip dipole antenna. The team adopted a clever mixer-last architecture in transmit mode and a mixer-first topology in receive mode, minimizing the number of active stages and slashing power consumption.
The array achieves an element pitch of only 0.49 λ in the E-plane and 0.50 λ in the H-plane, perfectly satisfying the half-wavelength criterion. This tight integration suppresses grating lobes and enables coherent beam-steering across a wide angular range. Remarkably, each transceiver element consumes a mere 26 milliwatts and occupies a core area of just 0.30 square millimeters—numbers so low that large-scale arrays become not merely conceivable but commercially viable.
In over-the-air communication experiments, the transmitter sustained a 16‑Gbaud quadrature phase-shift keying (QPSK) link, while the receiver handled a 26‑Gbaud QPSK data stream. Those symbol rates translate to raw data capacities of 32 and 52 gigabits per second per channel, respectively, validating the chip’s ability to send and receive complex modulated waveforms through free space. “This represents the first 300‑GHz-band two‑dimensional bi-directional phased-array transceiver with on-chip half‑wavelength‑spaced antennas implemented as a single all‑CMOS chip,” said Okada. “The low‑power consumption and small chip area per element are particularly important because future terahertz wireless systems will require compact, scalable, and manufacturable front‑end hardware.”
The significance extends well beyond the laboratory. CMOS-compatible terahertz front ends can ride the semiconductor industry’s immense scaling and cost-reduction curves, eventually making 6G base stations and user devices affordable to deploy. Beam-steering arrays like this one can dynamically track mobile users, maintain robust links in indoor and outdoor environments, and support the multi‑gigabit‑per‑second rates that future applications—from holographic telepresence to wireless cognition—will demand.
While the path to commercialization still demands improvements in output power and efficiency, the Tokyo team’s demonstration shows that silicon can indeed tame the terahertz frontier. By placing antennas and bidirectional transceiver circuitry side-by-side on a single chip, they have built a blueprint for the wireless hardware of the 2030s. “The achievement may accelerate research related to 6G wireless systems and beyond,” Okada concluded, “where compact phased arrays, beam steering, and low‑power terahertz circuits will be essential for realizing ultra‑high‑speed wireless links.”
Subject of Research: A 240–270 GHz 4×4 bi-directional phased-array transceiver in 65-nm CMOS for 6G wireless communication.
Article Title: A 240–270 GHz 4×4 Bi-Directional Phased-Array Transceiver with On-Chip Half-Wavelength-Spaced Array and Ultra-Low Power Consumption in 65-nm CMOS
News Publication Date: June 2026 (presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits)
Web References: Not available
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Image Credits: Institute of Science Tokyo
Keywords
6G, terahertz communication, phased-array transceiver, beam steering, CMOS, 300 GHz, on-chip antenna, low power, bi-directional, VLSI, sub-terahertz, half-wavelength spacing, QPSK, injection-locked tripler, Science Tokyo
