Combinatorial optimization is everywhere in modern technology. Designing a chip’s wiring layout, routing vehicles through a delivery network, scheduling flights, and assigning radio frequencies all belong to this family of problems, in which the goal is to find the best configuration from an astronomically large set of possibilities. Many of these tasks are NP-hard, meaning that no known algorithm can solve them efficiently as they grow. Classical computers, built on the von Neumann architecture that separates memory from processing, grind through such problems by evaluating candidate solutions one after another, and the cost quickly becomes prohibitive.

Ising machines take an entirely different approach. They are physical systems engineered to mimic the Ising model, a mathematical framework from statistical physics in which each of many interacting binary variables, called spins, settles into a state that minimizes the total energy of the system. Because any combinatorial optimization problem can be mapped onto such an energy-minimization landscape, a well-engineered Ising machine can let physics do the searching: spins flip stochastically, interact with their neighbors, and collectively relax toward low-energy configurations that correspond to good, and sometimes optimal, solutions. The concept has been realized in quantum annealers, optical platforms built from lasers and fibers, and various electronic chips, each with its own trade-offs between speed, scale, and programmability.

The new machine, which the researchers call VSIM, stands out for the speed at which its spins can change state. At the heart of each spin is a magnetic tunnel junction, the same nanoscale element that stores bits in MRAM. Rather than switching deterministically between two stable states as memory cells do, the device exploits the voltage-controlled magnetic anisotropy effect, in which an applied voltage alters the energy barrier that separates the two magnetic orientations. By tuning the width of a voltage pulse, the team can dial the probability that a single pulse flips the junction anywhere from zero to one hundred percent. That probabilistic switching is exactly what an Ising machine needs, because stochastic spin updates allow the system to escape local energy minima where deterministic algorithms become trapped.

The numbers are striking. Spin updates take between 0.3 and 1 nanosecond, firmly in the sub-nanosecond regime that has eluded most alternative platforms, and each update consumes less than 40 femtojoules per spin. Because the magnetic tunnel junctions are integrated directly with CMOS circuitry, the machine combines the density and manufacturability of standard semiconductor technology with the intrinsic randomness of nanoscale magnetism. The write currents involved are low, another consequence of the voltage-based control mechanism, and the all-to-all connectivity on the chip means any spin can in principle influence any other, which matters greatly for faithfully encoding the interaction structure of real optimization problems.

To demonstrate that the machine is more than a laboratory curiosity, the team mapped two problems drawn directly from electronic design automation, the software domain that underpins the entire semiconductor industry. The first is global routing, the task of deciding how to connect millions of circuit components across a chip’s wiring grid while minimizing wire length and congestion. The second is layer assignment, which determines which of several metal layers each wire segment should occupy. Both are commercially critical steps in chip design, and both were encoded as Ising Hamiltonians and solved on the hardware. In an era when chip design complexity is straining conventional design automation tools, hardware solvers aimed squarely at this workflow have obvious practical appeal.

Benchmarked against standard Max-cut test problems, a canonical yardstick in the Ising machine literature, the chip delivered high-quality solutions at a system-level energy efficiency of 1.92 times ten to the fifth solutions per second per watt. That figure reflects not just the raw speed of the magnetic tunnel junctions but the whole pipeline: an FPGA board configures the couplings, drives the annealing schedule, and reads out the final spin configuration. The researchers also examined how robustly the machine performs in the face of device-to-device variation, an unavoidable reality of nanoscale fabrication, finding that solution quality holds up well provided the single-pulse switching probability stays above roughly sixty percent.

The work lands in a crowded and fast-moving field. Quantum annealers have demonstrated computations on thousands of superconducting qubits, coherent Ising machines built from optical fiber loops have handled 100,000-spin problems, and a parade of CMOS-based annealing chips has appeared at recent circuits conferences. Spintronic approaches, in which the spin itself is the stochastic element, have generally been limited to far smaller arrays. What distinguishes this demonstration is the combination of scale, at 96,000 spins, with sub-nanosecond update speed and full CMOS integration, a trio of attributes that no single previous platform has offered simultaneously.

There remain caveats and open questions. The reported demonstrations, while industrially relevant, are specific problem instances, and scaling the machine to the problem sizes encountered in full-scale chip design will require larger arrays, better coupling precision, and careful management of annealing schedules. The metrics used to compare heterogeneous Ising machines, spanning quantum, optical, and electronic implementations, are themselves still being debated by the community. And like all physics-based solvers, Ising machines provide high-quality solutions rather than guaranteed optima, which may or may not suffice depending on the application.

Even so, the demonstration points toward a future in which the memory devices inside every processor become active computational elements. The voltage-controlled magnetic tunnel junction at the center of this work is already the storage element of a commercial memory technology, which means the path from laboratory demonstration to embedded accelerator runs through established fabrication infrastructure rather than exotic physics. If spintronic Ising machines can keep pace in scale, they could take their place alongside GPUs and dedicated AI accelerators as specialized hardware for the optimization workloads that quietly underpin modern technology. The team has released its source data and code to the community, an invitation for researchers worldwide to stress-test this new class of machine against the hardest problems they can find.

Subject of Research: A CMOS-integrated spintronic Ising machine using magnetoresistive memory for fast, energy-efficient combinatorial optimization

Article Title: An Ising machine for combinatorial optimization based on sub-nanosecond CMOS-integrated magnetoresistive random-access memory

Article References: An Ising machine for combinatorial optimization based on sub-nanosecond CMOS-integrated magnetoresistive random-access memory. (n.d.). https://doi.org/10.1038/s41928-026-01700-6

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01700-6

Keywords: Ising machine, combinatorial optimization, spintronics, MRAM, magnetic tunnel junction, voltage-controlled magnetic anisotropy, Nature Electronics, electronic design automation, global routing, Max-cut, probabilistic computing, CMOS integration

The Ising model, borrowed from statistical physics, describes a collection of spins that can each point up or down, with interactions that either favor alignment or anti-alignment between neighboring spins. Finding the lowest-energy spin configuration of such a system is mathematically equivalent to a broad class of hard combinatorial problems, a correspondence that Andrew Lucas laid out systematically in a widely cited 2014 paper in Frontiers of Physics. Because of this equivalence, researchers have long been interested in building physical systems, so-called Ising machines, whose natural dynamics drive them toward low-energy states, allowing the hardware itself to perform the search that would otherwise demand enormous computational effort from conventional digital machines.

Several approaches to Ising machines have been explored over the past decade. In 2016, two landmark demonstrations appeared in Science: a team led by T. Inagaki and colleagues at NTT built a coherent Ising machine using a network of optical parametric oscillators, while Peter McMahon and collaborators at Stanford University demonstrated a similar photonic architecture with improved scaling and solution quality. These photonic systems showed that physical analog hardware could indeed compete with digital algorithms on certain problem instances, sparking a worldwide effort to find faster, cheaper and more compact physical substrates for Ising-style computation.

Magnetic devices entered this race for compelling reasons. A magnetic tunnel junction consists of two ferromagnetic layers separated by a thin insulating barrier, and its resistance depends on the relative orientation of the two magnetizations, parallel or antiparallel. Those two resistance states map naturally onto the two states of an Ising spin, up or down. Furthermore, each magnetic tunnel junction is, in effect, a tiny bar magnet with genuine thermal fluctuations, a property that Kerem Camsari, Rafatul Faria, Brian Sutton and Supriyo Datta exploited in 2017 in Physical Review X to propose stochastic units called p-bits, probabilistic bits that fluctuate between states with tunable bias and can implement powerful sampling-based optimization and inference algorithms when networked together.

The work highlighted in the new perspective, an article by S. Li and colleagues in Nature Electronics, advances this program by using voltage-controlled magnetic anisotropy to switch and modulate the magnetic tunnel junctions in an integrated array. Voltage-controlled magnetic anisotropy, first demonstrated prominently by W.-G. Wang, M. Li, S. Hageman and C. L. Chien in Nature Materials in 2012, allows the magnetic anisotropy of an ultrathin ferromagnetic film, and hence its energy barrier and preferred magnetization direction, to be tuned by applying a voltage across an adjacent gate dielectric. Because this mechanism acts through an electric field rather than a current, it promises dramatically lower energy per operation than current-based switching schemes, addressing one of the central bottlenecks for scaling magnetic logic and memory technologies.

In the architecture described by the perspective, the integrated array of magnetic tunnel junctions serves as a physical realization of Ising spins, while the coupling between spins, the analog of the exchange interactions in the Ising model, encodes the structure of the optimization problem being solved. By driving the array with appropriate voltage control, the system explores the configuration space and relaxes toward low-energy states that correspond to good, and in favorable cases optimal, solutions of the encoded problem. Crucially, the perspective emphasizes that this can be done quickly and with low energy consumption, two figures of merit that determine whether such hardware can move beyond laboratory demonstrations and into practical use for real workloads in logistics, finance, drug discovery and chip design.

The new report builds on a series of recent advances in magnetic Ising and probabilistic computing hardware. In 2023, Y. Shao and colleagues published work in Nanotechnology on magnetic tunnel junction-based approaches to Ising computation, and in 2024, J. Si and collaborators reported in Nature Communications on magnetic tunnel junction arrays for such applications. More recently, in 2026, M. A. Iftakher and colleagues described related stochastic magnetic computing concepts in Nature Communications. Together, these studies trace a rapid trajectory from single-device physics toward integrated, array-scale systems, and the Li and colleagues work reported in Nature Electronics represents an important consolidation of that progress into a functional, integrated platform for model optimization problems.

What makes the magnetic approach particularly attractive is its compatibility with existing semiconductor manufacturing. Magnetic tunnel junctions are already embedded in billions of consumer devices as memory cells, and the materials and process technology for fabricating them at scale is mature. A computing architecture that repurposes these devices as stochastic optimization elements could, in principle, be fabricated alongside conventional CMOS circuitry, opening a path toward hybrid chips in which a conventional processor offloads hard combinatorial kernels to a dense magnetic Ising fabric. The low switching energies enabled by voltage-controlled magnetic anisotropy further strengthen the case, since the energy cost of each spin update is a key determinant of overall system efficiency at scale.

Challenges nonetheless remain before magnetic Ising machines can challenge state-of-the-art algorithms and specialized processors on production-scale problems. The quality of solutions found by physical relaxations depends on the fidelity of the implemented couplings, the stability and controllability of the stochastic dynamics, the number of spins that can be integrated, and the efficiency of reading out and verifying results. Problems of practical interest often involve far more variables than any near-term chip can host, requiring embedding techniques that inflate problem size, and the performance of Ising machines against the best classical solvers continues to be debated. The authors of the perspective, who are affiliated with the George Washington University and the Physical Measurement Laboratory of the National Institute of Standards and Technology, note that demonstrating clear, reproducible advantages on benchmark problems will be essential for the field’s credibility.

Even so, the demonstration that an integrated array of magnetic tunnel junctions can rapidly and efficiently solve Ising-model optimization problems marks a significant milestone at the intersection of magnetism, memory technology and unconventional computing. It suggests that the devices built to remember bits may also be enlisted to search for them, turning the physics of nanoscale magnetism into a computational resource. As the hardware matures and couples more tightly with conventional electronics, magnetic Ising machines could become a practical accelerator for some of the hardest, most economically consequential computational problems that society routinely faces.

Subject of Research: Using integrated arrays of magnetic tunnel junctions with voltage-controlled magnetic anisotropy to accelerate Ising-model-based combinatorial optimization.

Article Title: Magnetic memory accelerates combinatorial optimization

Article References: Zhang, H., Borders, W. A., & Stiles, M. D. (2026). Magnetic memory accelerates combinatorial optimization. Nature Electronics. https://doi.org/10.1038/s41928-026-01713-1

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01713-1

Keywords: magnetic tunnel junctions, Ising machines, combinatorial optimization, voltage-controlled magnetic anisotropy, Nature Electronics, probabilistic computing, spintronics, low-power computing, p-bits, statistical physics, MRAM, unconventional computing