The review, authored by Nada Salem, Ahmed Shaker, Mahmoud Ossaimee, Ahmed Saeed, Mohamed Abouelatta, and El-Sayed M. El-Rabaie, takes an unusually integrated approach. Rather than treating device physics, manufacturing, and circuit applications as separate silos, the authors connect the atomic structure of carbon nanotubes directly to transistor behavior and ultimately to commercial viability. This matters because the performance of a CNTFET is not determined by the nanotube alone; contact resistance, tube alignment, density control, metallic-tube removal, and compatibility with existing CMOS manufacturing all shape whether carbon can genuinely replace silicon in a factory setting.

At the heart of the technology lies a deceptively simple material trick. A carbon nanotube is a sheet of graphene rolled into a cylinder roughly one nanometer in diameter, and the precise way it is rolled, defined by its chirality indices (n, m), determines whether it behaves as a metal or a semiconductor. Tubes in which the difference between the two indices is divisible by three are nominally metallic, while the rest are semiconducting. For semiconducting single-walled tubes, the bandgap scales approximately inversely with diameter, following the relation Eg of about 0.84 divided by the diameter in nanometers. That simple formula gives device engineers a powerful tuning knob: choosing the tube diameter effectively sets the threshold voltage, the leakage current, and the ON-state current of the resulting transistor.

The physics inside these devices is equally striking. Because carriers are confined to a one-dimensional channel, transport can approach the ballistic limit, where electrons traverse the channel without scattering. Clean carbon nanotube channels have demonstrated carrier mobilities of roughly 1,000 to 10,000 square centimeters per volt-second, an order of magnitude or more above scaled silicon, with characteristic carrier velocities of 2 to 5 times ten to the seventh centimeters per second against a theoretical Fermi velocity ceiling near 8 times ten to the seventh. Subthreshold swings can approach 60 to 80 millivolts per decade, and ON/OFF current ratios spanning 10^5 to 10^8 have been reported depending on diameter, contacts, and dielectric engineering. These numbers explain why researchers have chased carbon nanotubes since the first CNTFET was demonstrated in 1998.

Architecture has evolved considerably since those early proof-of-concept devices. Back-gated transistors, in which the silicon substrate itself acts as the gate, were simple to build but suffered from contact resistances of a megohm or more and weak electrostatic control. Top-gated designs introduced thin dielectrics deposited by atomic layer deposition, tightening gate coupling and enabling individual devices to be isolated on a single wafer. Wrap-around or gate-all-around structures, demonstrated in 2008, surround the nanotube entirely, suppressing leakage and short-channel effects most effectively. Suspended devices, in which the tube hangs free over a trench, minimize substrate scattering and reveal the intrinsic transport properties of the material, though mechanical instability and limited dielectric options keep them largely a laboratory tool.

Modeling this zoo of devices has produced a rich theoretical landscape. Ballistic models, built on the Landauer formalism, estimate the performance ceiling of ideal short-channel devices. Quasi-ballistic and non-ballistic models add phonon scattering through virtual-source and Landauer-Büttiker approaches, capturing the roughly 30 percent current reduction that dissipative transport imposes in realistic channels. Tunneling-based compact models account for band-to-band tunneling that dominates in small-bandgap tubes under bias, while full non-equilibrium Green’s function formulations solve quantum transport self-consistently with electrostatics, linking device behavior directly to the chiral index of the tube. For circuit designers, SPICE-compatible compact models such as the Stanford virtual-source CNFET model bridge the gap, embedding quantum capacitance, contact resistance, and ambipolar conduction into tools that can evaluate logic, memory, and radio-frequency circuits.

Fabrication remains the decisive battleground. Modern processes grow horizontally aligned nanotube arrays on quartz by chemical vapor deposition at densities near three tubes per micrometer, transfer them to oxidized silicon wafers, selectively remove metallic tubes, and deposit high-k gate stacks of titanium dioxide with titanium-platinum electrodes. The resulting devices show improved ON/OFF ratios and reduced device-to-device variability, and the low processing temperatures make the route compatible with CMOS thermal budgets. On a very different frontier, aerosol jet printing has been used to fabricate working CNTFETs on flexible Kapton substrates using silver ink electrodes and cross-linked polymer dielectrics, opening a path toward wearable and bendable electronics that rigid silicon cannot serve.

The application portfolio is expanding fast. CNTFET biosensors have detected the H1N1 virus, DNA modifications, prostate-specific antigen at concentrations from 5 to 5000 picograms per milliliter, and SARS-CoV-2 spike protein epitopes within minutes, exploiting the nanometer-scale match between tube and biomolecule. In memory research, devices using hafnium oxide gates have achieved write and erase operations with 100-nanosecond pulses, roughly 10,000 times faster than earlier carbon nanotube memory, with retention exceeding four hours and endurance past 18,000 cycles. Digital demonstrations include 1-kilobit six-transistor SRAM arrays built with carbon nanotube CMOS, ternary logic gates that combine CNTFETs with resistive memory, and approximate multipliers for energy-efficient image processing. Wafer-scale synaptic transistors exploit the sensitivity of nanotubes to charged defects, positioning carbon at the heart of neuromorphic computing architectures that dissolve the boundary between logic and memory.

Even with this momentum, the review is candid about the barriers. Chirality-controlled synthesis of high-purity semiconducting tubes at wafer scale remains unsolved, and even small diameter variations shift bandgaps enough to scatter threshold voltages across a chip. Residual metallic tubes create leakage paths, contact engineering at the metal-carbon interface still introduces Schottky barriers and variability, and self-heating in real devices, where nanotube-to-substrate thermal boundary resistance limits heat dissipation, threatens reliability despite the exceptional intrinsic thermal conductivity of individual tubes. Uniform high-k dielectric deposition on chemically inert nanotube surfaces, variation-aware compact modeling, and back-end-of-line integration with existing CMOS flows round out the challenge list.

What emerges from the full picture is a technology standing at a genuine inflection point. The intrinsic material advantages of carbon nanotubes, from near-ballistic transport and diameter-tunable bandgaps to mechanical flexibility and bioscale sensitivity, are no longer in dispute. The remaining work is industrial: scalable purification, wafer-level alignment, stable low-resistance contacts, and standardized benchmarking against silicon and emerging two-dimensional materials. If those pieces fall into place, the authors conclude, CNTFETs are strong contenders to deliver the high-performance, energy-efficient, and miniaturized electronics that the next generation of computing, sensing, and communication systems will demand.

Subject of Research: Carbon nanotube field-effect transistors as post-silicon electronic devices

Article Title: Structure, modeling, fabrication, and applications of carbon nanotube field-effect transistors: a comprehensive review

Article References: Salem, N., Shaker, A., Ossaimee, M., Saeed, A., Abouelatta, M., & El-Rabaie, E.-S. M. (2026). Structure, modeling, fabrication, and applications of carbon nanotube field-effect transistors: a comprehensive review. Results in Physics, 89, Article 108749. https://doi.org/10.1016/j.rinp.2026.108749

Image Credits: AI Generated

DOI: 10.1016/j.rinp.2026.108749

Keywords: carbon nanotubes, CNTFET, field-effect transistors, post-silicon electronics, Moore's law, bandgap engineering, neuromorphic computing, biosensors, SRAM, CMOS compatibility, quantum transport, flexible electronics

The crux of the thermal management issue lies in the low thermal conductivity of interlayer dielectrics and the intricate interfaces formed during the 3D integration process. As heat builds up in densely packed components, efficient heat dissipation becomes essential to prevent overheating, which can compromise performance and reduce the lifespan of integrated circuits. Therefore, addressing these thermal challenges is vital for the continued advancement and reliability of 3D-stacked integrated circuits. As researchers delve deeper into this subject, state-of-the-art thermal management materials emerge as a beacon of hope—a pathway to not only mitigate heat buildup but also optimize the performance of these next-generation technologies.

In recent years, researchers have been working diligently to develop novel thermal management materials that address the unique challenges posed by 3D stacking. These materials must exhibit high thermal conductivity and robust performance characteristics while maintaining process compatibility with existing fabrication technologies. The integration of such materials into manufacturing pipelines is of utmost importance. As the semiconductor landscape continually evolves, materials must not only meet stringent performance requirements but also seamlessly assimilate into established processes to ensure scalability and economic feasibility.

Complex interfaces can often hinder effective heat transfer, making it imperative to explore methods to improve heat transport across these junctions. The effectiveness of thermal management materials is contingent not just on their inherent properties but also on their interaction with adjacent materials and layers. Innovative approaches that enhance the thermal interaction at interfaces could lead to significant advancements in thermal performance, perhaps presenting a solution to the ongoing challenges faced in 3D integrated circuit design.

Advanced thermal characterization techniques have emerged as indispensable tools for evaluating the efficacy of thermal management strategies. These methodologies enable the assessment of thermal conductivity, interface quality, and overall system performance in real-time. However, the demand for non-destructive in-line metrology has never been more urgent. As the industry strives for greater efficiency and reliability, it becomes paramount to introduce techniques that allow for continuous monitoring and assessment of thermal properties during the manufacturing process, thus facilitating timely intervention when performance issues arise.

As we push toward a future where 3D integration becomes the standard, a cohesive roadmap for research and development is essential. This roadmap should incorporate innovative material growth strategies, novel integration techniques, and sophisticated characterization methods to create a holistic understanding of thermal dynamics in stacked architectures. Establishing clear directions for future research can expedite progress in developing practical thermal solutions that comply with the rigors of next-generation semiconductor applications.

Collaboration between academia, industry, and research institutions is crucial in this endeavor. By pooling expertise and resources, stakeholders can address the multifaceted challenges of thermal management collectively. This collaboration can lead to breakthroughs in not only material science but also in the design of systems that optimize thermal performance, ensuring the longevity and efficiency of advanced 3D integrated circuits.

Moreover, as the exploration of thermal management materials progresses, lessons learned from earlier generations of semiconductor technologies provide invaluable insights. Historical perspectives on thermal management issues reveal patterns that can help shape current research efforts. By understanding previous challenges and solutions, researchers can avoid repeating past mistakes and instead innovate more effectively.

The role of nanotechnology cannot be understated in this conversation about thermal management. Nanoscale materials and structures offer unique physical properties that can dramatically enhance thermal conductivity and efficiency. As researchers develop new nanomaterials optimized for thermal transport, the potential to revolutionize heat management in 3D-stacked circuits becomes palpable.

In summary, the challenges posed by 3D integration in semiconductor technology are significant but not insurmountable. The journey toward achieving optimal thermal management involves not only the identification and development of superior materials but also the formulation of effective strategies for their integration and characterization. By focusing on the intricate relationship between materials, interfaces, and emerging technologies, the semiconductor industry can cultivate the necessary innovations required for a new era of high-performance computing and artificial intelligence.

As we move forward, the need for continuous evaluation and adaptation of thermal solutions in 3D integration will only grow. The exploration of advanced materials, in conjunction with innovative manufacturing processes and characterization techniques, promises a robust framework for enhancing thermal management efficiency. Stakeholders across various sectors will need to keep a close watch on emerging trends and research findings that could redefine the landscape of 3D-integrated circuit technology for years to come.

Recent developments suggest that the pursuit of groundbreaking thermal materials will be a linchpin in the evolution of semiconductor technology. With the right combination of research, collaboration, and innovation, we stand on the cusp of unlocking unprecedented capabilities in processing power, efficiency, and overall performance. This collective commitment to advancing thermal management solutions represents a pivotal moment for the semiconductor industry as it adeptly adapts to the increasing demands of modern high-performance applications.

Through a unified effort, the transformation of thermal management in 3D-stacked integrated circuits will pave the way for novel applications in artificial intelligence and beyond. The future of semiconductor technology hinges on merging science, engineering, and vision, ensuring that the iconic 3D architectures become the foundational bedrock for the next generation of intelligent systems.

Subject of Research: Thermal management materials for 3D-stacked integrated circuits.

Article Title: Thermal management materials for 3D-stacked integrated circuits.

Article References:

Woon, WY., Kasperovich, A., Wen, JR. et al. Thermal management materials for 3D-stacked integrated circuits.
Nat Rev Electr Eng 2, 598–613 (2025). https://doi.org/10.1038/s44287-025-00196-0

Image Credits: AI Generated

DOI: https://doi.org/10.1038/s44287-025-00196-0

Keywords: thermal management, 3D integration, semiconductor technology, heat dissipation, advanced materials, high-performance computing, artificial intelligence, thermal conductivity, interface engineering, nanotechnology, thermal characterization.