The core of the innovation lies in a class of devices known as ion-gated transistors. In these devices, a thin film of carbon nanotubes forms the conducting channel, and gating is achieved not through a conventional insulating dielectric but through an ionogel, a material in which mobile ions are embedded within a polymer matrix to form a solid. When a voltage is applied to the gate, ions migrate within the ionogel and modulate the flow of current through the carbon nanotube channel. The crucial and, until now, largely unwanted property of these materials is that the ions do not return instantaneously to their original positions when the voltage is removed. Their slow relaxation means that the electrical effect of a previous input lingers in the device for a measurable period, effectively giving the hardware a form of short-term memory.

Conventional semiconductor engineering has long treated this sluggish ionic behavior as a defect to be minimized, since it limits the speed at which a transistor can switch. The KAIST-led team inverted that assumption. Rather than fighting the slow dynamics, they exploited them, designing devices in which the duration of the lingering response could be tuned with precision. By adjusting the ionic content of the ionogel and controlling the thickness of the solid thin film, the researchers could dictate how quickly or slowly the ions within each device relaxed back to their resting state. Fast-relaxing devices responded sharply to the most recent input, while slow-relaxing devices integrated signals that had accumulated over a longer window of time.

The decisive engineering challenge was material form. Ion-gated devices have historically relied on liquid electrolytes or soft gels, which are difficult to pattern with the precision required for microfabrication and nearly impossible to stack into multiple functional layers. The team’s solution was to render the ionogel fully solid, creating a thin film that could be processed using existing thin-film semiconductor techniques. This solid-state approach allowed the researchers to fabricate devices reproducibly on 4-inch wafers and even on flexible substrates, and then to stack devices with different temporal characteristics vertically, producing a monolithic three-dimensional reservoir architecture in which multiple timescales of information processing coexist within a single hardware platform.

The resulting architecture belongs to a computational paradigm known as reservoir computing. In a reservoir system, input signals are fed into a network of dynamical elements whose internal states evolve according to their own physical properties, and only a simple output layer is trained to interpret those states. Because the reservoir itself performs the temporal transformation of the input, the approach is naturally suited to signals that unfold over time, such as motion, speech, or physiological waveforms. Implementing the reservoir directly in physical hardware, as the Korean team has done, means the temporal integration happens in the material itself rather than in software, which is precisely the property that makes the technology attractive for low-power edge devices.

To verify that the stacked devices genuinely encoded temporal information, the researchers subjected them to a demanding test: sequences of four consecutive input signals, each either on or off, generating sixteen distinct patterns. The devices successfully distinguished all sixteen, demonstrating that the combination of a fast layer responding to the latest signal and a slow layer carrying the accumulated history could uniquely fingerprint each temporal sequence. This capability, sometimes described as recognizing both the change that has just occurred and the changes that came before it, is exactly what a wearable sensor needs when interpreting a gesture or a heartbeat, where the meaning of any single reading depends on what preceded it.

The team then translated the measured device responses into a simulation model of a complete classification system, testing it on videos of moving handwritten digits. The model achieved validation accuracies above 90 percent for sequences of moving images played at different speeds, a result that speaks to the robustness of the multi-timescale representation. Because the digits were in motion, the classifier had to extract meaning from a stream of frames rather than from a static image, and the fact that performance held across different playback speeds suggests that the layered fast and slow responses captured the essential temporal structure of the input rather than artifacts of any particular timing.

Practical durability is often the weak point of novel device concepts, but the researchers report encouraging stability. The devices were fabricated on both rigid 4-inch wafers and flexible substrates, and their electrical characteristics remained stable for 55 months after fabrication, an unusually long verification window that lends weight to claims of manufacturability. The ability to build the devices with existing thin-film semiconductor processes on large-area substrates, and to stack them in multiple layers, positions the technology closer to industrial reality than approaches that depend on exotic materials or single-laboratory fabrication tricks. Professor Kwon emphasized this point, noting that the devices can be fabricated on large-area substrates using established processes and stacked in multiple layers.

The anticipated applications center on small devices worn on or attached to the body. A smartwatch or a skin-conformable patch must continuously analyze movement and physiological signals while operating within a strict power budget, and offloading temporal processing to a cloud server is neither always feasible nor privacy-preserving. A chip whose physical layers natively separate recent from accumulated signal history could, in principle, perform this analysis locally with far less computation and therefore far less energy than a conventional digital processor running the same task. The researchers suggest the technology could mature into AI chips that analyze movement and physiological signals for devices that must operate with low power consumption, such as smartwatches, though they are careful to note that further validation is needed to determine how the technology performs, and how much power it actually saves, in real products.

The study, whose first author is Research Professor Haksoon Jung of KAIST and whose co-corresponding authors are Professor Yong-Young Noh of POSTECH and Professor Jimin Kwon of KAIST, was supported by the National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT, and by the Korea Planning and Evaluation Institute of Industrial Technology funded by the Ministry of Trade, Industry and Energy. Beyond its immediate wearable ambitions, the work contributes a broader design principle for future neuromorphic hardware: that the intrinsic timescales of a material’s physics, here the relaxation dynamics of ions in a solid gel, can be treated as tunable computational resources rather than imperfections. If that principle generalizes, the slow and seemingly inconvenient physics of soft materials may become a foundation for machines that, like nervous systems, remember the recent past while responding to the present.

Subject of Research: A monolithic 3D-integrated multi-timescale reservoir computing chip based on solid ion-gated carbon nanotube transistors for temporal signal processing.

Article Title: KAIST develops AI chip that recognizes changes in motion over time

Article References: KAIST develops AI chip that recognizes changes in motion over time. (n.d.). Original publication

Image Credits: AI Generated

DOI: Not provided

Keywords: KAIST, reservoir computing, ion-gated transistors, carbon nanotubes, ionogel, 3D integration, neuromorphic hardware, edge AI, wearable devices, temporal signal processing, Advanced Materials, multi-timescale

The foundation of this innovation lies in the sophisticated fabrication of RNPUs using lightly doped silicon wafers treated through a meticulous series of oxidation, ion implantation, and annealing steps. By carefully controlling boron and arsenic dopant concentrations, the team engineered silicon-based devices characterized by unique ambipolar electronic activity and intrinsic nonlinearities. These properties arise partly due to Pb centers within the silicon matrix, contributing to trap-assisted charge transport mechanisms that underlie the device’s nonlinear current-voltage response.

Unlike previous iterations, this fabrication process deliberately omits hydrofluoric acid etching after reactive-ion etching. This subtle modification enhances the influence of the Pb centers at the active interface, fortifying the RNPU’s characteristic energy landscape and thereby strengthening short-term memory effects crucial for temporal signal processing. Consequently, these units function as stateful systems with fading memory spanning tens of milliseconds—a temporal scale optimal for parsing speech signals.

In typical circuitry configurations, the RNPU’s output voltage is measured directly across an external capacitance without extrinsic amplification or virtual grounding. This measurement approach preserves the dynamic charge-storage effects and time-dependent voltage evolution within the device, allowing the RNPU to exhibit recurrent fading memory behavior. The output at any instant is not just a reflection of the immediate input but is intricately conditioned by the sequence of preceding stimuli, a hallmark property for modeling temporal patterns inherent in speech.

Experimental characterization reveals a highly nonlinear response with input-dependent time constants governing the charging and discharging rates of the external capacitance. Sequential voltage steps of increasing magnitude elicit progressively varied temporal responses, confirming the RNPU’s analog processing capabilities extend far beyond that of conventional linear filters. This nonlinear temporal filtering emulates aspects of biological auditory processing, offering a physically grounded platform for real-time acoustic feature extraction.

Harnessing these unique attributes, the team applied RNPU preprocessing to benchmark speech datasets such as the TI-46-Word and the Google Speech Commands (GSC) datasets. Notably, the RNPU’s analog transformation of raw audio waveforms significantly reduces the complexity required in subsequent software-based classification stages. Shallow artificial neural networks (ANNs), including linear layers and shallow convolutional models, trained on RNPU-processed data achieve impressive classification accuracies exceeding 90%, rivaling or surpassing more computationally expensive digital preprocessing frameworks.

Crucially, the RNPU excels not only in feature extraction but also in computational efficiency. Its nonlinear filterbank-like functionality outperforms simulations of linear band-pass and low-pass filters with cutoff frequencies mimicking RNPU device time constants. Incorporation of nonlinear distortion products and delayed signal interactions further bridge the gap toward biological cochlear models, highlighting the RNPU’s neuromorphic nature. In contrast, reservoir computing approaches such as echo state networks, while offering recurrent dynamics, lack the bio-inspired frequency selectivity and compressive nonlinearities that the RNPU intrinsically provides, resulting in lower speech recognition performance.

To translate these advances into hardware implementations, the researchers integrated RNPU preprocessing with analog in-memory computing (AIMC) architectures based on phase-change memory (PCM) devices. Advanced convolutional neural networks were implemented on the IBM HERMES chip, leveraging the RNPU-generated features as inputs. These AIMC systems exhibit orders-of-magnitude improvements in energy efficiency and latency compared to conventional digital processors, while maintaining competitive classification accuracy. The synergy between RNPU preprocessing and AIMC inference establishes a new paradigm for ultra-low-power, real-time speech recognition systems.

Comprehensive system-level analyses highlight the RNPU’s static power consumption at approximately 1.9 nanowatts per device, scaling favorably in parallel configurations. When combined with AIMC classification stages, total energy consumption per inference is projected to approach the microjoule regime, positioning this hybrid analog-digital architecture at the forefront of energy-efficient artificial intelligence hardware. Furthermore, anticipated improvements in PCM device conductance scaling and analog-to-digital converter design promise further reductions in power and latency.

This research also revisits the fundamental principles of auditory processing in mammals by physically emulating nonlinear cochlear filtering through semiconductor device physics. By capturing temporal dependencies and nonlinear frequency selectivity “in the hardware,” the RNPU circumvents the need for computationally intensive preprocessing steps such as mel-frequency cepstral coefficient extraction. This shift towards physical computing opens avenues for deploying always-on, battery-powered speech interfaces in edge devices ranging from smartphones to hearing aids and IoT sensor nodes.

The practical implications extend beyond speech recognition. The RNPU’s fading memory and nonlinear dynamics are naturally suited for processing other temporally complex signals, including biosignals, environmental data, and time-series forecasting. Its room-temperature operation and silicon-based fabrication compatibility enable straightforward integration into existing semiconductor manufacturing workflows, facilitating scalability and commercialization.

Looking ahead, the researchers envisage co-design strategies that tightly couple RNPU analog preprocessing with AIMC inference layers, optimized through end-to-end training pipelines that incorporate device non-idealities and noise characteristics. Such holistic approaches promise to close the accuracy gap with digital systems while maintaining the substantial energy and speed benefits inherent in analog physical computing.

This study redefines the boundary between physics and computation by harnessing intrinsic material properties and nonlinear device phenomena to perform cognitive tasks traditionally reserved for digital processors. The confluence of materials engineering, neuromorphic principles, and deep learning heralds a future where intelligent systems operate with greater efficiency, responsiveness, and biological fidelity.

As the demands for low-latency, energy-conscious, and context-aware speech interfaces escalate, RNPU-based analog computing technologies stand poised to spearhead a new era of hardware-accelerated artificial intelligence. This innovation underscores the transformative potential of physical computing—a paradigm that leverages the natural dynamics of matter itself to perform complex information processing.

Subject of Research:
Analog speech recognition and neuromorphic computing based on Resistive Neural Processing Units (RNPUs) and physical computing.

Article Title:
Analogue speech recognition based on physical computing.

Article References:
Zolfagharinejad, M., Büchel, J., Cassola, L. et al. Analogue speech recognition based on physical computing. Nature (2025). https://doi.org/10.1038/s41586-025-09501-1

Image Credits:
AI Generated