The device architecture at the heart of this investigation is designed to maximize tunneling efficiency while suppressing leakage. It features a Germanium source, whose relatively low bandgap of 0.66 electron-volts enables high levels of carrier injection, paired with a Silicon drain and channel regions whose wider bandgap of 1.12 electron-volts reduces off-state leakage. A heavily doped p+ pocket layer, just 10 nanometers thick, sits at the source-channel junction to create steeper band bending and narrow the tunneling barrier width. The silicon body is vertically segmented into this p+ pocket and an n+ channel layer, each 10 nanometers thick, separated by a silicon dioxide layer. The total gate length is 70 nanometers, including a 30-nanometer lightly doped channel region that suppresses ambipolar conduction by physically distancing the drain junction from the tunneling hotspot. A hetero-dielectric gate stack comprising 2 nanometers of SiO2 and 7 nanometers of high-κ HfO2 reduces the equivalent oxide thickness without increasing physical gate leakage, while the gate metal work function is set to 4.25 electron-volts for optimal threshold characteristics.

What makes this study particularly timely is the growing recognition that interface traps—loose bonds or structural mismatches at the oxide-semiconductor interface—can randomly capture or emit carriers, leading to fluctuations in threshold voltage, on-current, and subthreshold swing. While the impact of random dopant fluctuation and line edge roughness has been extensively studied, the statistical variability arising from spatially localized interface traps in heterojunction devices remained a unique area of investigation. Previous variability studies had largely assumed uniform trap distributions across the entire interface, obscuring the physical reasons for heterostructure TFET degradation. The researchers addressed this critical gap by employing an interface segmentation-based statistical framework to explicitly compare the impact of trap localization within the pocket and channel regions.

Using Synopsys Sentaurus TCAD, the team modeled the device physics with an extended set of physical models. The dynamic non-local band-to-band tunneling model based on Kane’s formulation calculated the tunneling generation rate, evaluating tunneling probability across the complete spatial energy barrier rather than at a single point. This non-local formulation is particularly important for the abrupt Ge-source/Si-pocket heterojunction, where strong spatial band variation and non-uniform electric fields exist near the tunneling junction. The Shockley-Read-Hall recombination model simulated the impact of interface traps, with trap occupancy depending dynamically on local carrier concentrations and the trap energy level. Fermi-Dirac statistics accounted for the degenerate carrier concentrations in the highly doped source and pocket regions, while Old Slotboom bandgap narrowing models accurately represented the reduction in effective bandgap caused by high doping concentrations.

To investigate the impact of spatially localized traps, the researchers adopted the Interface Segmentation Approach, dividing the oxide-semiconductor interface along the 70-nanometer gate length into uniform 5-nanometer segments. Each segment’s interface trap density was treated as a random variable with a Gaussian distribution, centered at the mid-bandgap with an energy standard deviation of 0.1 electron-volts. The mean trap density was 4.96 × 10¹² cm⁻²eV⁻¹ with a spatial standard deviation of 2.88 × 10¹² cm⁻²eV⁻¹. A total of 100 randomized device instances were simulated for each study case to generate statistically significant distributions of the electrical parameters. Four distinct scenarios were considered: a baseline ideal device with no interface traps, traps randomized exclusively in the segments overlapping the n+ channel region, traps randomized exclusively in the segments overlapping the p+ pocket region, and traps randomized across the entire interface to mimic a realistic process scenario.

The baseline simulation established a stable on-current of 1.208 × 10⁻¹⁰ A/µm and an extremely low off-current of 1.71 × 10⁻¹³ A/µm, with a threshold voltage of 0.3137 volts. The mean electron velocity in the channel was recorded at 1.37 × 10⁸ cm/s, providing a reference for transport efficiency. The minimum subthreshold swing for the baseline device was found to be 38.4 mV/dec. Contour plots confirmed that the tunneling generation was strictly confined to the heterojunction interface between the Ge source and the Si pocket, validating the point-tunneling mechanism operated by the electric field peak. No significant Shockley-Read-Hall activity in the active region indicated that leakage mechanisms were effectively suppressed in the ideal device.

When interface traps were infused in the oxide region overlapping the n+ channel, the statistical analysis revealed a clear degradation in transport. The mean on-current dropped to 1.192 × 10⁻¹⁰ A/µm, a reduction of approximately 1.3 percent. Most critically, the electron velocity showed a significant drop from the baseline 1.37 × 10⁸ cm/s to 7.85 × 10⁷ cm/s—a reduction of approximately 42 percent. This confirms that channel traps strongly perturb carrier transport, reducing drift velocity drastically even though the tunneling injection remains stable. The spatial separation between the tunneling junction and the channel trap region ensures that the electrostatics at the Ge-source/p+-pocket interface remain largely unperturbed, preserving the peak electric field and tunneling width governing band-to-band tunneling. Meanwhile, the minimum subthreshold swing increased to a mean value of 148.12 mV/dec with a standard deviation of 4.12 mV/dec, indicating trap-induced broadening of the subthreshold transition through trap-assisted tunneling leakage and potential fluctuations.

In stark contrast, when traps were introduced in the heavily doped p+ pocket region—the zone typically regarded as the most sensitive in TFETs because of its proximity to the tunneling junction—the device demonstrated remarkable robustness. The band-to-band tunneling and Shockley-Read-Hall profiles were almost identical to the trap-free case, confirming a powerful screening effect. The primary transport parameters showed near-zero statistical variability, with the mean on-current and threshold voltage remaining identical to the baseline values. The minimum subthreshold swing showed a mean value of 142.94 mV/dec with a small standard deviation of 2.41 mV/dec. This immunity arises from the strong electrostatic screening in the heavily doped pocket, where the carrier concentration of 5 × 10¹⁹ cm⁻³ makes the Debye screening length sufficiently short, enabling mobile carriers to effectively screen localized interface-trap charges. Consequently, trap-induced potential perturbations decay rapidly, preventing significant alteration of the tunneling barrier and local electric field. The peak electric field of 1.067 × 10⁵ V/cm at the Ge-source/p+-pocket interface remained unchanged, preserving the tunneling probability.

When traps were distributed across both the pocket and channel regions, mimicking the natural by-products of gate stack fabrication and interface process steps, the statistical parameters were almost identical to the channel-only case. The on-current remained at 1.192 × 10⁻¹⁰ A/µm, and the minimum subthreshold swing gave a mean of 148.35 mV/dec with a standard deviation of 3.69 mV/dec—values very close to the channel-only case of 148.12 ± 4.12 mV/dec. This confirms that the reliability of the HDDG TFET is limited solely by the channel interface, as the source-pocket junction is guarded by the screening mechanism. The pocket region remains electrically isolated from trap-induced disturbances even under mixed-trap scenarios, highlighting the strength of the source-pocket junction design.

The comparative analysis against recently reported TFET structures, using their respective worst-case post-trap-analysis values, further validates the proposed architecture. While absolute values vary considerably across different device architectures, material systems, geometries, and bias conditions, the HDDG TFET demonstrates localized trap immunity within the heavily doped pocket region while the degradation caused by channel-localized traps remains spatially distinguishable. Despite the reduction in on-current under the worst-case trap condition, the device maintains low leakage and a post-trap subthreshold swing that remains comparable to, and in some cases better than, previously reported degraded TFET characteristics. The transfer characteristics obtained under trap-free, Gaussian, and uniform trap distributions exhibited only moderate variations, confirming the effectiveness of the heavily doped p+ pocket in suppressing trap-induced electrostatic perturbations.

These findings carry significant implications for reliability-aware low-power device design. For the HDDG architecture, process optimization should focus on improving the quality of the channel interface rather than the heterojunction boundary, maximizing reliable performance. The study reveals that device sensitivity is predominantly transport-limited: traps localized at the oxide-n+ channel interface act as scattering centers that reduce the mean electron velocity by 42 percent and degrade on-current by 1.3 percent, while the critical source-pocket tunneling junction demonstrates statistical immunity to interface traps. These insights are expected to guide future TFET process improvement strategies, particularly for interface engineering and high-κ dielectric integration in ultra-low power and variability-aware device design. As the semiconductor industry continues to push toward aggressively scaled tunneling devices for energy-constrained applications, understanding precisely where interface traps strike hardest—and where heavy doping can provide electrostatic armor—will be essential for translating the promise of sub-60 mV/decade switching into commercial reality.

Subject of Research: Nanoelectronics

Article Title: Role of trap position variation on electrical parameters in hetero-dielectric double gate TFET

Article References: Dutta, R., Bose, A., Hoque, S., & Saha, R. (2026). Role of trap position variation on electrical parameters in hetero-dielectric double gate TFET. Frontiers in Nanotechnology, 8, Article 1961029. https://doi.org/10.3389/fnano.2026.1961029

Image Credits: AI Generated

DOI: 10.3389/fnano.2026.1961029

Keywords: tunnel field-effect transistor, TFET, interface traps, Germanium source, hetero-dielectric double gate, band-to-band tunneling, subthreshold swing, reliability, variability analysis, Debye screening, trap-assisted tunneling, low-power electronics

The breakthrough, published in the prestigious international journal Science, was led by Prof. Jianhua Hao, Head of the Department of Physics and Materials, Chair Professor of Materials Physics and Devices and Associate Director of the PolyU-Wuhan Technology and Innovation Research Institute at PolyU. The collaboration included researchers from the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. Dr. Zehan Wu, Research Assistant Professor in the same department, is the first author of the research article. Their work addresses what the International Roadmap for Devices and Systems (IRDS) has identified as one of the most pressing bottlenecks in modern microelectronics, and it does so using a device architecture that the roadmap itself has flagged as the most promising successor to today’s dominant transistor design.

To appreciate why this matters, it helps to understand how the transistors inside every laptop, smartphone, and data centre actually work. Integrated circuits are built from complementary metal–oxide–semiconductor field-effect transistors, or MOSFETs, which switch electrical current by raising or lowering an energy barrier. In the OFF state, charges face a barrier they cannot cross; when a gating voltage is applied, charges gain enough thermal energy to spill over the top of that barrier in a process called thermionic emission. The steepness of this transition, measured by a figure known as the subthreshold swing (SS), determines how much voltage is needed to flip the transistor from OFF to ON. Here nature intervenes: because thermionic emission depends on the thermal distribution of electron energies, the subthreshold swing of any MOSFET cannot fall below 60 millivolts per decade of current at room temperature. That is the Boltzmann limit, and it is not an engineering shortfall but a consequence of statistical mechanics itself.

The consequences of this limit are profound. As chipmakers pack more transistors onto each processor, the 60 mV decade⁻¹ floor forces operating voltages to remain far higher than ideal, which means wasted power, wasted heat, and a hard ceiling on energy efficiency. Advanced MOSFETs typically require gate-voltage ranges of around 800 millivolts to operate, and every millivolt of that overhead is multiplied billions of times across a modern chip. For the artificial intelligence accelerators now driving enormous growth in global electricity consumption, the inability to switch transistors at lower voltages has become one of the defining engineering challenges of the decade. Breaking the 60 mV barrier is therefore not an incremental improvement but a potential inflection point for the entire industry.

The escape route identified by physicists is quantum tunnelling. Instead of forcing electrons to climb over an energy barrier, a tunnelling field-effect transistor (TFET) allows them to pass straight through it, exploiting the quantum-mechanical probability that particles can traverse barriers that would classically be impenetrable. Because tunnelling probability depends on the barrier’s width and height rather than on the thermal energy of the electrons, a TFET can in principle achieve subthreshold swings steeper than 60 mV decade⁻¹ even at room temperature. The IRDS has singled out TFETs as the most promising alternative to MOSFETs precisely for this reason. In practice, however, experimental TFETs have struggled for years with a frustrating trade-off: devices that achieved steep switching typically delivered painfully low output currents, undermining their usefulness in real circuits.

Prof. Hao’s team solved this problem with an elegantly engineered material system. Using pulsed laser deposition (PLD), a technique in which intense laser pulses vaporise a target material so that it recondenses as an ultra-thin film, the researchers fabricated an alternating heterostructure of two-dimensional bismuth (Bi) and indium selenide (InSe) layers. The choice of bismuth is the crucial insight. In its bulk form, bismuth is a semi-metal, a material that is neither a proper conductor nor a proper semiconductor. But when reduced to two-dimensional form with precise control over the layer structure at the nanoscale, bismuth transforms into a semiconductor. This transformation allowed the team to engineer an ideal energy band alignment between the bismuth and the indium selenide, creating exactly the conditions needed for charge carriers to tunnel efficiently from one material into the other through the quantum tunnelling mechanism.

The performance figures reported in the study are striking. The resulting Bi/InSe TFET achieved subthreshold swing values well below the 60 mV decade⁻¹ thermionic limit, and it maintained this steep switching behaviour across six orders of magnitude of current, a range that matters enormously for practical digital logic, where transistors must remain reliably OFF across many conditions rather than only at a single operating point. Remarkably, the device accomplished all of this at room temperature, on standard centimetre-scale silicon substrates, without exotic cryogenic cooling or specialised wafer treatments. The operating gate-voltage range required was only 160 millivolts, a fraction of the roughly 800 millivolts demanded by advanced MOSFETs, translating directly into the kind of power savings that next-generation computing demands.

Just as importantly, the device resolved the long-standing weakness of previous experimental TFETs. The PolyU-led team demonstrated a high output current of up to several microamps per micrometre alongside an exceptionally high ON/OFF current ratio. Output current is not a vanity metric: it determines whether a single transistor can drive multiple downstream logic gates, a capability engineers call fan-out, and whether signals propagate through a circuit with minimal delay. A steep-switching transistor that cannot deliver adequate current would force designers into cumbersome workarounds and erode the very efficiency gains it promises. By combining steep slopes with robust current drive, the Bi/InSe device demonstrates compatibility with existing integrated-circuit design practices and even the potential for a generational upgrade of current chips rather than a disruptive replacement.

The manufacturing dimension of the work may prove as consequential as the physics. Pulsed laser deposition has long been valued in research laboratories for its precision, but questions have lingered about whether it can serve high-precision, wafer-scale production of two-dimensional materials. This study demonstrates the practical viability of PLD for exactly that role, producing uniform ultra-thin heterostructures on silicon substrates that are the backbone of the existing semiconductor industry. Because the device integrates seamlessly with traditional silicon-based manufacturing processes, the researchers argue that their approach provides a scalable roadmap toward energy-efficient microchips, rather than a laboratory curiosity that would require an entirely new industrial ecosystem to deploy. That compatibility with ultra-short channel lengths, which two-dimensional materials are particularly well suited to support, positions the technology for the transistor geometries that future process nodes will demand.

The implications extend well beyond the laboratory bench. Ultra-low-power, high-performance integrated circuits built on tunnelling transistors could reshape the energy economics of artificial intelligence, where specialised hardware already consumes power on the scale of entire cities, and where every reduction in switching voltage compounds across billions of operations per second. Prof. Hao has emphasised that the technology paves the way for the ICs essential to emerging AI chips and advanced semiconductor applications, and the publication of the findings in Science signals that the broader research community regards the result as a landmark. For decades, the Boltzmann limit has stood as an immovable fact of life for chip designers, a boundary drawn by thermodynamics itself. By replacing thermionic emission with quantum tunnelling in a carefully crafted two-dimensional heterostructure, the PolyU-led team has shown that the boundary can be crossed, and in doing so has brought a long-awaited experimental technology a decisive step closer to commercial reality.

Subject of Research: A quantum-tunnelling field-effect transistor based on two-dimensional bismuth and indium selenide heterostructures that overcomes the Boltzmann switching limit in integrated circuits

Article Title: PolyU develops quantum-tunnelling field-effect transistor to overcome barriers to integrated-circuit chip development

Article References: PolyU develops quantum-tunnelling field-effect transistor to overcome barriers to integrated-circuit chip development. (n.d.). Original publication

Image Credits: AI Generated

DOI: Not provided

Keywords: quantum tunnelling, tunnelling field-effect transistor, TFET, two-dimensional materials, bismuth, indium selenide, Boltzmann limit, subthreshold swing, pulsed laser deposition, integrated circuits, low-power electronics, AI chips