Quantum-dot cellular automata, or QCA, is one of the most actively explored alternatives to complementary metal–oxide–semiconductor technology, the CMOS framework that underpins virtually every chip manufactured today. In a QCA circuit, the basic unit is a square cell containing four quantum dots, with two mobile electrons that tend to occupy diagonally opposite dots. Because there are two possible diagonal arrangements, each cell can represent a binary one or a binary zero. Information propagates not through wires carrying current but through Coulombic interactions: the electron configuration of one cell influences its neighbor, and arrays of cells can be arranged to perform logic operations. The result is a technology that promises switching speeds in the terahertz range, feature sizes at the molecular scale, and power consumption orders of magnitude below conventional electronics.

The centerpiece of the new work is a D-latch, a fundamental building block of digital memory that holds a single bit of data as long as an enable signal remains active. Latches are the precursors to flip-flops and registers, and any practical QCA-based processor would need thousands of them. Wani and Kassa’s design uses a majority-feedback architecture, exploiting the majority gate that serves as the native logic primitive of QCA. A majority gate outputs the value held by the majority of its three inputs, and by feeding the output back into one of the inputs, the circuit can hold its state indefinitely, which is precisely the behavior required of a latch. The elegance of this approach lies in its economy: instead of assembling latches from many separate logic gates, the feedback structure folds the storage function into a small cluster of cells.

The numbers reported in the study are striking. The optimized D-latch requires only 14 QCA cells arranged in a single layer and occupies a footprint of just 0.007 square micrometers. Single-layer designs are particularly valuable because multi-layer QCA fabrication, which stacks cells above one another, remains one of the most difficult manufacturing challenges facing the technology. By keeping everything on one plane, the researchers sidestep a major engineering bottleneck. Compared with a similar latch previously reported in the literature, the new circuit reduces the layout area, the latency, and the overall QCA cost, a composite metric that combines cell count, wire crossings, and the area consumed by the design.

Latency matters as much as area in memory design. In QCA, information ripples through the cell array one clock zone at a time, so the number of clock zones a signal must traverse determines how quickly the circuit responds. Each clocking zone in a QCA layout is driven by a four-phase clock that pumps information forward, and every additional zone adds delay and switching energy. By carefully arranging cells to minimize the critical path, the researchers produced a latch that settles to its stored value with fewer clock cycles than competing designs. For memory arrays, where read and write operations occur billions of times per second, such savings compound into significant gains in throughput and efficiency.

The second contribution of the paper addresses a practical requirement of real memory systems: the ability to deliberately overwrite stored data. The researchers extended their latch into a 15-cell variant equipped with SET and RESET control signals, making it suitable for use as a static random-access memory cell. In conventional SRAM, each bit is stored in a cross-coupled pair of inverters that can be written and read through access transistors. The QCA equivalent achieves the same function through its majority-feedback structure, with the SET and RESET inputs allowing the cell to be forced into a known state regardless of what was previously stored. This control capability is essential for initializing memory, clearing registers, and implementing the write operations that random-access memory demands.

Power analysis revealed another advantage of the SET/RESET-enabled design. Using QCAPro, a simulation tool that models the thermodynamic behavior of QCA circuits, the researchers mapped the energy dissipation and polarization characteristics of both circuits. The 15-cell memory cell was found to reduce peak energy dissipation by approximately 22 percent relative to the 14-cell baseline latch. This counterintuitive result, in which an additional cell yields lower peak power, reflects the way control signals can steer the circuit through lower-energy switching paths. In a technology whose central promise is ultra-low power consumption, trimming energy at the level of individual memory cells is a meaningful step toward practical nanoelectronic systems.

All designs were implemented and functionally verified in QCADesigner version 2.0.3, the standard simulation environment for QCA research. Functional verification confirms that the circuits produce the correct logical outputs across their input space, while the power and polarization analyses in QCAPro provide a window into the physical behavior of the electrons within each cell. This combination of logic-level and energy-level simulation is the accepted methodology in the QCA community for evaluating whether a proposed circuit is not only logically correct but also physically plausible and energy-efficient. The study reports that both circuits performed as intended, validating the majority-feedback approach as a reliable template for memory elements.

The significance of this work extends beyond the specific circuits described. Memory is one of the most demanding tests of any candidate post-CMOS technology, because practical systems require enormous arrays of identical, reliable, low-power storage elements. Demonstrating a latch and an SRAM cell with minimal cell counts, single-layer layouts, and quantified energy savings provides a concrete data point in the ongoing comparison between QCA and incumbent technologies. If QCA is ever to move from simulation to fabrication at scale, designs like these, which minimize the number of cells and avoid multi-layer complexity, will define the benchmarks that manufacturing processes must meet.

Considerable challenges remain before quantum-dot cellular automata can challenge silicon in commercial products. Fabricating and clocking arrays of quantum dots with the required precision, maintaining coherence at room temperature, and integrating millions of cells are problems that no laboratory has yet solved. But each incremental improvement in circuit density, latency, and power efficiency brings the field closer to viability. Wani and Kassa’s optimized latch and memory cell, published as open-access research with a permanent DOI, add to a growing library of compact QCA primitives that future designers can assemble into larger systems. As CMOS scaling slows, such foundational work on alternative computing substrates may prove to be among the most consequential research of the coming decade.

Subject of Research: Quantum-dot cellular automata memory circuit design for nanoelectronics

Article Title: An optimized majority-feedback QCA D-latch and SET/RESET-enabled SRAM cell for compact, low-latency nanoelectronic memory design

Article References: Wani, P., & Kassa, S. (2026). An optimized majority-feedback QCA D-latch and SET/RESET-enabled SRAM cell for compact, low-latency nanoelectronic memory design. Scientific Reports. https://doi.org/10.1038/s41598-026-74675-1

Image Credits: AI Generated

DOI: 10.1038/s41598-026-74675-1

Keywords: quantum-dot cellular automata, QCA, nanoelectronics, SRAM, D-latch, memory design, power dissipation, latency, CMOS, majority gate, QCADesigner, QCAPro

The review, authored by Nada Salem, Ahmed Shaker, Mahmoud Ossaimee, Ahmed Saeed, Mohamed Abouelatta, and El-Sayed M. El-Rabaie, takes an unusually integrated approach. Rather than treating device physics, manufacturing, and circuit applications as separate silos, the authors connect the atomic structure of carbon nanotubes directly to transistor behavior and ultimately to commercial viability. This matters because the performance of a CNTFET is not determined by the nanotube alone; contact resistance, tube alignment, density control, metallic-tube removal, and compatibility with existing CMOS manufacturing all shape whether carbon can genuinely replace silicon in a factory setting.

At the heart of the technology lies a deceptively simple material trick. A carbon nanotube is a sheet of graphene rolled into a cylinder roughly one nanometer in diameter, and the precise way it is rolled, defined by its chirality indices (n, m), determines whether it behaves as a metal or a semiconductor. Tubes in which the difference between the two indices is divisible by three are nominally metallic, while the rest are semiconducting. For semiconducting single-walled tubes, the bandgap scales approximately inversely with diameter, following the relation Eg of about 0.84 divided by the diameter in nanometers. That simple formula gives device engineers a powerful tuning knob: choosing the tube diameter effectively sets the threshold voltage, the leakage current, and the ON-state current of the resulting transistor.

The physics inside these devices is equally striking. Because carriers are confined to a one-dimensional channel, transport can approach the ballistic limit, where electrons traverse the channel without scattering. Clean carbon nanotube channels have demonstrated carrier mobilities of roughly 1,000 to 10,000 square centimeters per volt-second, an order of magnitude or more above scaled silicon, with characteristic carrier velocities of 2 to 5 times ten to the seventh centimeters per second against a theoretical Fermi velocity ceiling near 8 times ten to the seventh. Subthreshold swings can approach 60 to 80 millivolts per decade, and ON/OFF current ratios spanning 10^5 to 10^8 have been reported depending on diameter, contacts, and dielectric engineering. These numbers explain why researchers have chased carbon nanotubes since the first CNTFET was demonstrated in 1998.

Architecture has evolved considerably since those early proof-of-concept devices. Back-gated transistors, in which the silicon substrate itself acts as the gate, were simple to build but suffered from contact resistances of a megohm or more and weak electrostatic control. Top-gated designs introduced thin dielectrics deposited by atomic layer deposition, tightening gate coupling and enabling individual devices to be isolated on a single wafer. Wrap-around or gate-all-around structures, demonstrated in 2008, surround the nanotube entirely, suppressing leakage and short-channel effects most effectively. Suspended devices, in which the tube hangs free over a trench, minimize substrate scattering and reveal the intrinsic transport properties of the material, though mechanical instability and limited dielectric options keep them largely a laboratory tool.

Modeling this zoo of devices has produced a rich theoretical landscape. Ballistic models, built on the Landauer formalism, estimate the performance ceiling of ideal short-channel devices. Quasi-ballistic and non-ballistic models add phonon scattering through virtual-source and Landauer-Büttiker approaches, capturing the roughly 30 percent current reduction that dissipative transport imposes in realistic channels. Tunneling-based compact models account for band-to-band tunneling that dominates in small-bandgap tubes under bias, while full non-equilibrium Green’s function formulations solve quantum transport self-consistently with electrostatics, linking device behavior directly to the chiral index of the tube. For circuit designers, SPICE-compatible compact models such as the Stanford virtual-source CNFET model bridge the gap, embedding quantum capacitance, contact resistance, and ambipolar conduction into tools that can evaluate logic, memory, and radio-frequency circuits.

Fabrication remains the decisive battleground. Modern processes grow horizontally aligned nanotube arrays on quartz by chemical vapor deposition at densities near three tubes per micrometer, transfer them to oxidized silicon wafers, selectively remove metallic tubes, and deposit high-k gate stacks of titanium dioxide with titanium-platinum electrodes. The resulting devices show improved ON/OFF ratios and reduced device-to-device variability, and the low processing temperatures make the route compatible with CMOS thermal budgets. On a very different frontier, aerosol jet printing has been used to fabricate working CNTFETs on flexible Kapton substrates using silver ink electrodes and cross-linked polymer dielectrics, opening a path toward wearable and bendable electronics that rigid silicon cannot serve.

The application portfolio is expanding fast. CNTFET biosensors have detected the H1N1 virus, DNA modifications, prostate-specific antigen at concentrations from 5 to 5000 picograms per milliliter, and SARS-CoV-2 spike protein epitopes within minutes, exploiting the nanometer-scale match between tube and biomolecule. In memory research, devices using hafnium oxide gates have achieved write and erase operations with 100-nanosecond pulses, roughly 10,000 times faster than earlier carbon nanotube memory, with retention exceeding four hours and endurance past 18,000 cycles. Digital demonstrations include 1-kilobit six-transistor SRAM arrays built with carbon nanotube CMOS, ternary logic gates that combine CNTFETs with resistive memory, and approximate multipliers for energy-efficient image processing. Wafer-scale synaptic transistors exploit the sensitivity of nanotubes to charged defects, positioning carbon at the heart of neuromorphic computing architectures that dissolve the boundary between logic and memory.

Even with this momentum, the review is candid about the barriers. Chirality-controlled synthesis of high-purity semiconducting tubes at wafer scale remains unsolved, and even small diameter variations shift bandgaps enough to scatter threshold voltages across a chip. Residual metallic tubes create leakage paths, contact engineering at the metal-carbon interface still introduces Schottky barriers and variability, and self-heating in real devices, where nanotube-to-substrate thermal boundary resistance limits heat dissipation, threatens reliability despite the exceptional intrinsic thermal conductivity of individual tubes. Uniform high-k dielectric deposition on chemically inert nanotube surfaces, variation-aware compact modeling, and back-end-of-line integration with existing CMOS flows round out the challenge list.

What emerges from the full picture is a technology standing at a genuine inflection point. The intrinsic material advantages of carbon nanotubes, from near-ballistic transport and diameter-tunable bandgaps to mechanical flexibility and bioscale sensitivity, are no longer in dispute. The remaining work is industrial: scalable purification, wafer-level alignment, stable low-resistance contacts, and standardized benchmarking against silicon and emerging two-dimensional materials. If those pieces fall into place, the authors conclude, CNTFETs are strong contenders to deliver the high-performance, energy-efficient, and miniaturized electronics that the next generation of computing, sensing, and communication systems will demand.

Subject of Research: Carbon nanotube field-effect transistors as post-silicon electronic devices

Article Title: Structure, modeling, fabrication, and applications of carbon nanotube field-effect transistors: a comprehensive review

Article References: Salem, N., Shaker, A., Ossaimee, M., Saeed, A., Abouelatta, M., & El-Rabaie, E.-S. M. (2026). Structure, modeling, fabrication, and applications of carbon nanotube field-effect transistors: a comprehensive review. Results in Physics, 89, Article 108749. https://doi.org/10.1016/j.rinp.2026.108749

Image Credits: AI Generated

DOI: 10.1016/j.rinp.2026.108749

Keywords: carbon nanotubes, CNTFET, field-effect transistors, post-silicon electronics, Moore's law, bandgap engineering, neuromorphic computing, biosensors, SRAM, CMOS compatibility, quantum transport, flexible electronics