The research, published in the journal Discover Sustainability, was conducted by Harimukti Wandebori, Anak Agung Ngurah Tata Pinandhika, and Bernadetta Nadya Amarani Sitompul of the School of Business and Management at Bandung Institute of Technology. Their starting point was a long-standing unresolved question in the sustainability literature: do the very capabilities that keep small firms viable in volatile markets also move them toward greener practices? Most previous studies could not answer this because they collapsed economic, social, and environmental performance into a single composite score, obscuring exactly the differences that matter most for policy and practice.

The team focused on strategic agility, a dynamic capability that combines two distinct components: market responsiveness, meaning the speed with which a firm detects and reacts to changes in customer needs, competitor moves, and emerging threats; and resource fluidity, meaning the ease with which money, people, and equipment can be redeployed across activities. They also modelled three separate channels through which agility might indirectly influence sustainability: managerial ties with buyers, ties with suppliers, and ties with government officials. Crucially, each channel was specified separately, and each of the three sustainability pillars was treated as a distinct outcome rather than blended into an index.

The survey gathered responses from 179 strategic decision makers in Indonesian micro and small enterprises. The measurement design showed unusual care for a survey study of this kind. Predictor and outcome blocks used deliberately differentiated response anchors so that, for example, economic performance was rated relative to competitors while environmental practices were rated on frequency of use. Two attention check items with prescribed answers were embedded at separate points, completion times were recorded automatically, and a marker variable built from questions about attitudes toward the colour blue allowed the researchers to test statistically whether common method bias was inflating their estimates. Analysis proceeded with partial least squares structural equation modelling, a technique suited to complex path models with modest samples.

The headline result was a clear asymmetry. Strategic agility predicted economic performance with a path coefficient of 0.409 and social performance with 0.365, both medium effect sizes, but environmental performance at only 0.218, roughly half the strength of the other two. Because the outcome scales used different anchors, the team checked the gap on scale-free metrics. On latent correlations, the environmental pillar separated from the economic pillar by 0.229 and from the social pillar by 0.196, with bootstrap intervals that excluded zero in both cases. On the metric of partial coefficients, only the separation from the economic pillar was statistically distinguishable, and the authors are explicit that their title claims only that contrast. The gap also passed a battery of robustness checks: the environmental block showed the lowest ceiling rate and the most symmetric response distribution of the three, which is the opposite of what a ceiling effect or social desirability bias would produce, and correcting for unequal reliability across blocks widened rather than narrowed the difference.

Perhaps the most sobering finding concerned prediction. The model achieved out-of-sample predictive relevance for the economic and social pillars, meaning the estimated structure genuinely anticipated new observations, but it achieved none for the environmental pillar. In other words, the capability-and-ties framework that works for explaining how small firms prosper and serve their communities simply does not contain enough signal to forecast their environmental behaviour. The indirect effect of agility on environmental performance through managerial ties was statistically equivalent to zero against a triviality bound of 0.10, tested with two one-sided tests on the bootstrap distribution.

The tie-based channels themselves fared almost entirely empty. Of the nine paths running from the three tie types to the three pillars, only one, buyer ties to social performance, reached significance at a coefficient of 0.193. The authors handle this carefully: one significant result out of nine tests is a count compatible with chance, and it does not survive correction for multiplicity. They report it as a pattern to be tested in future work rather than as an established mechanism, a level of statistical honesty that stands out in a literature where such a result might otherwise be presented as a discovery.

The study also probes what the gap means mechanistically, and here an item-level analysis delivers a subtle twist. One plausible explanation for weak environmental performance would be simple economics: environmental practices cost money without returning it, so agile firms invest where returns register. If pricing were the boundary, the one environmental practice that pays for itself, reducing waste and resource inefficiency, should attract agility’s influence more strongly than the two that do not. The item-level estimates ordered the three environmental items exactly as that reward-boundary argument predicts, but no within-block difference was statistically distinguishable. Pricing alone, therefore, is not the whole story; the boundary appears to lie in whether a firm’s existing routines register any return at all, and environmental returns rarely do for a small enterprise.

There is an important design caveat the authors state plainly: because a cross-sectional sample contains only surviving firms, the strong economic association is consistent with two competing accounts. Under a capability account, agility genuinely produces better economic outcomes; under a selection account, agile firms simply survive longer and therefore appear in the sample more often. The design cannot separate the two, and the researchers do not pretend otherwise. Nor could the study resolve whether the agility gap differs between resource-rich and resource-poor firms: multigroup comparisons across six operationalisations of resource endowment produced signs that flipped between splits and no significant differences, and a power analysis showed the observed differences all fell below the minimum the sample could detect.

The policy implication, the authors argue, follows directly from the pattern of results. If capability building alone does not reach the environmental pillar, because the returns from environmental practices are invisible to the routines that small firms already have, then progress will depend on instruments that make those returns visible and required: regulations that set minimum standards, incentives that convert environmental savings into financial ones, and market mechanisms that reward green practices through the buyers small firms already depend on. For the vast population of micro and small enterprises in emerging economies, the path to environmental sustainability is not a matter of becoming more agile. It is a matter of changing the payoffs the environment of business, rather than the natural one, currently provides.

Subject of Research: The relationship between strategic agility, managerial ties, and the three pillars of sustainability in Indonesian micro and small enterprises

Article Title: Strategic agility reaches the environmental pillar of small firm sustainability more weakly than the economic pillar: disaggregated evidence from Indonesian micro and small enterprises

Article References: Wandebori, H., Pinandhika, A. A. N. T., & Sitompul, B. N. A. (2026). Strategic agility reaches the environmental pillar of small firm sustainability more weakly than the economic pillar: disaggregated evidence from Indonesian micro and small enterprises. Discover Sustainability. https://doi.org/10.1007/s43621-026-04788-0

Image Credits: AI Generated

DOI: 10.1007/s43621-026-04788-0

Keywords: strategic agility, small and medium enterprises, sustainability, triple bottom line, environmental performance, managerial ties, Indonesia, PLS-SEM, dynamic capabilities, emerging economy, green practices, business strategy

The Electrical Testing Board, described in the open-access journal HardwareX by a research team led by Geu M. Puentes-Conde of the Universidad Autónoma de Ciudad Juárez, is a four-layer FR-4 board measuring 187 by 160 millimeters, complete with an integrated carrying handle and an 88-pin gold-finger edge connector designed for backplane integration. Rather than attempting to replace a full-scale industrial test station, the platform is positioned as a compact, reproducible alternative for circuit prototyping, academic instruction and small-scale manufacturing, where the economics of full in-circuit testing infrastructure remain prohibitive. The hardware is released under the CERN Open Hardware License v2.0, its firmware under the GNU General Public License v3.0, and its documentation under Creative Commons Attribution 4.0.

In-circuit testing verifies the values and structural integrity of individual components soldered onto a board, while functional testing validates the overall operational behavior of the finished device. Both methodologies are indispensable in industry because defects can arise from many sources: improper material handling, components that fall outside parametric tolerances, failures in surface-mount assembly equipment, or simple human error. Commercial systems from vendors such as Keysight Technologies, Teradyne and SPEA apply voltage or current stimuli through test nodes, route the resulting signals through multiplexers and conditioning stages involving amplification, filtering and linearization, and finally digitize the analog result to yield electrical parameters such as resistance, capacitance, inductance, voltage, current and short- or open-circuit status. The new board follows this same architectural logic, but in a radically miniaturized and democratized form.

At the heart of the design is a three-board modular stack. A main PCB houses the functional test modules, a relay PCB carries the switching matrices, and a pluggable MCU PCB hosts the primary controller, a Microchip PIC32MX795F512L running at 80 megahertz. Because the core module is a daughterboard, a failed microcontroller can be swapped in seconds without any desoldering. Two slave PIC18F4620 microcontrollers, managed over the I2C bus, drive the relay matrices and handle auxiliary input and output tasks. Sixteen test nodes connect the device under test to four relay-based switching buses, labeled V+, M+, M− and G−, which route signals among the programmable power supplies, the digital multimeter subsystem, comparators, programmable pull-up and pull-down networks, and protection circuitry. The reed relays at the center of these matrices, Coto 9012-12-11 units, actuate in roughly 0.35 milliseconds, allowing a complete in-circuit or functional measurement cycle of 10 to 50 milliseconds per device.

The measurement capabilities are broad. The onboard digital multimeter offers voltmeter ranges of 0 to 10 volts and 0 to 100 volts through a 16-bit successive-approximation ADC paired with a low-drift 10-volt precision reference, ammeter ranges from 1 microampere to 1 milliampere across three calibrated gain stages built around a transimpedance amplifier, resistance measurements from 0.5 ohms to 1 megohm using a ratiometric voltage-divider method, and capacitance measurements from 10 nanofarads to 220 microfarads. Rather than replicating the expensive AC voltammetry and synchronous phase-detection approach used in commercial systems, the designers adopted a direct interface circuit technique: the unknown capacitor is charged and then discharged through a known reference resistor while an embedded timer measures the interval until a comparator threshold is crossed, from which capacitance follows from simple logarithmic relations. The method trades some accuracy at the low end of the range for dramatic reductions in circuit complexity and cost.

Validation against reference instrumentation suggests the trade-offs are manageable for its intended audience. Benchmarked against an HP 34401A six-and-a-half-digit multimeter, the voltmeter stayed within 0.14 percent relative error at low-voltage test points of 1, 3.3 and 5 volts, with error and variance growing at higher voltages, reaching about 0.91 percent at 90 volts, a divergence the authors attribute to attenuation networks and parasitic loading in the high-voltage path. The ammeter achieved sub-percent errors at points such as 5 microamperes and 150 microamperes, though deviations grew near the top of each subrange. Resistance measurements remained below 1 percent relative error across 1 kilohm to 1 megohm, while the lowest point, 0.5 ohms, showed an 11.31 percent error driven by relay contact resistance, a systematic offset the firmware can compensate through tare calibration. Capacitance accuracy was weakest at 10 nanofarads, with errors above 30 percent, but settled to roughly 8 to 10 percent for bulk values of 100 and 220 microfarads.

Beyond raw metrology, the platform is designed for integration into automated test equipment environments. It communicates with a host computer or programmable logic controller over RS-232, opto-isolated UART buses, or Ethernet through a Microchip LAN8720 physical layer transceiver, using a checksum-protected packet protocol in which command bytes select tasks such as automated testing, limit transmission and data retrieval. Up to 12 boards can be daisy-chained under a single host controller, each addressed by a dedicated digital selection line and monitored through a busy-status output. In a demonstration implementation, eight boards ran parallel end-of-line tests across a multi-cavity fixture pallet, performing power-up sequencing, firmware register extraction over UART, harness continuity checks, battery voltage profiling, quiescent current measurement, pneumatic actuation of buttons via high-current relay outputs, busbar presence verification and even acoustic pattern validation through the onboard audio conditioning circuit, a capability absent from the commercial systems the authors compared against.

The team is candid about the limits of the platform. It supports a single device under test per board, offers 16 test nodes compared with up to 2,592 on a two-module Keysight i3070 system, and its practical analog bandwidth is deliberately limited to DC to 10 kilohertz by the relay switching network. It cannot measure inductance, does not support IEEE 1149.1 JTAG boundary-scan testing, and is not certified for industrial deployment, restricting its scope to controlled laboratory, prototyping and small-production settings operated by qualified engineering personnel. Long-term relay endurance, thermal drift, fault injection robustness and full metrological characterization were also left as explicit future work. Power consumption, however, is modest: roughly 2.5 watts at idle and between 3.1 and 6 watts during typical testing routines.

The economic argument is nevertheless compelling. Where a complete commercial system with instrument cards, chassis and enclosure can run into six figures, the proposed assembly costs about $790 to fabricate, or an estimated $3,500 for a full system including host controller, enclosure, cables and test probes, still roughly an order of magnitude below the entry point of industrial hardware, which typically demands $25,000 to $250,000. All design files, schematics, firmware, bill of materials and even a debugging enclosure are openly available through a public repository, enabling any competent electronics laboratory to replicate or adapt the platform.

The implications extend beyond manufacturing quality control. The authors envision materials scientists using the programmable switching matrices and multimeter to map resistance and capacitance across novel conductive polymers or biological tissue samples, applied physics laboratories replacing bulky benchtop instruments in automated experiments, environmental researchers deploying the opto-isolated inputs and Ethernet interface as a ruggedized sensor node layer, and embedded acoustics teams exploiting the audio conditioning chain for voice and frequency pattern work. Future development will focus on integrating machine learning directly into the firmware layer to shorten test cycles and enable predictive fault isolation, along with expanding the physical node architecture to widen signal routing capacity and test coverage. For a field in which the cost of entry has quietly determined who can afford rigorous electrical verification, an open, sub-$1,000 testing platform may prove to be one of the more quietly disruptive hardware releases of the year.

Subject of Research: A low-cost modular open-hardware PCB assembly for in-circuit and functional testing of electronic devices

Article Title: A low-cost modular PCB assembly for functional and in-circuit testing

Article References: Puentes-Conde, G. M., Sifuentes, E., Molina, J., Enríquez-Aguilera, F., Bravo, G., & Ávila, A. H. (2026). A low-cost modular PCB assembly for functional and in-circuit testing. HardwareX, 28, Article e00844. https://doi.org/10.1016/j.ohx.2026.e00844

Image Credits: AI Generated

DOI: 10.1016/j.ohx.2026.e00844

Keywords: in-circuit testing, functional testing, open-source hardware, printed circuit board, automated test equipment, digital multimeter, relay switching matrix, electronics manufacturing, small and medium enterprises, microcontroller, capacitance measurement, HardwareX