The circuit at the heart of the study is the three-level active neutral-point-clamped converter, or 3L-ANPC, a workhorse topology in modern grid-tied systems. It appears in photovoltaic inverters feeding solar farms into the grid, in railway traction drives, and in the power supplies that keep data centers running. Compared with simpler two-level designs, the three-level ANPC produces cleaner output voltage and current waveforms with fewer harmonics, subjects its semiconductor switches to lower voltage stress, and reduces switching losses. Those advantages shrink the size and weight of passive components such as filters, which is a major reason the topology has spread so widely through industrial applications and has become a focal point for engineers chasing higher power density.

The pressure to improve these converters comes from a fundamental materials problem. Conventional silicon devices, for all their maturity and low cost, are constrained by their intrinsic physical properties and struggle to meet the demands of high-frequency, high-efficiency, high-density operation. Silicon carbide, a wide bandgap semiconductor, switches far faster and loses far less energy in the process, making it the obvious successor. The catch is price: in high-current applications, a silicon carbide MOSFET typically costs six to eight times as much as a silicon IGBT and roughly twice as much as a silicon MOSFET, and the premium grows exponentially at higher current ratings. The industry’s answer has been the hybrid switch, a parallel combination of a high-current-rated silicon IGBT and a lower-current-rated silicon carbide MOSFET that captures much of the wide bandgap benefit at a fraction of the cost of an all-silicon-carbide design.

Hybrid switches have already found their way into 3L-ANPC converters in several configurations, each with trade-offs. Replacing only the two inner switches with hybrid devices lets the silicon carbide MOSFETs handle high-frequency switching while everything else operates at the fundamental frequency, but some silicon devices still endure high-frequency switching in certain schemes. Replacing the clamping and outer switches instead spreads the switching stress more evenly but leaves the inner devices as plain silicon. A third approach replaces the outer switches to balance thermal performance, at the cost of slightly lower overall efficiency. A fourth replaces the outer and inner switches together. In all of these prior designs, the researchers argue, the optimization is incomplete: either some devices that are not hybrid switches still switch at high frequency, or the topology fails to conduct both clamping branches simultaneously during the zero-voltage state, leaving conduction losses unnecessarily high.

The new topology, which the team calls the H-Si/SiC 3L-HANPC, replaces both the clamping switches and the inner switches with hybrid devices while keeping silicon IGBTs in the outer positions. Two coordinated tricks drive the efficiency gains. First, an optimized gate-drive timing scheme ensures that hard-switching events fall on the silicon carbide MOSFETs, whose unipolar structure makes their switching losses dramatically lower than those of bipolar silicon IGBTs, which suffer from slow transitions and tail-current losses. In the adopted timing pattern, the silicon carbide MOSFET turns on before and turns off after the silicon IGBT, with a half-microsecond delay in each direction, so the IGBT enjoys zero-voltage switching on both edges and contributes mainly conduction losses while the MOSFET absorbs the switching burden. Second, during the zero-voltage state the modulation strategy turns on both clamping branches at once, creating dual current conduction loops that lower the equivalent resistance of the current path and cut conduction losses in the hybrid switches.

The modulation itself uses phase-disposition pulse-width modulation, with the converter transitioning among defined switching states as the reference voltage crosses the carrier waveform. When the reference is positive, the circuit moves through the positive, zero, and intermediate states; when negative, it mirrors the sequence on the other half of the leg. Because the hybrid switches follow the silicon-carbide-first timing sequence, multiple switching states can occur within a single operating mode, and the team mapped each one to show how current flows through the MOSFETs, IGBTs, and body diodes during the transitions between the positive and zero states.

The second major contribution is a differentiated placement strategy that breaks with the convention of using identical hybrid switches everywhere. The researchers analyzed the root-mean-square currents flowing through each switch position under their modulation scheme and found that the inner switches carry roughly 1.7 times the RMS current of the clamping switches, because the inner devices conduct the full load current during the active state while the clamping devices carry only about half during the zero state. Since the inner switches also endure the most frequent transitions between active and zero states, concentrating the largest switching losses on their silicon carbide MOSFETs, they benefit most from a hybrid switch with a high silicon-carbide-to-silicon current ratio. The clamping switches, with lower currents and lower losses in both categories, can tolerate a cheaper, lower-current hybrid configuration without hurting performance.

Applying that logic with commercial devices, the team selected a high-ratio combination of a 35-ampere silicon carbide MOSFET and a 40-ampere silicon IGBT for the inner switches, and a lower-cost combination of a 16-ampere MOSFET and a 30-ampere IGBT for the clamping switches, sized against an 800-volt DC link, 220-volt output phase voltage, and 40-kilohertz switching frequency. The three-phase semiconductor cost of the proposed configuration came to 1,266.66 yuan, sitting between a cost-optimized traditional scheme at 1,087.98 yuan and a high-efficiency traditional scheme at 1,541.34 yuan. In other words, the differentiated design captures most of the efficiency of the expensive configuration while spending far less than it would cost to fit premium hybrid switches at every position.

Experimental validation on a three-phase platform with a 400-volt DC bus, 110-volt output, 18-ampere rated current, and 40-kilohertz switching confirmed the claims. Measured with a HIOKI PW6001 power analyzer with a basic accuracy of plus or minus 0.05 percent, the proposed H-Si/SiC 3L-HANPC achieved about 1.5 percent higher efficiency than a conventional all-silicon hybrid ANPC at unity power factor, and roughly 0.2 percent higher than the best competing hybrid topologies. At a power factor of 0.5, the gap widened to about 3 percent over the silicon baseline. Against the two traditional hybrid-switch configurations, the proposed differentiated scheme delivered slightly higher efficiency than the cost-optimized design under heavy load and only marginally lower efficiency than the premium design, placing it between the two across the operating range.

Thermal simulations in PLECS added a further argument for the differentiated approach. Compared with the cost-optimized scheme, the proposed configuration reduced the junction temperature of the inner switches by 2 to 12 degrees Celsius, while the clamping switches ran only 2 to 5 degrees warmer. Relative to the high-efficiency scheme, the inner switches performed identically and the clamping switches ran slightly warmer, but the overall temperature difference between the two positions narrowed, improving the thermal balance of the whole converter. The team concludes that the design combines the cost advantage of one traditional scheme, the efficiency of the other, and better thermal balancing than either, positioning the H-Si/SiC 3L-HANPC as a strong candidate for high-efficiency, high-power-density applications from solar inverters to traction systems, wherever engineers must squeeze every fraction of a percent of efficiency out of a constrained budget.

Subject of Research: Si/SiC hybrid-switch three-level ANPC converter topology with differentiated device placement for improved efficiency, cost, and thermal balance

Article Title: A three-level ANPC converter with differentiated Si/SiC hybrid switches in the inner and clamping positions

Article References: A three-level ANPC converter with differentiated Si/SiC hybrid switches in the inner and clamping positions. (n.d.). https://doi.org/10.3389/fenrg.2026.1786735

Image Credits: AI Generated

DOI: 10.3389/fenrg.2026.1786735

Keywords: power electronics, SiC MOSFET, Si IGBT, hybrid switch, three-level ANPC converter, converter efficiency, modulation strategy, conduction losses, switching losses, thermal performance, wide bandgap semiconductors, grid-tied inverters