Traditional transistor miniaturization has long driven performance gains in integrated circuits. However, as transistors and their connecting copper wires shrink into the sub-10 nanometer regime, the surrounding protective layers—essential for maintaining electrical integrity—resist further reduction. These layers, typically tantalum-based barrier and liner materials, must maintain a minimum thickness of around four nanometers. In future nanoscale interconnects, these coatings may consume nearly half the cross-sectional area of the copper wiring, severely throttling electrical conductivity and device speed. The NUS and Applied Materials team’s innovation resides in synthesizing an ultrathin WS₂ film, less than a nanometer thick, that simultaneously fulfills the dual role of barrier and liner, drastically slashing thickness without compromising performance.

This pioneering coating, grown on industry-standard 200-millimeter silicon wafers using a low-temperature thermal atomic layer deposition process at 350 degrees Celsius, exemplifies a remarkable confluence of scalability and compatibility. The process avoids plasma, guaranteeing conformal deposition with precise thickness control down to a single atomic layer. Notably, this method achieves uniform coverage in high aspect ratio trenches, exceeding 95% conformity even at depth-to-width ratios of 10:1. Such attributes position this WS₂ monolayer as a viable drop-in replacement within existing semiconductor fabrication lines, bridging the formidable divide between laboratory breakthroughs and industrial applicability.

The WS₂ film’s threshold thickness of approximately 0.7 nanometers contrasts starkly with the conventional six nanometer standard, enabling a future 20-nanometer-wide copper wire to retain over 90% of its conductive cross-section. This relatively unobstructed copper path translates into reduced electrical resistance and elevated current carrying capacity, directly enhancing chip speed and energy efficiency. Extensive electrical testing demonstrated a monumental reduction in resistance—exceeding a factor of one million—compared to uncoated counterparts. The superior adhesion properties offered by the WS₂ liner promote smooth and continuous copper film formation, vital for producing reliable, defect-free interconnects at such ultrathin dimensions.

Beyond adhesion, the WS₂ monolayer serves as a robust diffusion barrier that impedes copper migration into silicon and dielectric materials under thermal and electrical stress. In accelerated aging tests, conventional barrier-free copper rapidly reacted with underlying silicon, forming deleterious intermetallic compounds and defect clusters. In stark contrast, WS₂-coated samples exhibited no such degradation, maintaining pristine interfaces even after prolonged exposure. Remarkably, devices using the atomically thin barrier exhibited projected lifetimes surpassing unprotected designs by an order of magnitude, signaling a dramatic leap in device durability.

Central to the WS₂ film’s efficacy is its polycrystalline structure composed of myriad tiny grains and grain boundaries arranged in random orientations. Unlike continuous single crystals, where aligned grain boundaries can form direct diffusion channels, the staggered grain orientation in multilayer WS₂ films creates a complex labyrinth that frustrates copper atom penetration akin to the staggered offsets in a well-built brick wall. This insight, derived from computational modeling by NUS chemists, identifies nanoscale grain architecture as a key parameter in optimizing barrier functionality, challenging the entrenched paradigm that perfect crystallinity is always advantageous.

The discovery that a single atomic layer can supplant the combined barrier and liner stack confronts long-held assumptions in semiconductor interconnect design. Prior industry standards dictated separate layers with cumulative thicknesses of several nanometers to provide necessary protection and adhesion. By collapsing these essential roles into an atomically thin WS₂ sheet, researchers open new vistas for continuing Moore’s Law scaling into unprecedented regimes. Professor Silvija Gradečak, co-director of the NUS-Applied Materials Corporate Lab, emphasizes that this fundamental shift in approach heralds a new class of interconnect architectures tailored to atomically precise materials engineering.

The process’s compatibility with low thermal budgets—vital for avoiding damage to complex multilayer device stacks—and its wafer-scale uniformity underscore its readiness for integration into contemporary manufacturing ecosystems. These breakthrough properties allow semiconductor producers to adopt WS₂-based coatings without extensive equipment overhauls or processing disruptions, facilitating rapid technology transfer. Dr. Hippolyte Astier highlights that such advancements transcend the immediate generation of chips, positioning the industry to harness this technology across multiple forthcoming innovations extending out to 2037 and beyond.

Applied Materials’ Director of Engineering, Dr. John Sudijono, notes the criticality of merging academic ingenuity with industrial constraints through the Corporate Lab framework. The collaborative environment enabled iterative validation of WS₂ films under realistic fabrication conditions, ensuring the material meets demanding reliability, scalability, and process compatibility benchmarks. This convergence of theory, experimentation, and commercialization is essential to bridging the notorious gulf between laboratory demonstrations and full-scale production deployments in semiconductor manufacturing.

Looking forward, the team is exploring refined control over WS₂ grain orientation and microscopic interface phenomena to fine-tune long-term stability and electrical behavior. Further studies aim to exploit the low-temperature vapor-phase growth technique to deposit other two-dimensional materials within diverse chip components, expanding the scope of atomic-scale coatings in integrated circuit design. This foundational research not only sets a new standard for interconnect barriers and liners but also signals the inception of a broader materials revolution in microelectronics.

The ultrathin WS₂ monolayer innovation thus represents a monumental stride towards sustaining the pace of semiconductor evolution. By ingeniously combining barrier and liner functionality into a single atomic layer with industrially scalable fabrication, this discovery resolves a pressing miniaturization bottleneck, empowering the continuation of chip performance scaling in an era where every nanoscale dimension counts. As the semiconductor industry confronts the ultimate physical limits of transistor and interconnect shrinking, atomically precise materials like WS₂ will be vital enablers of future computational breakthroughs, underpinning the technology transformations of tomorrow.

Subject of Research: Not applicable

Article Title: Low-temperature wafer-scale growth of ultrathin tungsten disulfide for bifunctional interconnect barriers and liners

News Publication Date: 31-Mar-2026

Web References: https://doi.org/10.1038/s41928-026-01592-6

Image Credits: College of Design and Engineering, NUS

Keywords

Semiconductors, Microelectronics, Materials engineering, Materials science

The semiconductor manufacturing landscape traditionally hinges on EUV lithography, a technique instrumental in printing intricate circuits onto silicon substrates, forming the backbone of chips embedded in modern electronics such as smartphones, laptops, and an ever-expanding array of digital devices. EUV lithography depends on complex configurations involving precision mirrors, tin vapor light sources, and painstakingly crafted photomasks. However, available commercial EUV printers demand investments north of $200 million and occupy entire rooms, limiting their availability to only a handful of global corporations.

Responding to these challenges, the Texas engineering team, in collaboration with renowned research partners, embarked on reinventing the EUV lithography process. By reducing the architecture to its fundamental elements, they created a more versatile and modular system. This reimagined EUV printer is not only accessible to a broader range of users but opens new avenues for experimental modifications, accelerating developmental cycles in semiconductor research.

Beyond redesigning the hardware, the researchers merged this compact EUV device with an innovative lithographic technique: volumetric 3D patterning. Conventional EUV lithography processes are constrained to two-dimensional, layer-by-layer assembly of three-dimensional nanostructures, inherently slowing down production due to sequential exposure and alignment requirements. The volumetric 3D approach circumvents this barrier by enabling simultaneous patterning of multiple layers at once, cutting down exposure times from days to mere minutes without compromising nanoscale precision or feature complexity.

Chih-Hao Chang, a mechanical engineering professor and one of the lead authors of the study published in Nano Letters, highlights this transformative leap. He explains that although the pure printing duration might not be lengthy, the traditional repeated processing steps accumulate to prolonged fabrication times. Their volumetric method slashes this bottleneck, empowering researchers to prototype intricate 3D nanostructures rapidly, fostering innovation at an unprecedented pace.

This research represents a vital contribution to the National Science Foundation’s Future of Semiconductors (FuSe2) initiative, an ambitious program aimed at lowering the barriers and costs associated with semiconductor research. By creating practical, compact, and cost-effective EUV lithography systems, the Cockrell team supports the overarching goal of revitalizing semiconductor innovation and expanding participation beyond current industrial giants.

Currently, the team is actively testing novel EUV-sensitive materials developed collaboratively with UT Dallas and Johns Hopkins University, tailored specifically for their compact printer system. These material advances are crucial in optimizing the efficiency and resolution capabilities of the new fabrication platform, fine-tuning it to meet and potentially surpass existing industry standards.

Despite the exceptional promise, the researchers acknowledge that current limitations confine patterning to periodic nanostructures, primarily relevant for applications in photonics and memory chips. However, the long-term vision is ambitious: to engineer faster printers capable of crafting increasingly complex and smaller features, essential for the next generation of semiconductor switches. Such improvements directly translate into chips with enhanced computational power and energy efficiency.

Saurav Mohanty, a recent Ph.D. graduate and the study’s first author, envisages applications reaching far beyond the realm of semiconductors. He articulates that the ability to seamlessly pattern three-dimensional nanostructures could have tremendous impact in diverse fields including nanomedicine—for precise drug delivery systems—quantum computing architectures where nanoscale control is paramount, and the synthesis of novel materials with unique quantum or photonic properties.

This research is not merely an incremental update but a paradigm shift that redefines accessibility and scalability in semiconductor manufacturing. The miniaturization of EUV lithography equipment opens previously inaccessible experimentation avenues and democratizes a critical technology once monopolized by a select few. By enabling rapid and flexible nanofabrication, the Cockrell team’s innovation accelerates progress toward the pursuit of more powerful, efficient, and compact electronics.

As the semiconductor industry faces increasing pressures to sustain Moore’s Law and address the escalating costs of chip manufacturing, combining hardware innovation with advanced patterning strategies represents a holistic approach to overcoming these challenges. The future envisaged by these researchers includes faster prototyping periods, widespread experimental capabilities, and ultimately, the fabrication of semiconductor devices with unprecedented complexity and performance.

In conclusion, the work emerging from the Cockrell School of Engineering underscores the crucial interplay between mechanical engineering, materials science, and applied physics in pushing the boundaries of lithographic technology. The implications of this research resonate throughout the technology sector and beyond, promising to catalyze a wave of advancements not only in electronics but also in medicine, quantum sciences, and advanced material synthesis.

Subject of Research: Development of a compact and cost-effective extreme ultraviolet (EUV) lithography printer for rapid three-dimensional nanopatterning.

Article Title: Three-Dimensional Nanopatterning Using Extreme Ultraviolet Colloidal Talbot Lithography

Web References:

• DOI: 10.1021/acs.nanolett.6c01662
• Future of Semiconductors (FuSe2) – NSF Program

References:
Chang, C.-H., Mohanty, S., et al. “Three-Dimensional Nanopatterning Using Extreme Ultraviolet Colloidal Talbot Lithography,” Nano Letters, DOI: 10.1021/acs.nanolett.6c01662.

Image Credits: The University of Texas at Austin

Keywords

Materials engineering, Nanolithography, Semiconductors, EUV lithography, 3D patterning, Volumetric lithography, Nanomanufacturing, Integrated circuits, Photonics, Quantum computing, Advanced materials, Semiconductor research

Bettadapur’s background showcases a remarkable trajectory in prominent tech firms. Having held key leadership positions at industry giants such as ASML, Intel, and Lam Research, alongside roles in various Silicon Valley startups, he has an established history of scaling businesses and executing successful exit strategies. His proven capability in fostering innovation and executing strategic visions makes him an invaluable asset to Irresistible Materials as it strives to establish itself as a frontrunner in the EUV resist market.

Under Bettadapur’s guidance, Irresistible Materials aims to amplify the adoption of its innovative Multi-Trigger Resist (MTR™) platform. This platform, ingeniously crafted to address the strict requirements of EUV lithography, represents a significant advancement over conventional resist materials. With the semiconductor industry continuously pushing the limits of technology to achieve smaller microchip feature sizes, the need for advanced resist materials that enhance production efficiency and reduce costs becomes increasingly pertinent.

The introduction of the MTR technology has set a new benchmark in resist performance. Its expedited processing capabilities are a game changer, demonstrating a speed that is up to two times faster than existing options. This increased efficiency translates into substantial cost savings, potentially lowering the annual cost of ownership for EUV scanners by approximately $10-15 million, a significant reduction for high-tech manufacturing entities aiming for profitability without compromising quality.

Irresistible Materials’ strong foundations give it a competitive edge in the global market. Since its inception in 2010, the company has diligently expanded its partner network and developed a comprehensive portfolio that encompasses innovative resists for various lithography applications, including EUV and electron beam technologies. The strategic direction provided by Bettadapur is anticipated to bolster these initiatives further, paving the way for sustained growth and groundbreaking innovations.

The MTR platform embodies state-of-the-art technology designed specifically for EUV lithography applications. The proprietary technology utilizes a small-molecule design that allows for enhanced resolution and pattern fidelity—crucial factors in the relentless quest for smaller chip structures. This innovative approach ensures superior performance, addressing the complexities posed by traditional resist materials that often hinder progress in the semiconductor sector.

The implications of the MTR platform stretch beyond mere performance enhancement. The technology is developed with sustainability in mind, boasting formulations that are free of per- and polyfluoroalkyl substances (PFAS) and other hazardous metals. This commitment to environmentally responsible manufacturing processes aligns with the industry’s increasing demand for greener solutions, reinforcing Irresistible Materials’ position as a socially responsible technology provider.

As the series of industry challenges necessitate continuous advancement in EUV lithography, Irresistible Materials stands at the forefront, equipped to navigate and tackle these complex demands. According to industry analysis, the global EUV photoresist market is projected to experience substantial growth, with an estimated compound annual growth rate (CAGR) exceeding 20% and approaching a market value of $1 billion by the decade’s end. Bettadapur’s leadership is poised to align the company’s strategic initiatives with these booming market trends.

Daniel Armbrust, the Chairman of the board at Irresistible Materials, expressed enthusiasm about the new appointment, stating that Bettadapur’s extensive experience across various technological landscapes uniquely positions him to guide the company toward a leadership role in the EUV resist sector. His entrepreneurial spirit and vast industry connections will not only enhance the company’s market penetration but will also foster collaborative partnerships that are essential in a technology-driven ecosystem.

In conclusion, the appointment of Dinesh Bettadapur as CEO of Irresistible Materials marks a significant turning point for the company and the EUV lithography sector as a whole. With an impressive history tutoring multiple startups to success and an unwavering commitment to innovation, Bettadapur’s leadership promises to usher in a new era of advancements in resist materials that could redefine semiconductor manufacturing. Irresistible Materials is now positioned to make waves in the market, challenging established norms and setting new standards in technology and efficiency.

Ultimately, the advancements expected from Irresistible Materials under Bettadapur can potentially transform the landscape for not only manufacturers but consumers alike, propelling the semiconductor industry into a phase characterized by unprecedented growth and innovation.

Subject of Research: Development of novel resist materials for EUV lithography
Article Title: Dinesh Bettadapur Appointed CEO of Irresistible Materials to Drive Semiconductor Innovation
News Publication Date: October 2023
Web References: Irresistible Materials
References: [Irresistible Materials Press Release, 2023]
Image Credits: Credit: Irresistible Materials

Keywords: EUV lithography, Dinesh Bettadapur, Irresistible Materials, semiconductor manufacturing, Multi-Trigger Resist, resist materials, sustainable technology.