Molybdenum disulfide, a prototypical TMD, captures attention because of its unique crystalline structure composed of three atomic layers: a central molybdenum atom layer flanked by sulfur atoms on either side. This extreme thinness — only three atoms thick — endows it with exceptional electronic, optical, and mechanical properties advantageous for next-generation devices. However, the challenge lies in the precise removal of the top sulfur layer during device fabrication without compromising the integrity of the underlying molybdenum. The delicate balance between effective etching and structural preservation requires innovative approaches beyond conventional physical methods.

The primary technique used for etching semiconductor materials is plasma processing. Plasma, often called the fourth state of matter, consists of ionized gases with energetic ions and electrons capable of selectively dislodging atoms from a surface. This technology, extensively researched at the U.S. Department of Energy’s Princeton Plasma Physics Laboratory (PPPL), has been instrumental for decades in material processing. Its application to TMDs, however, demands unprecedented precision because the overlap between the energy required to remove the top sulfur layer and the energy threshold that damages the molybdenum layer is exceedingly narrow.

Recent computational simulations spearheaded by a team at PPPL have unveiled a chemical strategy to widen this critical energy gap, allowing for cleaner etching of the top sulfur atoms. Key to their approach is the functionalization of the TMD surface with reactive species such as oxygen or fluorine. These atoms form chemical bonds with the sulfur on the surface, modifying the etching dynamics so that the energy barrier for sulfur removal drastically decreases from approximately 30 electron volts to around 10–14 electron volts. This decrease provides a safer operational window in plasma processing, effectively reducing collateral damage to the lower molybdenum layer.

The underlying mechanism involves not brute force but a subtle chemical assist. When a plasma ion interacts with an oxygen-functionalized MoS2 surface, it triggers the formation of sulfur dioxide (SO2) molecules. These gaseous intermediates naturally detach from the surface, making the removal of sulfur energetically easier and more selective. Fluorine coatings operate on a comparable principle, creating sulfur-fluorine compounds that similarly facilitate surface cleaning. This chemical-assisted etching presents a paradigm shift from traditional plasma processing by harnessing molecular chemistry to augment physical processes.

This insight was elucidated by Yury Polyachenko, a Princeton graduate student and PPPL associate, who emphasized that the novelty lies in the material’s chemistry rather than in the brute energetic impact by plasma ions. “We are not directly breaking the bonds,” Polyachenko explained, “but rather forming intermediate products such as sulfur dioxide, which are more easily removed.” This interplay between plasma physics and surface chemistry unlocks new avenues for nanoscale precision in semiconductor manufacturing.

While the research to date establishes a foundational understanding of the mechanism, challenges remain in quantifying and minimizing unintended damage during the plasma etching process. The team cautiously notes the imperative of characterizing the extent of molecular disruption beyond the top atomic layer, which will inform process optimization. Future experiments and simulations aim to rigorously map out the delicate trade-offs to perfect the functionalization-assisted plasma etching technique.

The implications for semiconductor technology are profound. If scalable, this methodology could be applied to a range of TMDs beyond molybdenum disulfide, including variants where molybdenum is replaced by tungsten or sulfur by selenium. Such versatility promises a diversified palette of two-dimensional materials that suit targeted electronic, photonic, or quantum applications. Exploring these analogues will determine the breadth of the technique’s utility across materials science.

These advances further complement ongoing efforts to synthesize and fabricate ultra-thin, high-performance transistors that exceed silicon’s legacy. The integration of plasma physics expertise with cutting-edge computational modeling at PPPL underscores the multi-disciplinary nature of tackling modern device challenges. Moreover, the synergy between experimental precision and theoretical insight catalyzes the innovation cycle driving semiconductor evolution forward.

The research was conducted under the auspices of the U.S. Department of Energy’s Office of Science, utilizing the resources of both the National Energy Research Scientific Computing Center (NERSC) and Princeton’s high-performance computing clusters. This computational power enabled detailed simulations of atomic-scale interactions underlying the selective plasma processing. The results were recently published in the Journal of Physical Chemistry Letters, marking a significant step toward practical implementation.

As the semiconductor industry relentlessly pursues materials and processes to sustain Moore’s Law and beyond, the ability to selectively modify atomically thin layers will be instrumental. This discovery not only provides a path to more reliable and precise etching but also deepens the understanding of plasma-matter interactions at the nanoscale. The marriage of chemical functionalization and plasma technology opens exciting possibilities for the fabrication of next-generation electronics, fueling the era of ultrathin, ultra-efficient devices.

Image Credits: Yury Polyachenko / Princeton Plasma Physics Laboratory (PPPL)

Subject of Research: Transition Metal Dichalcogenides (MoS2), plasma processing, and selective atom removal techniques for semiconductor manufacturing

Article Title: Transition Metal Dichalcogenide MoS2: Oxygen and Fluorine Functionalization for Selective Plasma Processing

News Publication Date: 27-Apr-2026

Web References:
– Princeton Plasma Physics Laboratory: https://www.pppl.gov/
– U.S. Department of Energy: https://www.energy.gov/
– Journal of Physical Chemistry Letters: http://dx.doi.org/10.1021/acs.jpclett.6c00348

References:
Polyachenko, Y. et al. Transition Metal Dichalcogenide MoS2: Oxygen and Fluorine Functionalization for Selective Plasma Processing. Journal of Physical Chemistry Letters, 2026.

Keywords:
Chemistry, Physics, Plasma physics, Computers, Technology, Transition metal dichalcogenides, Molybdenum disulfide, Plasma processing, Semiconductor manufacturing, Nanoscale fabrication, Material functionalization, Surface chemistry

The semiconductor manufacturing landscape traditionally hinges on EUV lithography, a technique instrumental in printing intricate circuits onto silicon substrates, forming the backbone of chips embedded in modern electronics such as smartphones, laptops, and an ever-expanding array of digital devices. EUV lithography depends on complex configurations involving precision mirrors, tin vapor light sources, and painstakingly crafted photomasks. However, available commercial EUV printers demand investments north of $200 million and occupy entire rooms, limiting their availability to only a handful of global corporations.

Responding to these challenges, the Texas engineering team, in collaboration with renowned research partners, embarked on reinventing the EUV lithography process. By reducing the architecture to its fundamental elements, they created a more versatile and modular system. This reimagined EUV printer is not only accessible to a broader range of users but opens new avenues for experimental modifications, accelerating developmental cycles in semiconductor research.

Beyond redesigning the hardware, the researchers merged this compact EUV device with an innovative lithographic technique: volumetric 3D patterning. Conventional EUV lithography processes are constrained to two-dimensional, layer-by-layer assembly of three-dimensional nanostructures, inherently slowing down production due to sequential exposure and alignment requirements. The volumetric 3D approach circumvents this barrier by enabling simultaneous patterning of multiple layers at once, cutting down exposure times from days to mere minutes without compromising nanoscale precision or feature complexity.

Chih-Hao Chang, a mechanical engineering professor and one of the lead authors of the study published in Nano Letters, highlights this transformative leap. He explains that although the pure printing duration might not be lengthy, the traditional repeated processing steps accumulate to prolonged fabrication times. Their volumetric method slashes this bottleneck, empowering researchers to prototype intricate 3D nanostructures rapidly, fostering innovation at an unprecedented pace.

This research represents a vital contribution to the National Science Foundation’s Future of Semiconductors (FuSe2) initiative, an ambitious program aimed at lowering the barriers and costs associated with semiconductor research. By creating practical, compact, and cost-effective EUV lithography systems, the Cockrell team supports the overarching goal of revitalizing semiconductor innovation and expanding participation beyond current industrial giants.

Currently, the team is actively testing novel EUV-sensitive materials developed collaboratively with UT Dallas and Johns Hopkins University, tailored specifically for their compact printer system. These material advances are crucial in optimizing the efficiency and resolution capabilities of the new fabrication platform, fine-tuning it to meet and potentially surpass existing industry standards.

Despite the exceptional promise, the researchers acknowledge that current limitations confine patterning to periodic nanostructures, primarily relevant for applications in photonics and memory chips. However, the long-term vision is ambitious: to engineer faster printers capable of crafting increasingly complex and smaller features, essential for the next generation of semiconductor switches. Such improvements directly translate into chips with enhanced computational power and energy efficiency.

Saurav Mohanty, a recent Ph.D. graduate and the study’s first author, envisages applications reaching far beyond the realm of semiconductors. He articulates that the ability to seamlessly pattern three-dimensional nanostructures could have tremendous impact in diverse fields including nanomedicine—for precise drug delivery systems—quantum computing architectures where nanoscale control is paramount, and the synthesis of novel materials with unique quantum or photonic properties.

This research is not merely an incremental update but a paradigm shift that redefines accessibility and scalability in semiconductor manufacturing. The miniaturization of EUV lithography equipment opens previously inaccessible experimentation avenues and democratizes a critical technology once monopolized by a select few. By enabling rapid and flexible nanofabrication, the Cockrell team’s innovation accelerates progress toward the pursuit of more powerful, efficient, and compact electronics.

As the semiconductor industry faces increasing pressures to sustain Moore’s Law and address the escalating costs of chip manufacturing, combining hardware innovation with advanced patterning strategies represents a holistic approach to overcoming these challenges. The future envisaged by these researchers includes faster prototyping periods, widespread experimental capabilities, and ultimately, the fabrication of semiconductor devices with unprecedented complexity and performance.

In conclusion, the work emerging from the Cockrell School of Engineering underscores the crucial interplay between mechanical engineering, materials science, and applied physics in pushing the boundaries of lithographic technology. The implications of this research resonate throughout the technology sector and beyond, promising to catalyze a wave of advancements not only in electronics but also in medicine, quantum sciences, and advanced material synthesis.

Subject of Research: Development of a compact and cost-effective extreme ultraviolet (EUV) lithography printer for rapid three-dimensional nanopatterning.

Article Title: Three-Dimensional Nanopatterning Using Extreme Ultraviolet Colloidal Talbot Lithography

Web References:

• DOI: 10.1021/acs.nanolett.6c01662
• Future of Semiconductors (FuSe2) – NSF Program

References:
Chang, C.-H., Mohanty, S., et al. “Three-Dimensional Nanopatterning Using Extreme Ultraviolet Colloidal Talbot Lithography,” Nano Letters, DOI: 10.1021/acs.nanolett.6c01662.

Image Credits: The University of Texas at Austin

Keywords

Materials engineering, Nanolithography, Semiconductors, EUV lithography, 3D patterning, Volumetric lithography, Nanomanufacturing, Integrated circuits, Photonics, Quantum computing, Advanced materials, Semiconductor research

As conventional silicon-based Complementary Metal-Oxide-Semiconductor (CMOS) technology approaches the limits of physical scalability, the semiconductor industry has turned its focus to 2D materials. The physical constraints faced by silicon below the sub-nanometer scale have fueled the need for new materials that can effectively continue to enhance electrical performance while maintaining a small footprint. Emerging 2D semiconductors, characterized by their atomic-level thickness yet stable electrical properties, are being considered as the next evolutionary step in semiconductor technology.

However, despite their promise, these 2D semiconductors face one major impediment to commercialization: the integration of high-quality gate stacks. These gate stacks are critical structures that play a key role in controlling the electrostatic behavior of the transistor channel. As such, the performance and stability of a transistor hinge significantly on the quality of its gate stack. The challenge arises when conventional silicon processes are applied to 2D materials, resulting in degraded quality and an increase in interface defects as well as leakage currents.

In this pivotal study, Professor Lee’s team undertook a comprehensive benchmarking process to compare various gate stack integration approaches. They categorized these methods into five distinct groups, identifying their unique characteristics and evaluating them against critical performance metrics such as interface trap density and equivalent oxide thickness. By benchmarking these technologies, the team established a systematic roadmap that becomes essential for the academia and industry as they strive toward the successful commercial application of 2D transistors.

The research also highlighted innovative approaches, particularly the incorporation of ferroelectric materials within gate stacks. This strategy is poised to revolutionize the field by facilitating ultra-low-power logic applications, non-volatile memory solutions, and enhancing the possibilities for in-memory computing. By detailing the technical prerequisites, including Back-End-of-Line (BEOL) compatibility and low-temperature deposition requirements, the research underscores its real-world applicability and potential in advancing next-generation semiconductor devices.

As the technology landscape evolves toward the post-silicon era, leading semiconductor companies, including major brands like Samsung and Intel, have begun to weave 2D transistor technology into their long-term strategies. The transition from exploring 2D semiconductors as a possibility to actively developing them as a core technology signifies a major leap forward for the industry. Companies have recognized the immense potential that 2D transistors hold for enhancing device functionality, making the need for robust gate stack solutions even more urgent.

The implications of the research extend beyond mere theoretical promise. By providing a well-defined roadmap, the study not only sets clear benchmarks for future research but also enables closer collaboration between academic researchers and industry players. This collaboration is critical for overcoming the remaining barriers to commercialization and driving the development of applications that could impact various fields, including artificial intelligence, ultra-low-power mobile technology, and high-density computing systems.

Professor Lee emphasized the importance of high-quality gate stacks for the successful uptake of 2D transistors in commercial applications. The research team’s findings present a foundational blueprint aimed at addressing the pressing challenges faced by the semiconductor industry. Furthermore, they foresee an expansion of their investigative efforts aimed at the practical integration of these technologies into functional devices.

The lead author of this paper, Dr. Yeon Ho Kim, currently serves as a postdoctoral researcher dedicated to exploring contact and gate stack engineering for 2D transistors. As a foremost contributor to this pivotal research, Dr. Kim is anticipated to play a crucial role in the continued progress of 2D semiconductor technologies, bringing both academic and industrial expertise to the field.

The significance of this research is heightened by its support from pivotal organizations such as the Ministry of Science and ICT in South Korea, which recognizes the potential of next-generation semiconductors. This backing underscores a national commitment to advancing technology that could bolster South Korea’s global competitiveness in the semiconductor landscape.

Furthermore, Seoul National University’s College of Engineering has established itself as a frontrunner in semiconductor research. With a commitment to fostering leaders for the global industry, the College aims to not only advance technological frontiers but also nurture the talent necessary to lead these innovations. The research team, under Professor Lee, continues to be at the forefront of global trends, shaping the course of next-generation semiconductor technologies through their innovative approaches and rigorous scientific inquiry.

In summary, the roadmap for gate stack engineering developed by Professor Lee’s team is expected to pave the way for significant advancements in semiconductor technology. By addressing the key challenges associated with the integration of 2D transistors, this research holds promise for overcoming current limitations and ushering in a new era of high-performance, efficient semiconductor devices that can meet the demands of future computing needs.

Subject of Research: Engineering of Gate Stacks for 2D Transistors
Article Title: Gate Stack Engineering of Two-Dimensional Transistors
News Publication Date: 10-Sep-2025
Web References: Nature Electronics
References: DOI: 10.1038/s41928-025-01448-5
Image Credits: © Nature Electronics, originally published in Nature Electronics

Keywords

2D Transistors, Gate Stacks, Semiconductor Technology, CMOS, Ferroelectric Materials, Integrated Devices, Roadmap, Professor Chul-Ho Lee.