As modern semiconductor devices continue to shrink, the quest for thinner channels is driven by the need to enhance transistor control and reduce leakage currents. However, thinning these channels beyond a critical dimension introduces severe drawbacks. Electrons face increased resistance at the interface between the metal electrodes and semiconductor channel, which sharply degrades the electrical performance of the device. This increased contact resistance is a major bottleneck in the design of next-generation ultra-thin transistors, especially as the semiconductor industry pushes the envelope on device speed, energy efficiency, and integration density.

Professor Byoung Hun Lee and his research team have made a breakthrough by reimagining the metal-semiconductor contact interface in tellurium-based transistors. Tellurium is an exotic but promising semiconductor material notable for its high charge carrier mobility, thermal stability at room temperature, and compatibility with low-temperature process fabrication methods. Nevertheless, its narrow band gap necessitates that the transistor channel be crafted with extreme precision, typically less than five nanometers thick, to suppress leakage current and maintain energy efficiency.

The fundamental challenge arises from the physics of the Schottky barrier—a potential energy barrier that electrons must overcome to move between the metal contact and the semiconductor. As the channel thickness decreases, this barrier widens, drastically limiting electron injection and transport. The trick of fabricating ultra-thin channels to minimize leakage inadvertently exacerbates contact resistance, thus throttling the current that flows when the device operates in its on-state. Balancing this trade-off has remained an elusive goal until now.

The innovative solution presented by the POSTECH researchers draws inspiration from established silicon semiconductor fabrication techniques, particularly the Raised Source and Drain (RSD) architecture. By deliberately increasing the semiconductor thickness only at the source and drain regions—areas directly interfacing with the metal contacts—the team succeeded in dramatically reducing electron resistance without compromising the ultra-thin channel that controls the transistor’s switching behavior. This selective thickening acts as a conduit that bypasses the detrimental effects typically seen at metal-semiconductor interfaces.

Experimentation with the RSD technique on tellurium transistors yielded impressive results. The contact resistance plummeted by a factor of 50, from an exceedingly high 97.5 kilo-ohm micrometers to an astonishingly low 1.7 kilo-ohm micrometers. Moreover, when subjected to cryogenic temperatures of minus 196 degrees Celsius, these transistors showcased a spectacular enhancement in on-state current, exhibiting more than a 17-fold increase. These dramatic improvements highlight the efficacy of localized thickness modulation in simultaneously achieving low resistance and high operational performance.

Beyond the immediate electrical advantages, this architecture’s compatibility with scalable manufacturing processes is particularly noteworthy. The team leveraged sputtering, a large-area, low-temperature deposition technique, ensuring that their approach can be integrated into standard semiconductor fabrication lines. This scalability addresses a significant hurdle in transitioning novel materials and architectures from laboratory demonstrations to industrial-scale mass production, heralding new possibilities for commercial adoption.

This advancement holds particular promise for the future of 3D integrated circuits—a technology paradigm that stacks logic and memory vertically to reduce the latency and energy overhead associated with data movement. Such structures require reliable devices that operate efficiently at temperatures below 400°C. The tellurium transistor design with localized thickness control aligns perfectly with these constraints, positioning itself as a core enabling technology for next-generation computing architectures, particularly in AI and high-performance computing applications where data throughput and power efficiency are paramount.

The concept of “localized thickness control” that underpins this innovation represents a form of band engineering that manipulates the fundamental electronic properties of semiconductor regions to optimize device function. By controlling electron energy bands through dimensional modulation, the researchers have redefined the conventional wisdom that thinner channels always equate to higher resistance. This shift in approach provides a versatile platform that can be adapted to a range of two-dimensional (2D) materials and ultra-thin semiconductors beyond tellurium, potentially catalyzing broad advancements in nanoelectronic devices.

Professor Lee emphasizes that their approach not only solves a chronic technical challenge in ultra-thin semiconductor devices but also accelerates the roadmap toward increasingly sophisticated 3D integrated circuits. These circuits are expected to revolutionize computational efficiency and integration density, enabling powerful new classes of electronic systems. The research, supported by national scientific initiatives and published in the prestigious journal ACS Nano, underscores the transformative potential of band engineering in semiconductor research.

This breakthrough illustrates a compelling example of how revisiting and adapting well-established semiconductor techniques—such as the raised source/drain structure—in conjunction with advanced materials like tellurium, can yield unforeseen leaps in performance. The successful marriage of material science innovation, precise nanofabrication, and robust device engineering showcased here highlights a roadmap for overcoming long-standing barriers in semiconductor physics and device technology.

Looking forward, the scalable and energy-efficient tellurium transistors developed by this team position themselves as crucial components in the development of future computing systems that increasingly demand miniaturization without sacrificing reliability or performance. As the demand for lower power consumption and higher processing speeds grows unabated, innovations that blend materials science ingenuity with practical device engineering such as this will be vital in shaping the semiconductor landscape of the coming decades.

Subject of Research: Ultra-thin semiconductor transistor engineering and contact resistance reduction
Article Title: Thickness-Modulated Band Engineering for Low-Resistance Contacts in Ultrathin Tellurium Transistors
News Publication Date: 27-Mar-2026
Web References: 10.1021/acsnano.5c18395
Image Credits: POSTECH

Keywords

Ultra-thin semiconductors, tellurium transistors, contact resistance, raised source/drain structure, band engineering, low-temperature fabrication, 3D integrated circuits, nanoelectronics, sputtering deposition, electron transport, Schottky barrier, high-performance computing

At the heart of optimizing semiconductor performance lies the concept of electronic doping – a process that precisely manipulates the charge carrier concentration in semiconductor materials to enhance their electrical conductivity. Traditional doping techniques often rely on incorporating metal salts or organic additives, which, while effective to an extent, introduce complexities such as chemical residues and stability issues over time. Such methods are typically slow and largely based on iterative trial-and-error protocols, resulting in limited predictability and control over the final device properties. Recognizing these challenges, a research team led by Dr. Pabitra Nayak at the Tata Institute of Fundamental Research in Hyderabad has pioneered a novel doping technique termed in situ regenerative adduct-assisted (IRAA) doping, which promises to revolutionize the electronic tuning of organic semiconductors.

The IRAA doping strategy represents a paradigm shift. Unlike conventional methods that often necessitate external additives or prolonged incubation periods, IRAA facilitates a clean, rapid, and additive-free doping process. During the doping event, a self-regenerating active doping species is spontaneously generated in situ—meaning directly within the material system—ensuring continuous and efficient doping without residual impurities. This innovative approach not only accelerates the doping kinetics but also significantly enhances the uniformity and stability of the doped semiconductor material, addressing key hurdles that have long impeded organic semiconductor applications.

Beyond simply refining an existing process, IRAA fundamentally reengineers the doping framework. Historically, organic semiconductor doping has been constrained by the use of singular dopants which inherently balance between effectiveness, stability, and compatibility compromises. IRAA disrupts this outdated model by introducing a multi-component dopant system, wherein individual molecular constituents can be optimized independently for targeted functionalities. This flexibility transforms doping into a modular and design-driven science, allowing precise tailoring of electronic properties for diverse semiconductor types and device architectures. The implication is profound: doping methodologies can now be predictive and adaptable rather than empirical and rigid.

This breakthrough has profound significance for numerous emerging technologies, particularly flexible electronics and next-generation solar cells. Organic semiconductors and halide perovskite materials have been spotlighted for their exceptional optoelectronic properties, but their broader adoption has been hampered by doping inefficiencies and material instabilities. The IRAA method directly addresses these pain points, laying the groundwork for scalable manufacturing of highly efficient, stable, and flexible devices that leverage organic and perovskite materials.

In the realm of solar energy, where achieving high power conversion efficiency and prolonged operational lifetimes is crucial, IRAA offers a promising pathway. Silicon-based solar cells currently dominate the market with power conversion efficiencies reaching about 27.9%. However, halide perovskite solar cells—initially around 10% efficient a decade ago—have shown remarkable improvement owing to advances in material engineering and doping techniques. Leveraging the IRAA doping strategy, researchers have demonstrated halide perovskite solar cells with an impressive efficiency of 24.6%, bringing these materials tantalizingly close to commercial viability and opening avenues for further enhancement.

This doping methodology’s clean and regenerative nature also means devices can be engineered with greater precision, minimizing defects and enhancing charge transport stability—both critical for practical, long-term applications. Importantly, the IRAA strategy is universally applicable and scalable, making it highly attractive for industrial-scale production of organic semiconductor-based optoelectronics, including flexible displays, sensors, and photovoltaic cells.

The holistic benefits provided by IRAA touch on core technological challenges that have limited the functional potential of organic semiconductors for decades. By effectively eliminating the reliance on fixed dopant chemistries and their associated trade-offs, IRAA empowers researchers to fine-tune semiconductor electronic properties dynamically. This advancement elevates semiconductor doping from a somewhat artisanal craft to an engineering discipline rooted in molecular design and mechanistic understanding.

Additionally, the rapid, additive-free nature of IRAA doping simplifies device fabrication workflows, reducing time and material waste, which is a significant advantage for cost-effective manufacturing. This streamlined approach will likely accelerate the translation of laboratory experimentation into commercially feasible products—a critical step for industries ranging from renewable energy to consumer electronics.

The implications for renewable energy go beyond mere efficiency gains. The ability to engineer semiconductors with enhanced stability and tailor-made electrical properties via IRAA could facilitate the development of next-generation solar cells and energy conversion devices that endure harsh environmental conditions without degradation. Such robust devices are crucial for scaling solar technologies in global markets, especially in regions with limited maintenance infrastructure.

This innovation epitomizes the synergy between fundamental science and applied engineering. It underscores a future where electronic properties are not passively accepted but actively molded through a modular, design-first doping approach. The capacity to customize semiconductor behavior with such fine control will unlock new functionalities, improve device longevity, and catalyze sustainable energy transitions.

Through the pioneering work led by Dr. Nayak and his team, electronic doping has entered a new era—one characterized by regeneration, precision, and sustainable efficiency. The IRAA doping strategy not only challenges existing conventions but sets a new standard for how organic and perovskite semiconductors can be harnessed in the technologies of tomorrow. As research continues to explore and expand IRAA’s potential, the prospect of renewable and flexible electronics achieving widespread adoption becomes ever more tangible. Indeed, this approach may represent a key milestone on the global journey toward cleaner, smarter, and more adaptive semiconductor devices.

Subject of Research: Experimental study on a novel in situ regenerative adduct-assisted p-type doping technique for organic semiconductors

Article Title: In Situ Regenerative Adduct Assisted p-Type Doping of Organic Semiconductor

Web References:
https://advanced.onlinelibrary.wiley.com/doi/10.1002/adma.73351
http://dx.doi.org/10.1002/adma.73351

Image Credits: Photograph by Brijesh K. Patel

Keywords

Organic semiconductors, Electronic doping, IRAA doping, Halide perovskites, Renewable energy, Solar cells, Charge transport, Optoelectronics, Semiconductor stability, Modular doping, Design-driven doping, Photovoltaic efficiency

Recent breakthroughs have turned the spotlight onto metallic two-dimensional (2D) materials, known for their atomically flat surfaces and compatibility with low-temperature processing techniques. These attributes make them ideal candidates for forming contacts with delicate monolayer semiconductors. While such contacts have been successfully implemented in n-type TMD-based transistors, extending this success to p-type devices has proven elusive. The primary roadblock has been WSe₂’s relatively large bandgap, which complicates the realization of high-performance p-type transistors.

Groundbreaking new research now demonstrates a compelling solution—using metallic layered Nb₀.₃W₀.₇Se₂ as a contact material for monolayer and bilayer WSe₂ field-effect transistors (FETs). This multidimensional approach leverages the inherent advantages of layered 2D metals, promoting seamless, low-resistance interfaces with p-type WSe₂ channels. The study reveals that these 2D–2D contacts enable transistor channel lengths down to 100 nm, marking a major stride toward the miniaturization necessary for modern integrated circuits.

A profound achievement of this research lies in the exceptional on-current densities attained. For monolayer WSe₂ transistors utilizing Nb₀.₃W₀.₇Se₂ contacts, on-current densities reach an impressive 358 µA µm⁻¹. Even more striking are the results for bilayer WSe₂ channels, which demonstrate on-current densities soaring to 1.1 mA µm⁻¹. These figures represent considerable enhancements over previous p-type devices, signalling the potential for these materials to unlock new paradigms in low-power, high-efficiency electronics.

The use of Nb₀.₃W₀.₇Se₂ as a contact metal also addresses one of the trickiest technical challenges in transistor fabrication—the formation of a high-quality, low-barrier interface without damaging the sensitive monolayer channel. Conventional metal deposition often necessitates elevated temperatures, which can introduce undesirable defects and strain. In contrast, the layered vdW metallic contacts employed here can be deposited at substantially lower temperatures, preserving the pristine nature of the 2D semiconductor surface and maintaining the integrity of electrical transport pathways.

Another technical milestone achieved in these devices is the integration of scaled gate dielectrics with an effective oxide thickness (EOT) of just 1.3 nm. Such aggressive gate scaling is essential for controlling the electrostatic environment around the transistor channel, thereby suppressing leakage currents and achieving steep subthreshold slopes. The resulting monolayer WSe₂ transistors boast a subthreshold swing as low as 88 mV dec⁻¹, underscoring the finely tuned interface properties and excellent gate control obtained through this innovative design.

This work also highlights the strategic advantage of using metallic Nb₀.₃W₀.₇Se₂ over traditional metal contacts. The unique chemical and electronic properties of this material facilitate a better energy level alignment with p-type WSe₂, reducing Schottky barrier heights, and enabling more efficient hole injection. This aspect is particularly vital in overcoming the intrinsic limitations posed by large bandgap semiconductors that typically suffer from high contact resistance when paired with conventional metals.

In addition to electrical characterization, the study provides compelling insights into the structural compatibility between Nb₀.₃W₀.₇Se₂ and WSe₂ layers. Atomic-level investigations confirm the formation of atomically sharp interfaces devoid of interfacial disorder or contamination that could degrade device performance. The layered nature of both materials ensures lattice matching and eliminates dangling bonds traditionally present in bulk semiconductor–metal interfaces, a common cause of electronic traps and scattering centers.

From an application perspective, the implications of these findings are enormous. The enhanced current densities and reduced contact resistance herald the possibility of fabricating ultrafast, energy-efficient p-type transistors which have long been the bottleneck in complementary metal-oxide-semiconductor (CMOS) technology scaling efforts. Moreover, the low thermal budget of the contact fabrication process paves the way for integrating these devices onto flexible and temperature-sensitive substrates, broadening their utility in wearable electronics and advanced sensor networks.

The approach also opens new avenues for exploring other metallic layered compounds as contact materials across a broader family of 2D semiconductors. By tuning composition and structural parameters, it may be possible to engineer a versatile suite of contact materials optimized for both n-type and p-type conduction across various TMDs. This modularity accelerates the path toward fully 2D-integrated circuits with unprecedented performance metrics and device densities.

Furthermore, this technology is poised to influence the ongoing shift towards heterogeneous material integration, where different 2D layers perform designated functions within a single compact device architecture. By employing all-2D materials for both channel and contacts, researchers can exploit unique electrical, mechanical, and optical properties intrinsic to atomically thin layers while avoiding the complications caused by bulky 3D metal contacts.

The achievement is also a testament to exceptional material synthesis and engineering capabilities. Precisely controlling the stoichiometry and uniformity of Nb₀.₃W₀.₇Se₂ layers is critical for reproducibility and device consistency. Advanced chemical vapor deposition and exfoliation methods have played pivotal roles, showcasing the interplay between materials science and device engineering in realizing functional pico- to nanometer scale electronics.

Looking ahead, the robustness of these 2D–2D contacts under various environmental conditions and operational stresses will be a subject of intense study. Stability against oxidation, thermal cycling, and electrical stress is essential to transition from lab-scale prototypes to commercial device platforms. Early indications suggest excellent mechanical and chemical stability, promising a pathway for durable and scalable technology.

This pioneering research not only bolsters the fundamental understanding of metal–semiconductor interfaces at the atomic scale but also represents a critical step toward fully exploiting the remarkable properties of 2D TMDs in practical applications. By surmounting the longstanding difficulty of creating low-resistance p-type contacts in monolayer WSe₂, the field moves significantly closer to realizing ultrathin, flexible, and highly efficient electronic devices that could revolutionize consumer electronics, computing, and sensing technologies.

In conclusion, the use of metallic layered Nb₀.₃W₀.₇Se₂ contacts in p-type WSe₂ field-effect transistors exemplifies a creative and effective materials engineering strategy to overcome one of the key hurdles in 2D semiconductor technology. The synergistic combination of low contact resistance, high on-current densities, and ultra-thin gate dielectrics positions these devices as frontrunners in next-generation electronic platforms. This advancement marks a seminal development in semiconductor device engineering, with profound implications for the future of nanoelectronics and beyond.

Subject of Research:
Low-resistance contacts in p-type monolayer tungsten diselenide (WSe₂) transistors using metallic layered Nb₀.₃W₀.₇Se₂.

Article Title:
Low-resistance contacts for p-type monolayer tungsten diselenide transistors using metallic layered Nb₀.₃W₀.₇Se₂.

Article References:
Sun, Z., Afzalian, A., Wu, P. et al. Low-resistance contacts for p-type monolayer tungsten diselenide transistors using metallic layered Nb₀.₃W₀.₇Se₂. Nat Electron (2026). https://doi.org/10.1038/s41928-026-01568-6

Image Credits: AI Generated

DOI: https://doi.org/10.1038/s41928-026-01568-6