At the heart of neuromorphic systems lies the vector–matrix multiplication operation, which mimics synaptic transmission and weight modulation in neural networks. While 2D materials such as MoS₂ have demonstrated great promise in creating compact, low-power devices for these fundamental computations, scaling up the hardware to accommodate more complex tasks has proven expensive energetically or technically cumbersome. A persistent roadblock is the trade-off between weight precision and energy consumption: increasing weight precision traditionally requires elevated operating voltages or complex calibration mechanisms that lead to considerable power drain. Addressing this dilemma has been a focal point for researchers aiming to make neuromorphic hardware viable for real-world, energy-conscious applications.

In a transformative new study, researchers have unveiled an innovative in-hardware signal-folding scheme that simultaneously delivers high weight precision and exceptional energy efficiency. Unlike earlier approaches that either focused solely on reducing voltage or on calibration to combat device variability, this dual folding method ingeniously redefines how input signals and device conductances are manipulated before computation. Implemented on a vertical one-transistor–one-resistor (1T1R) MoS₂ crossbar array, this architecture cleverly leverages the unique properties of MoS₂ to achieve both reduced power demand and expanded precision without relying on external compensation schemes.

The key insight underpinning this work is the concept of “signal folding,” which is executed via two complementary schemes: input signal folding and weight conductance folding. Input signal folding compresses the range of input voltages required to activate the device array, effectively decreasing the operational voltage and thus the energy consumed during vector–matrix multiplication. Concurrently, weight conductance folding addresses the variability inherent in device manufacturing and the nonlinear response of memristive elements by combining conductance states so that device-to-device variations cancel each other out, leading to a fine-grained effective weight resolution.

This dual-folding approach fundamentally changes the paradigm of neuromorphic computation by encoding signals into two combinatorial folded signals rather than using the raw, unfolded inputs. By doing so, the researchers make it possible to operate MoS₂-based crossbar arrays at significantly lower voltages while preserving the fidelity of synaptic weights, thereby attaining an optimal balance between power consumption and computational accuracy. The ingenuity of this method lies in its in-hardware implementation, which eschews power-hungry post-processing calibration or compensatory circuit overhead commonly seen in previous works.

Comparative experiments demonstrate the superiority of the signal-folding neuromorphic architecture. When benchmarked against traditional unfolded signal approaches, the folding schemes cut power consumption during vector–matrix multiplication operations by an impressive margin—up to 90%. Despite this dramatic reduction in energy requirements, the system maintains nearly identical accuracy levels, proving that high energy efficiency need not come at the expense of computational precision. This represents a monumental step toward practical neuromorphic hardware that can operate sustainably in edge AI contexts, where power constraints are stringent and performance demands are high.

The hardware setup employs a vertical 1T1R crossbar array structure fabricated with multilayer MoS₂ channels. This vertical configuration optimizes device density and minimizes parasitic capacitances, which further contributes to operational efficiency. Moreover, the transistor-resistor pairing enables fine electrical control of conductance states, an essential aspect for encoding and manipulating weights in neuromorphic computations. The unique electrostatic tunability of MoS₂ devices allows these dual folding methodologies to be implemented seamlessly, positioning this material as a front-runner in the neuromorphic hardware race.

Beyond the technical aspects, this research paves the way for scalable neuromorphic systems capable of supporting complex edge AI applications such as real-time image recognition, natural language processing, and sensor fusion in autonomous systems. Traditional neuromorphic platforms have struggled to reconcile weight precision with energy budgets due to device variability and the analog nature of computations. The signal folding strategy significantly simplifies this challenge, removing the need for prohibitively complex calibration circuitry and thus shrinking system overhead. This reduction in architectural complexity not only conserves energy but can also enhance system reliability and lifespan.

It is worth noting that the signal folding mechanisms introduced here do not rely on any form of external calibration or adaptive compensation—attributes that often introduce latency and additional system complexity. By internalizing error mitigation within the device physics and signal encoding itself, the system remains both agile and efficient. This built-in robustness against device variability affords new opportunities for integration into smaller form factors and energy-constrained environments, potentially catalyzing the adoption of neuromorphic computing in consumer electronics, robotics, and medical devices.

Furthermore, the researchers’ approach presents an exciting blueprint for addressing fundamental limitations seen in other emerging memory technologies. Device-to-device variations and analog noise in nanoscale memristive systems have long constrained weight precision, limiting the practical deployment of vector–matrix multiplication arrays for neural networks. By harnessing the inherent properties of MoS₂ through signal folding, this approach indicates a promising direction for mitigating these limitations while maintaining low operational voltage regimes.

The folding schemes also offer conceptual innovations that could find applications beyond neuromorphic computing. Signal folding—representing input signals and conductances with combinatorial encodings—could inspire novel low-power architectures in other domains requiring high precision and minimal energy footprints. This could include sensors arrays, analog signal processors, or quantum computing interfaces, where similar challenges of balancing signal fidelity with operational energy exist.

Looking ahead, the potential scalability of this technology is especially compelling. The vertical 1T1R MoS₂ crossbar geometry is conducive to high-density integration, enabling vast synaptic connectivity that mimics biological neural networks more faithfully than ever before. Coupled with these signal folding techniques, future neuromorphic chips could achieve multi-level weight precision at ultra-low power, unlocking capabilities in federated learning and on-device AI that were previously unattainable due to energy and accuracy trade-offs.

In conclusion, this groundbreaking work marks a definitive advance in neuromorphic hardware design by overcoming a critical energy-precision bottleneck through inventive use of signal folding within a 2D material platform. By enabling vector–matrix multiplication at significantly lower voltages and cancelling device variability innately, the researchers have unlocked a pathway toward energy-efficient, high-precision neuromorphic systems suitable for edge computing scenarios. The implications for AI hardware ecosystems are profound, promising faster, smarter, and more power-aware computing for a plethora of real-world applications.

As two-dimensional materials like MoS₂ continue to mature in their fabrication and integration, and as computational architectures evolve to fully harness these physical properties, neuromorphic hardware leveraging signal folding could soon shift from laboratory prototypes to the core of next-generation AI devices globally. This study not only exemplifies the synergistic power of materials science and circuit design but also sets the stage for truly sustainable, scalable neuromorphic platforms that bring us closer to the dream of brain-like computation at the edge.

Subject of Research: Neuromorphic hardware using two-dimensional MoS₂ materials, focusing on energy-efficient vector–matrix multiplication through signal folding techniques.

Article Title: Signal-folding-based neuromorphic hardware for energy-efficient computing

Article References:
Tong, L., Xu, L., Huang, X. et al. Signal-folding-based neuromorphic hardware for energy-efficient computing. Nat Electron (2026). https://doi.org/10.1038/s41928-026-01626-z

Image Credits: AI Generated

DOI: https://doi.org/10.1038/s41928-026-01626-z

The heart of this advancement lies in the design of the neuromorphic processor, which integrates on-chip learning mechanisms using beyond-CMOS components, enabling the system to adjust its synaptic weights in situ. Traditional CMOS-based implementations, constrained by scalability and energy inefficiency, have long challenged the realization of compact and efficient neuromorphic systems. This new approach circumvents these barriers by embracing emerging nanoscale devices that can emulate synaptic plasticity with remarkable precision and low power consumption. The result is a processor that not only computes but also learns continuously, analogous to biological neural networks.

Key to this neuromorphic solution is the innovative hardware architecture that combines standard digital circuits with emerging analog elements representing synaptic functionalities. Unlike previous attempts that relied heavily on software emulation or fixed hardware weights, this processor dynamically updates its synapses through on-device learning algorithms implemented at the circuit level. The learning mechanism is based on spike-timing dependent plasticity (STDP), where the timing of input and output spikes determines synaptic strength modifications. Such integration of learning rules into hardware circuits ensures real-time adaptation and significantly reduces the energy overhead typically associated with training.

The integration of beyond-CMOS devices, such as memristors or phase-change memory elements, lies at the core of the processor’s synaptic arrays. These devices intrinsically possess nonvolatile resistive states, which correspond to synaptic weights, allowing the system to maintain learned information without continuous power consumption. The array structure depicted in the accompanying figure demonstrates how these devices are organized into crossbar arrays, enabling massive parallelism in synaptic operations. Each synapse can be individually programmed and updated, supporting high-resolution weight modulation and dense connectivity reminiscent of biological neural networks.

Another remarkable aspect of the design is the processor’s scalability and compatibility with existing semiconductor manufacturing processes. By carefully selecting materials and device configurations that interface seamlessly with state-of-the-art CMOS foundries, the team ensures that this neuromorphic platform can be produced using current fabrication infrastructure. This hybrid integration strategy avoids costly overhauls while enabling incremental incorporation of beyond-CMOS devices into mainstream processors, fostering a smoother transition toward more intelligent hardware systems.

The on-chip learning circuits utilize novel compact neuron models implemented with mixed-signal techniques, balancing analog and digital domains. These neurons generate output spikes based on accumulated input currents, encapsulating essential neuronal behaviors such as refractory periods and firing thresholds. This biologically inspired modeling contributes to the processor’s energy efficiency by minimizing unnecessary switching activities and exploiting event-driven computing principles. Event-driven processing ensures that computations occur only when relevant signals arise, drastically lowering power consumption relative to clock-driven architectures.

Importantly, the processor’s learning framework supports supervised and unsupervised paradigms, broadening its applicability to diverse machine learning tasks. By embedding learning rules directly at the synaptic device level, the system can autonomously adjust to changing signal patterns, enabling robust performance in noisy and variable environments. This capacity for lifelong learning and adaptation is essential for autonomous agents operating in real-time and unpredictable scenarios, such as drones, robotics, or edge AI applications.

The authors also address the challenges of device variability and endurance which arise with emerging memory technologies. To combat these obstacles, error-correcting circuits and redundancy strategies are integrated at various design layers, ensuring reliable operation over extended usage periods. Such architectural foresight is crucial for practical deployment, given that beyond-CMOS devices often exhibit stochastic behaviors and limited cycling durability compared to conventional transistors. The combined hardware-software co-design approach effectively mitigates these limitations while preserving the processor’s learning agility.

Equally notable is the processor’s impressive energy efficiency, achieved through the interplay of event-driven computation, in-memory processing, and neuromorphic plasticity. Conventional von Neumann architectures suffer enormous energy penalties due to separate memory and processing units, dubbed the memory wall problem. By embedding computational functions within memory arrays and performing synaptic updates locally, this neuromorphic design drastically reduces data movement and thereby power consumption. Performance benchmarks indicate that the processor sustains competitive accuracy on standard neural network tasks while consuming orders of magnitude less energy than traditional digital chips.

The implications of this research extend well beyond incremental improvements in AI hardware. By providing a scalable platform capable of on-chip learning with beyond-CMOS technology, the team paves the way for truly autonomous and energy-frugal smart devices. Applications range from continuous health monitoring wearables and adaptive sensor networks to intelligent prosthetics and beyond, where always-on learning and responsiveness are imperative. As neuromorphic processors evolve, they promise to deliver cognitive capabilities once exclusive to biological brains, directly embedded within physical silicon.

Moreover, this advancement ushers in new design paradigms for computing systems by bridging the gap between device physics and high-level learning algorithms. The processor embodies a holistic integration of hardware and software principles, showcasing how neuromorphic engineering can transform memory devices into computational units that learn and adapt. This synergy could redefine the approach to building AI systems, shifting from power-hungry, centralized models toward distributed, brain-inspired architectures optimized for edge deployment.

Future avenues inspired by this work may include the exploration of novel materials and three-dimensional integration schemes to further enhance synaptic density and connectivity. Such efforts could lead to processors with neuron counts approaching those of small mammalian brains while remaining compact and energy efficient. Additionally, expanding the processor’s learning protocols to more complex and hierarchical schemes might unlock advanced cognitive functionalities akin to those seen in higher-level biological systems.

Ethical and societal impacts are also an intrinsic consideration when advancing neuromorphic technology toward widespread adoption. On-chip learning systems that operate autonomously raise important questions about transparency, control, and security. Ensuring that these intelligent processors act reliably and predictably, especially in safety-critical environments, will be essential. Equally, their potential to enable ubiquitous AI embedded in everyday objects necessitates responsible stewardship to balance innovation with privacy and ethical standards.

Ultimately, the neuromorphic processor presented by Greatorex and colleagues marks a transformative milestone in the journey toward hardware-based artificial intelligence. By harmonizing emerging beyond-CMOS memory devices with biologically inspired circuits and learning frameworks, the research delivers a scalable, efficient, and adaptive computing platform. This work not only accelerates the realization of brain-like machines but also redefines the future landscape of AI hardware, promising systems that learn as naturally and continuously as living brains.

Subject of Research: Neuromorphic processor with on-chip learning integrating beyond-CMOS devices

Article Title: A neuromorphic processor with on-chip learning for beyond-CMOS device integration

Article References:
Greatorex, H., Richter, O., Mastella, M. et al. A neuromorphic processor with on-chip learning for beyond-CMOS device integration. Nat Commun 16, 6424 (2025). https://doi.org/10.1038/s41467-025-61576-6

Image Credits: AI Generated