The scale of the challenge is rooted in how conventional flash works. Since the floating-gate transistor was proposed by Dawon Kahng and Simon Sze in 1967 and the block-erase concept was introduced by Fujio Masuoka in 1984, silicon flash has relied on pushing charge through insulating barriers using strong electric fields, either through Fowler–Nordheim tunneling or hot-carrier injection. Faster writing generally demands stronger fields, which in turn increase energy dissipation, promote defect generation in the tunneling dielectric, and accelerate long-term reliability degradation. Speed, power, and endurance are therefore locked together in a trade-off that no amount of geometric shrinking has fully broken. Even three-dimensional NAND, which has grown from 32 stacked layers in 2012 to more than 200 today, changes the architecture but not the underlying charge-writing physics.

Two-dimensional materials—graphene, transition-metal dichalcogenides such as molybdenum disulfide and tungsten disulfide, and insulating hexagonal boron nitride—offer a different starting point. These crystals are one to a few atoms thick, their surfaces carry no dangling bonds, and they can be stacked into van der Waals heterostructures without the lattice-matching constraints of conventional epitaxy. The result is atomically sharp interfaces with far fewer defects than silicon-dielectric systems. According to the review, this allows memory designers to control the full lifecycle of stored charge—injection, transport, trapping, confinement, and release—through band alignment and interface engineering rather than brute-force electric fields, a strategy the authors call interface-controlled charge programming.

The performance gains reported across the literature are striking. Where silicon flash typically writes in microseconds to milliseconds at 10 to 20 volts or more, 2D devices have demonstrated nanosecond and even subnanosecond programming at a few volts, with energy per operation dropping from picojoule–nanojoule levels to the femtojoule–picojoule range. Endurance in several 2D systems has exceeded one million write–erase cycles, compared with roughly one thousand to one hundred thousand for conventional devices, thanks to reduced electrical stress at dangling-bond-free interfaces. Retention remains the weakest metric: most 2D devices have been evaluated over thousands to tens of thousands of seconds rather than the ten-year industrial standard of commercial flash, and the review stresses that rigorous benchmarking under standard conditions is still lacking.

Several landmark demonstrations illustrate how interface engineering delivers speed. One device stacked molybdenum disulfide, boron nitride, and few-layer graphene, using a phase-engineered edge contact in which a metallic lithiated molybdenum disulfide phase meets the semiconducting phase laterally, avoiding the deposition-induced disorder and Fermi-level pinning caused by conventional top metal contacts. That architecture achieved programming in about 10 nanoseconds. A separate device based on indium selenide, boron nitride, and multilayer graphene reached programming and erasing in 21 nanoseconds by exploiting atomically clean van der Waals interfaces confirmed by electron microscopy. Most dramatically, a graphene-channel device exploited the way atomically thin channels concentrate lateral electric fields near the drain, boosting hot-carrier injection and achieving programming in roughly 400 picoseconds at about 5 volts—while still retaining charge for more than 10,000 seconds and surviving more than 5.5 million cycles.

Low-power operation follows a parallel logic. One heterostructure using molybdenum disulfide, boron nitride, graphdiyne, and graphene achieved write pulses of only 30 millivolts and erase pulses of −0.5 volt by aligning bands favorably in a semi-floating-gate architecture. Another device inserted a threshold-switching layer of graphdiyne oxide between the control gate and floating gate; during a write pulse the layer briefly enters a low-resistance state, allowing direct charge injection, then returns to a high-resistance state that suppresses back leakage. That device programmed and erased with a 20-nanosecond pulse at 2 volts with an energy cost as low as 10 femtojoules per operation. Gate-tunable contacts offer a third route: in a tungsten disulfide–boron nitride heterostructure, the contact could be switched between a quasi-ohmic state for efficient injection and a Schottky-dominated state that suppresses programming current to approximately 10⁻¹¹ amperes.

Retention depends on keeping charge trapped once it is written. Molybdenum disulfide devices using lead iodide as the trapping layer exploit that material’s naturally abundant, energetically deep iodine-vacancy traps; the devices experimentally demonstrated retention beyond 1.2 × 10⁴ seconds, from which the original study extrapolated a charge loss of approximately 16 percent after 10 years. Another approach embedded cadmium selenide cores shelled in cadmium sulfide with electrochemically inert surface ligands into a monolayer molybdenum disulfide charge-trap memory; retention measurements over 5 × 10⁴ seconds, when extrapolated, suggested that approximately 96.5 percent of the stored charge could be retained after 10 years. Both projections rest on extrapolation from short laboratory tests, a caveat the review makes explicit.

Beyond storing bits, 2D flash is emerging as a computing platform. Because a flash cell’s conductance can be programmed to many levels, arrays of cells can perform the vector–matrix multiplications that dominate neural-network workloads directly in memory, sidestepping the costly shuttling of data between processor and memory in conventional von Neumann architectures. One molybdenum disulfide floating-gate device combining barrier-free bismuth contacts with a dual-pulse editing scheme demonstrated 2,249 distinguishable conductance states—more than 11 bits of analog precision, retained even at 85 degrees Celsius—while programming in roughly 230 nanoseconds, with retention beyond 10⁴ seconds and endurance above 10⁵ cycles. Another device with a coplanar control-gate geometry reached 256 clearly distinguishable states, equivalent to 8-bit precision, and a small 9 × 2 array built from such cells performed image convolution and vector–matrix multiplication, maintaining near-ideal inference accuracy on an ImageNet recognition task even under 8-bit quantization.

The most ambitious demonstrations merge sensing, memory, and computation in single devices. A reconfigurable split-floating-gate architecture uses spatially separated dual gates to reconfigure the same channel into p–n, n–p, n–n, and p–p homojunctions, allowing the same cell to act as a self-powered photodetector that stores its own readings, an analog memory cell supporting 63 stable states with endurance over one million cycles, or a nonlinear activation element exhibiting ReLU-like and Sigmoid-like responses. At the array scale, researchers fabricated a 1,024-cell 2D flash array with 98.4 percent yield and roughly 20-nanosecond programming using an ultraclean memory-stack-first van der Waals integration process, and built an 8 × 16 analogue content-addressable memory from molybdenum disulfide cells with semimetallic antimony contacts; that system was estimated to achieve energy consumption below 0.1 femtojoule per search per cell and an ultralow latency of 36 picoseconds, representing a 13.8-fold improvement in energy efficiency and a 568-fold reduction in latency compared with conventional SRAM-based content-addressable memory.

Integration with existing silicon infrastructure is the final hurdle, and early results are encouraging. Using an atom-to-chip strategy, one team monolithically integrated 2D flash modules on the back-end metal layers of CMOS circuitry, achieving a chip yield of 94.34 percent, an operation speed of about 20 nanoseconds, and an energy consumption as low as 0.644 picojoules per bit, with FPGA-based testing confirming instruction-driven operation, 32-bit parallel programming, and high programming accuracy across 32 word lines. The review’s authors caution, however, that most record performances come from single devices or small arrays, and that wafer-scale synthesis, cross-wafer uniformity, array-level crosstalk and disturbance, and thermal-budget compatibility with back-end-of-line manufacturing remain unsolved. Whether 2D flash becomes a mainstream memory or a niche computing accelerator will depend not on any single record, but on whether the interface-controlled design philosophy can be carried coherently from atomically clean laboratory stacks to manufacturable, system-ready hardware.

Subject of Research: Two-dimensional materials and interface engineering for next-generation flash memory and in-memory computing

Article Title: Two‐Dimensional Flash Memory: Materials, Interfaces, and Storage–Computing Convergence

Article References: Wang, Z., Meng, F., Meng, F., Huo, S., Xu, J., Wang, Y., Ma, Y., Xie, Y., Hu, X., Pan, C., & Wu, E. (2026). Two‐Dimensional Flash Memory: Materials, Interfaces, and Storage–Computing Convergence. Advanced Science, 13(59), Article e78009. https://doi.org/10.1002/advs.78009

Image Credits: AI Generated

DOI: 10.1002/advs.78009

Keywords: flash memory, two-dimensional materials, van der Waals heterostructures, in-memory computing, molybdenum disulfide, graphene, hexagonal boron nitride, hot-carrier injection, charge trapping, neuromorphic computing, CMOS integration, nanoelectronics