Compact non-volatile photonic chip design performs matrix multiplication across 40 nm bandwidth

Denise Maddox — Sat, 24 Oct 2026 19:35:58 +0000

Researchers have designed an ultra-compact photonic engine that performs matrix-vector multiplication, the core mathematical operation underlying artificial neural networks, using light rather than electrons. The proposed device, described in Scientific Reports by Ali Atri and Abbas Zarifkar, occupies just 185 by 21 micrometers and relies on mode division multiplexing, routing information in two transverse magnetic modes of the same waveguide. Because the design is validated through electro-thermal simulations rather than a fabricated chip, its reported performance figures are model-based estimates of what the architecture could achieve.

The architecture combines three functional blocks. A multimode interferometer splits input power with a simulated insertion loss of 0.98 dB, while a directional-coupler demultiplexer separates the fundamental and first-order modes with roughly 10 dB of crosstalk suppression and 0.87 dB insertion loss. At its heart sits a weighting core of four independently programmable paths, each containing five phase-change cells made of Ge2Sb2Se4Te1, known as GSST, for twenty cells in total.

By electrically switching each cell between amorphous and crystalline states, the device can be reconfigured into 1,296 distinct matrix settings, with simulated extinction ratios of 11.29 dB for the TM0 mode and 17.3 dB for the TM1 mode. The switching behavior predicted by the simulations is notably fast and reversible. A pulse of 5 volts for 33 nanoseconds crystallizes a GSST cell, while a stronger 12-volt pulse lasting just 5 nanoseconds melts the material, which then quenches rapidly back into the amorphous state.

Because GSST holds its state without continuous power, the cells are non-volatile, meaning the matrix weights persist between operations and static power consumption drops to zero. The complete multiplication engine shows a simulated total insertion loss of 2.76 dB for TM0 and 3.64 dB for TM1 at the telecom wavelength of 1550 nanometers. A further strength of the design is its broadband tolerance: the device maintains functionality across a 40-nanometer window from 1540 to 1580 nanometers.

The authors position the work as a scalable pathway toward energy-efficient, mode-multiplexed photonic computing, in which electronic processors are increasingly strained by the speed and power demands of large neural networks.

Subject of Research: A compact non-volatile photonic matrix-vector multiplication engine design for neuromorphic computing

Article Title: Non-volatile, compact, and broadband multimode matrix vector multiplication for photonic neuromorphic computing

Article References: Atri, A., & Zarifkar, A. (2026). Non-volatile, compact, and broadband multimode matrix vector multiplication for photonic neuromorphic computing. Scientific Reports. https://doi.org/10.1038/s41598-026-77326-7

Image Credits: AI Generated

DOI: 10.1038/s41598-026-77326-7

Keywords: photonic computing, neuromorphic computing, matrix-vector multiplication, mode division multiplexing, phase-change materials, GSST, non-volatile memory, silicon photonics, optical neural networks, electro-thermal simulation, Non-volatile, compact

reconfigurable photonic devices using phase-change materials – Science

Compact non-volatile photonic chip design performs matrix multiplication across 40 nm bandwidth