The experiment, led by Ziqian Li and Eesh Gupta, who contributed equally, together with senior author David I. Schuster, showcases a device in which seven distinct memory modes can be individually addressed through a single transmon qubit acting as a classical control intermediary. Crucially, the memory modes are not raw qubits exposed to the noise of the processing layer. Instead, they live inside a multimode storage cavity, and a carefully engineered buffer layer sits between the processor and the cavity, isolating the fragile stored quantum states from the nonlinear elements that make computation possible but also make errors likely.

The need for such a device is easy to appreciate when one considers how modern superconducting quantum processors actually operate. In today’s machines, every physical qubit is tied to its own dedicated control lines, readout resonators and filters. A logical qubit protected by a surface code can demand dozens of physical qubits, each with its own coaxial cable running down into the dilution refrigerator. The wiring burden grows so quickly that scaling to useful machines has become as much a problem of engineering and cryogenics as of quantum physics. A random access memory flips this picture: if quantum information can be parked in high-coherence storage and retrieved on demand through a small number of shared control channels, the number of lines required per logical qubit falls dramatically, and the logic and storage subsystems can each be optimised separately.

The conceptual foundations for quantum random access memory stretch back to 2008, when Giovannetti, Lloyd and Maccone formalised the idea of a structure that could be queried in superposition, an operation at the heart of several quantum algorithms with proven exponential advantages. Practical implementations, however, have lagged far behind their classical counterparts. Demonstration efforts in other platforms, including a 105-mode random access memory realised with atomic ensembles in 2019, showed that the principle could be realised, but superconducting processors, the leading candidate for fault-tolerant quantum computation, notably lacked an equivalent. Architectural proposals from computer scientists, including work by Baker, Schuster and Chong on memory-equipped quantum architectures, argued that the power of random access could reshape how error-corrected machines are organised, but the hardware to realise such a vision did not yet exist.

The new device closes that gap with an elegant layered design. At its heart is a multimode microwave storage cavity, a single physical object that supports many electromagnetic modes at distinct frequencies, each capable of holding a quantum state for a long time. Seamless cavities of this kind have previously achieved photon lifetimes measured in tens or even hundreds of milliseconds, far exceeding the coherence of planar transmon qubits. A single transmon, the workhorse qubit of the superconducting world, provides the address mechanism: by tuning the transmon into resonance with a selected cavity mode, the experimenters can swap a quantum state into or out of that mode while leaving the others untouched.

The crucial innovation is the cascaded architecture with its buffer layer. Directly coupling a transmon to a multimode cavity creates a problem: the strong nonlinearity of the qubit, which enables control, also pushes unwanted photons and residual excitations back into the memory, degrading the stored states through induced dephasing and other many-body effects. The team solved this by inserting an intermediate buffer mode between the processor and the storage cavity, cascading the interactions so that the storage modes are only weakly, virtually engaged during operation. The single transmon then classically addresses the seven memory modes through this buffer, addressing them one at a time while the full stack remains protected from processor nonlinearities.

The performance figures reported are striking for a first demonstration. Arbitrary random access across the eight-bit device, meaning the ability to write to or read from any chosen memory mode on demand, was achieved with an average infidelity of less than 1.5 percent per mode. The researchers did not stop at headline numbers: they characterised the dominant error processes in detail, showing that residual many-body interactions within the multimode cavity set the present error budget. This kind of honest error accounting matters enormously for the path forward, because it tells engineers exactly which physical mechanisms must be suppressed as the architecture is scaled to more modes and longer storage times.

Beyond mere storage, the architecture supports operations performed transversally within the memory module, meaning operations that act across the encoded information without spreading errors from one component to its neighbours, a key requirement for fault tolerance. Combined with the drastic reduction in control lines per logical qubit, this positions the cascaded random access memory as a candidate unit cell for fault-tolerant quantum architectures. In such a scheme, the memory module would hold many logical qubits in long-lived cavity modes, a modest number of transmons would provide address and control, and dedicated processors would operate on retrieved states, each subsystem optimised on its own terms. The authors describe the result as enabling resource-efficient control of logical qubits, separating the problems of high-speed logic and long-duration storage that currently fight for the same physical qubits.

The work also resonates with a broader trend in the field towards bosonic and multimode approaches to quantum information. Error-corrected logical qubits encoded in oscillator states, dual-rail cavity qubits with erasure detection, and high-quality-factor niobium and coaxial cavities have all advanced rapidly in recent years, with several experiments now reaching or exceeding the break-even point for quantum error correction. What has been missing is a way to organise many such high-performance memories into an addressable, switchable whole. The cascaded random access memory provides exactly that missing layer of organisation, and it does so using components, transmons, cavities and parametric couplers, that are already compatible with existing superconducting processor fabrication.

There remain, of course, substantial challenges between this eight-bit demonstration and the megabyte-scale ambitions of quantum computing. Error rates must fall further, storage times must lengthen relative to operation times, and the many-body interaction effects that dominate the current error budget must be engineered away or incorporated into error models. The researchers have made their data and simulation codes openly available through figshare, an invitation for the community to probe, reproduce and extend the results. Yet the conceptual milestone is unambiguous. Classical computing took its decisive step towards scalability when memory was separated from logic and made randomly accessible. Quantum computing has now taken an analogous step, demonstrating that a single control qubit can reach into a protected reservoir of quantum states and retrieve any one of them on demand. If the approach scales as its designers hope, the random access quantum memory may come to be seen as the moment quantum hardware began to acquire the architectural maturity that classical machines have enjoyed for decades.

Subject of Research: Demonstration of an eight-bit cascaded random access quantum memory using superconducting circuits, transmons and multimode storage cavities for scalable fault-tolerant quantum computing.

Article Title: A cascaded random access quantum memory

Article References: Li, Z., Gupta, E., Zhao, F., Banerjee, R., Lu, Y., Roy, T., Oriani, A., Vrajitoarea, A., Chakram, S., & Schuster, D. I. (2026). A cascaded random access quantum memory. Nature Physics. https://doi.org/10.1038/s41567-026-03418-w

Image Credits: AI Generated

DOI: 10.1038/s41567-026-03418-w

Keywords: quantum memory, random access memory, superconducting circuits, transmon qubit, multimode cavity, quantum computing, fault tolerance, quantum error correction, circuit quantum electrodynamics, logical qubits, cascaded architecture, quantum architecture

One of the pivotal insights driving progress is the natural synergy between semiconductor spin qubit technologies and the well-established infrastructure of complementary metal-oxide-semiconductor (CMOS) industry. Unlike other qubit architectures, semiconductor spin qubits inherently align with CMOS fabrication methodologies, an inheritance of the silicon-based electron spin’s compatibility with industrial processes honed over decades. This congruence grants a unique opportunity to leverage the relentless advancements in CMOS scaling, precision manufacturing, and large-scale integration, establishing a pathway toward economically viable, fault-tolerant quantum processors on a scale that was previously unthinkable.

However, while this compatibility offers great promise, it is not without significant nuances. The operational paradigms of spin qubits diverge in important ways from the standard CMOS device operations. For instance, the quantum manipulation of spins relies on delicate control over quantum coherence and entanglement, demanding materials, device architectures, and control electronics tailored to nurture and preserve fragile quantum states. This contrasts with classical CMOS devices designed primarily for digital logic and charge-based operation, necessitating adaptations in materials and fabrication processes to reconcile these differing requirements.

The integration challenge extends further when considering the co-location of qubit arrays with their associated classical control elements. Minimizing heat dissipation is critical because quantum coherence is highly sensitive to thermal noise. Consequently, the cryogenic operating conditions required for spin qubits necessitate inventive low-power classical control circuits capable of operating reliably at millikelvin temperatures or interfacing effectively with room-temperature electronics. This co-integration must be achieved without sacrificing scalability or manufacturability, posing a formidable systems-engineering puzzle that relates directly to the principles of very-large-scale integration (VLSI) perfected by the CMOS domain.

One of the striking contrasts between semiconductor spin qubits and other qubit varieties is how spin systems were conceived with CMOS compatibility in mind from their inception. Spin qubits benefit from silicon’s abundance, excellent isolation properties, and a mature industrial ecosystem, setting them apart from alternative qubits that require substantial retrofitting to meet CMOS process requirements. This foresight facilitates a streamlined transition from research prototypes to foundry-compatible devices, potentially accelerating the development cycle and commercial readiness far beyond competing quantum architectures.

To realize these ambitions, concerted collaborative efforts are imperative. Bridging the knowledge and process gaps between spin-qubit researchers and CMOS industry experts will unlock synergies that neither field could achieve independently. By melding deep quantum physics understanding with the practical manufacturing experience of silicon foundries, these partnerships pave the way for fault-tolerant quantum processors that blend exquisite quantum control with the reliability and economies of scale intrinsic to CMOS fabrication.

Addressing device variability represents another critical hurdle on the path to utility-scale quantum computers. Variability in nanoscale semiconductor structures can induce fluctuations in qubit performance, undermining the overall fidelity required for error correction protocols. The CMOS industry’s rich history in managing transistor variability through statistical process control and adaptive circuit design provides a treasure trove of strategies to tame these fluctuations within spin qubit arrays. Translating these techniques into the quantum realm demands significant innovation but offers a proven framework from which to draw inspiration.

Moreover, the control electronics for spin qubits must evolve beyond traditional CMOS transistor circuits. Quantum gate operations require precise timing, amplitude modulation, and phase control of microwave and radiofrequency signals to manipulate spin states coherently. Developing compact, cryo-compatible, low-noise electronics integrated directly on the qubit chip or its immediate vicinity presents technical challenges intertwined with CMOS integration strategies. Progress in this area will be a linchpin for scalable, economically viable quantum computing platforms.

Material considerations also play a pivotal role in the CMOS compatibility of spin qubits. The purity, isotopic composition, and defect profiles of silicon substrates can dramatically influence qubit coherence times, directly impacting performance. Advanced CMOS wafers and processes must be tailored or supplemented to maintain or enhance these material qualities essential to spin qubit fidelity, sometimes challenging standard commercial silicon processing norms.

Another dimension of complexity involves the system architecture and error correction demands inherent in fault-tolerant quantum computing. Semiconductor spin qubits must be arranged into two-dimensional lattice structures and controlled with intricate microwave pulse sequences to implement error-correcting codes robustly. Integrating these systems into CMOS-compatible hardware platforms requires careful attention to wiring density, crosstalk minimization, and thermal management strategies that exploit the scalability features of CMOS while addressing quantum-specific constraints.

The path forward is illuminated by the increasing convergence between the quantum device research community and the semiconductor industry, where innovations in silicon photonics, cryoelectronics, and advanced packaging techniques offer promising routes to overcome integration bottlenecks. These technologies can support efficient control and readout schemes that dovetail with CMOS processes, driving down the complexity and cost of quantum processor platforms.

In addition to technical challenges, the economic importance of scaling quantum processors cannot be overstated. Crossing the utility scale threshold means that quantum systems provide computational advantages that justify their production, operation, and maintenance costs. CMOS-compatible semiconductor spin qubits stand as a leading contender to achieve this milestone first, thanks to their scalability potential, material advantages, and integration pathways.

The prospect of industrial-scale production of fault-tolerant quantum processors becomes tangible as semiconductor spin qubits mature within the CMOS ecosystem. This alignment not only opens avenues for rapid fabrication and deployment but also for quality assurance, standardization, and incorporation into existing computing infrastructures. Such integration could usher quantum computing from laboratories to data centers, catalyzing transformative advances in fields ranging from cryptography to pharmaceuticals.

In conclusion, semiconductor spin qubits offer a uniquely CMOS-friendly foundation on which to construct the next generation of quantum processors. Addressing the multifaceted challenges of operation, materials, system design, and co-integration through a symbiotic relationship between quantum physicists and CMOS engineers promises to accelerate the realization of utility-scale, fault-tolerant quantum computing. This convergence not only enhances technical feasibility but also positions quantum computing at the cusp of widespread industrial adoption, heralding a new era of computational capabilities grounded in silicon’s enduring legacy.

Subject of Research: Semiconductor spin qubits and their compatibility with complementary metal-oxide-semiconductor (CMOS) technologies for scale-up toward utility-scale quantum computing.

Article Title: CMOS compatibility of semiconductor spin qubits.

Article References:
Dumoulin Stuyck, N., Saraiva, A., Gilbert, W. et al. CMOS compatibility of semiconductor spin qubits. Nat Rev Electr Eng (2026). https://doi.org/10.1038/s44287-026-00283-w

Image Credits: AI Generated