The central innovation lies in the transistor itself. Molybdenum disulfide, a two-dimensional semiconducting material just a few atoms thick, forms the conducting channel of the device. Because the material is so thin, its electronic properties can be controlled with exceptional precision by electric fields applied from above and below. The researchers exploited this by constructing a dual-gate architecture: one gate tunes the channel’s conductivity in the conventional manner, while the second gate is made of a ferroelectric material whose polarization state can be flipped and retained without continuous power. This ferroelectric layer effectively gives the transistor a form of nonvolatile memory, allowing it to remember its configuration even when the device is switched off.

That combination of tunability and memory is what enables the reconfigurability at the heart of the new architecture. By adjusting the voltages applied to the two gates, the researchers can steer a single transistor between fundamentally different modes of operation. In one configuration, the device behaves as a spiking neuron, integrating incoming electrical pulses and firing an output spike only when the accumulated input crosses a threshold, mirroring the leaky integrate-and-fire dynamics of biological neurons. In another configuration, the same physical device operates as a logic transistor within a standard digital circuit, performing the deterministic switching operations on which conventional computing relies. No rewiring, no fabrication changes, and no additional components are needed to move between these modes; only gate voltages change.

Spiking neural networks represent a fundamentally different approach to computation compared with the artificial neural networks that dominate today’s AI landscape. Rather than exchanging continuous numerical values, spiking networks communicate through discrete electrical pulses, or spikes, much like the neurons in a biological brain. Information is encoded in the timing and frequency of these spikes, which allows the network to remain largely idle between events and consume power only when meaningful signals arrive. This event-driven behavior is the reason the human brain, running on roughly twenty watts, can outperform supercomputers on many perceptual tasks. Hardware that natively supports spiking dynamics could therefore deliver dramatic improvements in energy efficiency, particularly for edge applications such as wearable sensors, medical implants, and autonomous systems where power budgets are unforgiving.

Until now, building spiking hardware has typically required dedicated devices such as memristors, phase-change memory cells, or specialized neuron circuits, each fabricated separately from the logic elements of the surrounding system. That separation imposes penalties in chip area, fabrication complexity, and the energy cost of moving signals between distinct regions of a circuit. The new work collapses that distinction. Because every transistor in the architecture is potentially reconfigurable, a chip could dynamically allocate its resources, dedicating more of its fabric to spiking computation during sensory processing tasks and reprogramming sections for deterministic logic when precise arithmetic is required. This fluid boundary between neural and digital operation is what the researchers describe as a neural-network-in-logic architecture.

The ferroelectric gating mechanism deserves particular attention for what it implies about energy efficiency. Conventional transistor-based neuron circuits often need capacitors or feedback loops to accumulate charge and emulate neuronal integration, and they lose their state when power is removed. A ferroelectric gate, by contrast, stores its polarization intrinsically. In the spiking mode, the ferroelectric layer can integrate the effect of repeated input pulses by gradually shifting its polarization, acting as an intrinsic memory of recent activity. The result is a neuron whose history is physically encoded in the material itself, reducing the overhead associated with maintaining state and enabling genuinely event-driven operation. Because molybdenum disulfide channels are atomically thin, the electrostatic coupling between the ferroelectric polarization and the channel is unusually strong, which the researchers identify as essential to achieving reliable switching behavior at practical operating voltages.

Molybdenum disulfide has emerged as one of the most promising two-dimensional semiconductors for post-silicon electronics. Unlike graphene, which lacks a natural band gap, molybdenum disulfide is a semiconductor with favorable transport properties even in monolayer form. Its inert, dangling-bond-free surface means that interfaces with gate dielectrics are remarkably clean, reducing the scattering and variability that plague conventional scaled transistors. These properties have made it a favorite candidate for ultimately scaled electronics, and the new study demonstrates that the same material platform can serve functions far beyond simple switching. The combination of a two-dimensional channel with a ferroelectric gate effectively unites two of the most active research directions in device engineering into a single, multifunctional structure.

The demonstration of logic functionality alongside spiking behavior is more than a technical curiosity. Real-world intelligent systems rarely consist of neural computation alone; they require interfacing with digital peripherals, preprocessing data, and executing control decisions that demand exact, repeatable outcomes. A processor that can host both computational styles on a shared, reconfigurable fabric could avoid the energy and latency costs of shuttling data between separate neural and digital dies. The researchers show that individual transistors and small circuits built from them can be toggled between spiking and logic roles and reprogrammed repeatedly, establishing the foundation for architectures in which the boundary between inference and computation is drawn in software rather than silicon.

Significant engineering challenges remain before such devices could appear in commercial products. Ferroelectric materials integrated with two-dimensional semiconductors are still maturing, and questions of endurance, uniformity across large wafers, and long-term stability will need to be answered at scale. Fabricating high-quality molybdenum disulfide over the large areas required for industrial manufacturing remains an active area of research, although recent progress in wafer-scale growth of two-dimensional materials suggests the obstacle is one of engineering refinement rather than fundamental physics. The operating characteristics of the spiking elements, including threshold variability and response speed, will also need to be characterized and optimized for large networks.

Nevertheless, the significance of the demonstration is difficult to overstate. The semiconductor industry has spent decades pursuing ever finer transistors, but the diminishing returns of miniaturization have pushed researchers toward devices that do more with each switching element. A transistor that can remember, spike, and compute, reconfigurable on demand, represents exactly the kind of functional diversification that next-generation computing may require. If the reconfigurable molybdenum disulfide dual-gate architecture can be scaled to arrays of thousands or millions of devices, it could pave the way toward chips that learn, adapt, and compute within a single unified fabric, blurring the line between the machines we program and the brains that inspire them. For now, the work stands as a striking proof of concept that the boundary between neural and conventional computing can be drawn, and redrawn, atom by atom.

Subject of Research: Reconfigurable molybdenum disulfide dual-gate transistors with ferroelectric gating for spiking neural network-in-logic hardware architectures

Article Title: A spiking neural network-in-logic architecture based on reconfigurable molybdenum disulfide dual-gate transistors with ferroelectric gating

Article References: Li, L., Zheng, H., Li, C., Xiang, H., Wang, J., Zheng, F., Chen, M., Chien, Y.-C., Gao, J., Huo, J., Chi, D., Fong, X., Wan, Y., Meng, W., Li, L.-J., & Ang, K.-W. (2026). A spiking neural network-in-logic architecture based on reconfigurable molybdenum disulfide dual-gate transistors with ferroelectric gating. Nature Electronics. https://doi.org/10.1038/s41928-026-01706-0

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01706-0

Keywords: spiking neural networks, molybdenum disulfide, ferroelectric gating, dual-gate transistors, neuromorphic computing, two-dimensional materials, reconfigurable logic, Nature Electronics, energy-efficient computing, post-silicon electronics, neural-network-in-logic, nonvolatile memory

The review, authored by Nada Salem, Ahmed Shaker, Mahmoud Ossaimee, Ahmed Saeed, Mohamed Abouelatta, and El-Sayed M. El-Rabaie, takes an unusually integrated approach. Rather than treating device physics, manufacturing, and circuit applications as separate silos, the authors connect the atomic structure of carbon nanotubes directly to transistor behavior and ultimately to commercial viability. This matters because the performance of a CNTFET is not determined by the nanotube alone; contact resistance, tube alignment, density control, metallic-tube removal, and compatibility with existing CMOS manufacturing all shape whether carbon can genuinely replace silicon in a factory setting.

At the heart of the technology lies a deceptively simple material trick. A carbon nanotube is a sheet of graphene rolled into a cylinder roughly one nanometer in diameter, and the precise way it is rolled, defined by its chirality indices (n, m), determines whether it behaves as a metal or a semiconductor. Tubes in which the difference between the two indices is divisible by three are nominally metallic, while the rest are semiconducting. For semiconducting single-walled tubes, the bandgap scales approximately inversely with diameter, following the relation Eg of about 0.84 divided by the diameter in nanometers. That simple formula gives device engineers a powerful tuning knob: choosing the tube diameter effectively sets the threshold voltage, the leakage current, and the ON-state current of the resulting transistor.

The physics inside these devices is equally striking. Because carriers are confined to a one-dimensional channel, transport can approach the ballistic limit, where electrons traverse the channel without scattering. Clean carbon nanotube channels have demonstrated carrier mobilities of roughly 1,000 to 10,000 square centimeters per volt-second, an order of magnitude or more above scaled silicon, with characteristic carrier velocities of 2 to 5 times ten to the seventh centimeters per second against a theoretical Fermi velocity ceiling near 8 times ten to the seventh. Subthreshold swings can approach 60 to 80 millivolts per decade, and ON/OFF current ratios spanning 10^5 to 10^8 have been reported depending on diameter, contacts, and dielectric engineering. These numbers explain why researchers have chased carbon nanotubes since the first CNTFET was demonstrated in 1998.

Architecture has evolved considerably since those early proof-of-concept devices. Back-gated transistors, in which the silicon substrate itself acts as the gate, were simple to build but suffered from contact resistances of a megohm or more and weak electrostatic control. Top-gated designs introduced thin dielectrics deposited by atomic layer deposition, tightening gate coupling and enabling individual devices to be isolated on a single wafer. Wrap-around or gate-all-around structures, demonstrated in 2008, surround the nanotube entirely, suppressing leakage and short-channel effects most effectively. Suspended devices, in which the tube hangs free over a trench, minimize substrate scattering and reveal the intrinsic transport properties of the material, though mechanical instability and limited dielectric options keep them largely a laboratory tool.

Modeling this zoo of devices has produced a rich theoretical landscape. Ballistic models, built on the Landauer formalism, estimate the performance ceiling of ideal short-channel devices. Quasi-ballistic and non-ballistic models add phonon scattering through virtual-source and Landauer-Büttiker approaches, capturing the roughly 30 percent current reduction that dissipative transport imposes in realistic channels. Tunneling-based compact models account for band-to-band tunneling that dominates in small-bandgap tubes under bias, while full non-equilibrium Green’s function formulations solve quantum transport self-consistently with electrostatics, linking device behavior directly to the chiral index of the tube. For circuit designers, SPICE-compatible compact models such as the Stanford virtual-source CNFET model bridge the gap, embedding quantum capacitance, contact resistance, and ambipolar conduction into tools that can evaluate logic, memory, and radio-frequency circuits.

Fabrication remains the decisive battleground. Modern processes grow horizontally aligned nanotube arrays on quartz by chemical vapor deposition at densities near three tubes per micrometer, transfer them to oxidized silicon wafers, selectively remove metallic tubes, and deposit high-k gate stacks of titanium dioxide with titanium-platinum electrodes. The resulting devices show improved ON/OFF ratios and reduced device-to-device variability, and the low processing temperatures make the route compatible with CMOS thermal budgets. On a very different frontier, aerosol jet printing has been used to fabricate working CNTFETs on flexible Kapton substrates using silver ink electrodes and cross-linked polymer dielectrics, opening a path toward wearable and bendable electronics that rigid silicon cannot serve.

The application portfolio is expanding fast. CNTFET biosensors have detected the H1N1 virus, DNA modifications, prostate-specific antigen at concentrations from 5 to 5000 picograms per milliliter, and SARS-CoV-2 spike protein epitopes within minutes, exploiting the nanometer-scale match between tube and biomolecule. In memory research, devices using hafnium oxide gates have achieved write and erase operations with 100-nanosecond pulses, roughly 10,000 times faster than earlier carbon nanotube memory, with retention exceeding four hours and endurance past 18,000 cycles. Digital demonstrations include 1-kilobit six-transistor SRAM arrays built with carbon nanotube CMOS, ternary logic gates that combine CNTFETs with resistive memory, and approximate multipliers for energy-efficient image processing. Wafer-scale synaptic transistors exploit the sensitivity of nanotubes to charged defects, positioning carbon at the heart of neuromorphic computing architectures that dissolve the boundary between logic and memory.

Even with this momentum, the review is candid about the barriers. Chirality-controlled synthesis of high-purity semiconducting tubes at wafer scale remains unsolved, and even small diameter variations shift bandgaps enough to scatter threshold voltages across a chip. Residual metallic tubes create leakage paths, contact engineering at the metal-carbon interface still introduces Schottky barriers and variability, and self-heating in real devices, where nanotube-to-substrate thermal boundary resistance limits heat dissipation, threatens reliability despite the exceptional intrinsic thermal conductivity of individual tubes. Uniform high-k dielectric deposition on chemically inert nanotube surfaces, variation-aware compact modeling, and back-end-of-line integration with existing CMOS flows round out the challenge list.

What emerges from the full picture is a technology standing at a genuine inflection point. The intrinsic material advantages of carbon nanotubes, from near-ballistic transport and diameter-tunable bandgaps to mechanical flexibility and bioscale sensitivity, are no longer in dispute. The remaining work is industrial: scalable purification, wafer-level alignment, stable low-resistance contacts, and standardized benchmarking against silicon and emerging two-dimensional materials. If those pieces fall into place, the authors conclude, CNTFETs are strong contenders to deliver the high-performance, energy-efficient, and miniaturized electronics that the next generation of computing, sensing, and communication systems will demand.

Subject of Research: Carbon nanotube field-effect transistors as post-silicon electronic devices

Article Title: Structure, modeling, fabrication, and applications of carbon nanotube field-effect transistors: a comprehensive review

Article References: Salem, N., Shaker, A., Ossaimee, M., Saeed, A., Abouelatta, M., & El-Rabaie, E.-S. M. (2026). Structure, modeling, fabrication, and applications of carbon nanotube field-effect transistors: a comprehensive review. Results in Physics, 89, Article 108749. https://doi.org/10.1016/j.rinp.2026.108749

Image Credits: AI Generated

DOI: 10.1016/j.rinp.2026.108749

Keywords: carbon nanotubes, CNTFET, field-effect transistors, post-silicon electronics, Moore's law, bandgap engineering, neuromorphic computing, biosensors, SRAM, CMOS compatibility, quantum transport, flexible electronics