At the heart of this research lies the fabrication of metal–semiconductor heterojunctions formed by stacking niobium disulfide (NbS₂), a metallic TMDC, with molybdenum disulfide (MoS₂), a well-known semiconducting TMDC. The fine-tuned interface between these materials enables unprecedented control over electrical properties, substantially lowering the contact resistance—a key bottleneck in the performance and energy efficiency of nanoelectronic devices. By reducing contact resistance, devices built on these heterostructures can operate with markedly lower power, heralding a new era of energy-conscious computing technologies.

The heterostructures fabricated via the novel method boast precise patterning capabilities, allowing for the creation of complex device architectures without sacrificing uniformity or quality. This flexibility is critical for integrating the TMDCs into existing semiconductor manufacturing workflows, potentially bridging the gap between emerging 2D materials and commercial electronics. The scalability of the synthesis process means that posterity is not limited to explorations in laboratory settings; rather, the mass production of high-performance 2D electronic components is now a feasible reality.

One of the most compelling applications demonstrated with these NbS₂–MoS₂ heterostructures is in non-volatile memory (NVM) devices. These memories retain information without power, which is essential for reducing standby power consumption in electronic systems. The researchers report exceptional programming capabilities, wherein the memory states can be switched reliably with high precision. The robust data storage performance of these devices ensures longevity and resilience, both critical factors for commercial adoption.

In contrast to 3D NAND flash memory, which achieves high storage density through vertical stacking of memory cells, this new 2D memory platform leverages an atomically thin, planar architecture. This planar integration offers seamless compatibility with logic devices, enabling combined transistor and memory functionalities on the same chip. Such integration is vital for the development of heterogeneous computing architectures, wherein different computing elements coexist closely to optimize performance and power efficiency.

Moreover, the potential to scale the gate length of these memory devices down to 10 nanometers represents a significant stride towards commercialization and miniaturization. As gate lengths shrink, the challenges of maintaining device integrity and performance intensify, making the demonstrated operation at these scales especially noteworthy. The planar NbS₂–MoS₂ platform holds promise for overcoming scaling limits that plague conventional semiconductor devices, enabling the continuation of Moore’s Law-like progression in device density and capability.

Fundamentally, this research underscores the transformative role of advanced materials design in overcoming traditional limitations of electronic components. The meticulous engineering of 2D metal–semiconductor interfaces not only optimizes electrical behavior but also introduces new paradigms for device architecture and energy consumption. This marriage of material science and device physics exemplifies the interdisciplinary approach needed to push the boundaries of computing technology.

The scalability aspect of the synthesis method is particularly remarkable, given the typical challenges in producing large-area 2D heterostructures with high uniformity. Traditional mechanical exfoliation techniques yield high-quality flakes but suffer from low yield and poor reproducibility. Chemical vapor deposition (CVD) methods have improved throughput but often compromise on uniformity and pattern precision. The new method strikes an ideal balance, harnessing the strengths of scalable fabrication while maintaining the stringent quality requirements necessary for electronic applications.

From an application perspective, the ability to create non-volatile memory elements with low contact resistance directly addresses the pressing need for energy-efficient memory technologies in modern electronics. Computing systems increasingly demand memories that consume less power without sacrificing speed or data retention capabilities. By enabling low-power operation and robust memory retention simultaneously, these TMDC-based devices could significantly contribute to reducing the overall energy footprint of electronics.

The implications extend beyond mere memory applications. The integration of metallic and semiconducting TMDC layers opens avenues for novel device concepts such as in-memory computing systems, which aim to merge logic and storage functions to minimize data movement and associated energy costs. This approach has the potential to vastly improve computational efficiency in applications ranging from artificial intelligence to edge computing, where low-power, high-density devices are paramount.

Critically, the planar architecture of the NbS₂–MoS₂ heterostructure provides advantages not only in device integration but also in thermal management and reliability. The atomically thin nature of the materials allows for efficient heat dissipation and reduces defect densities that typically emerge at interfaces in thicker, bulk structures. This contributes to the operational stability and longevity of devices built on this platform, addressing a major hurdle faced by many emerging nanoelectronic components.

From a broader scientific vantage, this work exemplifies the synthesis–structure–property relationship that underpins cutting-edge materials science. The precise control over heterostructure formation ensures that electronic transport across the metal–semiconductor boundary is optimized, propelling device performance to new heights. Such control is vital as the electronics industry moves towards complex, multifunctional nanosystems where every atomic layer can dramatically influence overall behavior.

Looking ahead, the demonstrated techniques open promising perspectives for addressing the critical challenges in the semiconductor industry, especially as traditional silicon technologies approach fundamental physical and economic limits. The ability to fabricate high-quality, scalable 2D TMDC heterostructures with tunable electronic properties aligns well with the industry’s quest for novel materials that can sustain Moore’s Law and meet the escalating demands for energy-efficient computation.

Furthermore, the inherent compatibility of these TMDC heterostructures with existing fabrication processes mitigates integration barriers. This smooth transition pathway from research to manufacturing could accelerate the adoption of 2D materials in commercial memory and logic devices. As industries increasingly embrace heterogeneous integration and system-on-chip approaches, innovations such as these will be pivotal in shaping the future semiconductor landscape.

In conclusion, the synthesis of patterned NbS₂–MoS₂ metal–semiconductor heterostructures marks a significant milestone in 2D materials research and its application in nanoelectronics. The union of high-quality, scalable fabrication with demonstrated device utility in non-volatile memory with low-power operation highlights a versatile platform poised to influence multiple domains within electronics. This work not only expands the horizons of materials science but also charts a pragmatic course towards realizing the next generation of ultra-efficient computing devices.

Subject of Research: Metal–semiconductor 2D heterostructures in scalable nanoelectronic devices

Article Title: Non-volatile memories based on patterned metal–semiconductor heterostructures of niobium disulfide and molybdenum disulfide

Article References:
Wang, Z., Migliato Marega, G., Collette, E. et al. Non-volatile memories based on patterned metal–semiconductor heterostructures of niobium disulfide and molybdenum disulfide. Nat Electron (2026). https://doi.org/10.1038/s41928-026-01634-z

Image Credits: AI Generated

DOI: https://doi.org/10.1038/s41928-026-01634-z

For years, the enigmatic stochasticity inherent in memristor operation posed a significant obstacle to the design of reliable devices capable of leveraging this randomness for practical purposes. Memristors operate by forming and dissolving metallic ion filaments within their solid electrolyte matrix under voltage bias. These filaments spontaneously emerge and disappear, creating volatile memory states that hold immense promise for applications demanding intrinsic randomness, such as true random number generation (TRNG) critical for secure cryptographic systems and probabilistic computing architectures aimed at tackling complex optimization problems. Despite their potential, capturing the real-time filamentary dynamics inside memristors remained a formidable challenge due to the nanoscale phenomena occurring inside opaque device structures.

Addressing this investigative gap, the research team implemented scanning thermal microscopy (SThM), a highly sensitive nanoscale thermal probing technique. By harnessing SThM’s capability to detect minute Joule heat signatures during filament formation and rupture events, they managed to visualize spatially localized temperature variations on the device surface related to resistive switching. This approach unveiled compelling evidence of multiple localized hot spots arising and vanishing repeatedly, which correlates strongly with the presence of several conductive filaments co-existing and intermittently conducting current. The thermal imaging corroborated the theoretical prediction that the resistive switching process in volatile memristors is far from a single filament event but rather a dynamic competitive interplay modulated by ionic motion and Joule heating.

The identification of these multi-filament dynamics, entangled with complex electrothermal feedback mechanisms, sheds light on the intrinsic stochasticity in memristor operation. This nuanced understanding enables the precise modulation and optimization of filament behavior, allowing researchers to tailor devices that maximize stochastic properties required for next-generation computational functions. Through sophisticated device engineering, stochastic memristors can now be effectively harnessed as hardware true random number generators, capable of generating entirely unpredictable digital and analog random sequences fundamental for secure data encryption and probabilistic information processing paradigms.

Expanding on the practical implications, the team successfully devised a bimodal TRNG system utilizing the memristors’ inherent stochastic switching to produce random numbers in both digital and analog domains. This innovation marks a transformative step toward integrating memristor-based true randomness sources directly into hardware security modules, circumventing the limitations of conventional pseudo-random algorithms and thereby enhancing cryptographic robustness. In a striking demonstration of real-world applicability, the researchers conducted secure data encryption and decryption sequences using the randomness derived from the stochastic memristors as encryption keys, decisively illustrating the feasibility of this technology in safeguarding sensitive information.

Furthermore, the study ventured into exploring the memristor’s potential for probabilistic computing, an emerging computational paradigm inspired by the stochastic processes found in natural systems. By manipulating the multi-filament resistive switching, the team implemented an inverse operation of a binary full-adder circuit — a fundamental building block of arithmetic logic — showcasing how such devices could perform complex logic functions under probabilistic frameworks. This development signifies a critical advance toward designing low-energy, fault-tolerant computing systems that can efficiently solve combinatorial optimization and machine learning challenges, which are pivotal for artificial intelligence and data-centric applications.

Professor Jung Ho Yoon reflected on the implications of these findings, emphasizing the paradigm shift from viewing memristor functionality as a simplistic filament rupture model to appreciating the rich, multi-filament and electrothermal interactions underpinning device behavior. This deeper mechanistic insight paves the way for the rational design of intelligent semiconductor devices tailored for stochastic and probabilistic computing architectures. The team envisions establishing global leadership in this technological frontier by translating their fundamental discoveries into practical, scalable applications that revolutionize how information is processed and secured.

The experimental success of visualizing multi-filament competition through nanoscale thermal imaging techniques stands as a methodological milestone. It underscores the power of combining advanced microscopy with rigorous electrothermal modeling to decode nanoscale device physics that were previously obscured. This breakthrough is expected to stimulate further research into tuning memristive properties via material engineering and device geometry optimization, ultimately unlocking new functionalities for neuromorphic computing, random number generation, and secure communication systems.

Supported by prominent South Korean funding agencies including the National Research Foundation and the Commercialization Promotion Agency for R&D Outcomes, this study represents a robust interdisciplinary effort encompassing materials science, electrical engineering, and applied physics. The full findings have been detailed in the article titled “Unraveling Origin of Stochasticity in Multi-Filamentary Memristor,” published on January 21 in the esteemed journal Advanced Functional Materials, boasting an impact factor of 19.0 and high citation ranking. The rigorous peer-reviewed publication offers a comprehensive exposition of the experimental techniques, theoretical models, and potential device architectures arising from this work.

In summary, this investigation redefines our understanding of volatile memristor devices by revealing a complex, multi-filament conductive framework coupled with electrothermal modulatory effects responsible for their stochastic switching behavior. These insights not only resolve longstanding questions about randomness origins in memristors but also unlock new possibilities for next-generation computational systems characterized by true hardware-level randomness and probabilistic processing capabilities. As the semiconductor industry seeks innovative solutions amid the limits of conventional technologies, this research charts a promising route toward integrating inherently stochastic memristors into future intelligent information processing platforms.

Subject of Research: Stochastic Switching Mechanisms in Ion-Motion-Mediated Volatile Memristors and Their Applications in True Random Number Generation and Probabilistic Computing

Article Title: Unraveling Origin of Stochasticity in Multi-Filamentary Memristor

News Publication Date: January 21, 2024

Web References: http://dx.doi.org/10.1002/adfm.202527482

Image Credits: Prof. Jung Ho Yoon

Keywords

Materials Science, Memristor, Stochastic Switching, Volatile Memristor, Conductive Filaments, Electrothermal Effects, Scanning Thermal Microscopy, True Random Number Generator, Probabilistic Computing, Semiconductor Devices, Joule Heating, Cryptography

Hafnium oxide, HfO2, has garnered considerable attention within the realm of microelectronics due to its remarkable properties. Characterized by a high dielectric constant, excellent thermal stability, and a wide band gap, HfO2 is an exceptional candidate for next-generation semiconductor devices. These features, however, present notable obstacles for precise and smooth etching of HfO2 films, which are critical for the miniaturization required in modern electronic components.

The conventional methods employed in plasma-enhanced ALE of HfO2 typically rely on the use of harmful halogen gases, including fluorine and chlorine. While these gases facilitate the etching process through physical and chemical reactions, they also contribute to environmental concerns, acting as greenhouse gases and posing toxicity risks. The success of the new halogen-free method was recently documented in the journal Small Science, marking a promising step toward sustainable semiconductor manufacturing practices.

In their pursuit of a cleaner etching process, the research team, led by Professors Shih-Nan Hsiao and Masaru Hori from Nagoya University, innovatively combined N2 and O2 plasma treatments to create a two-step etching process. Initial experimentation involved bombarding HfO2 films with N+ ions under a controlled environment, facilitating the bonding of nitrogen atoms to the oxide film. This crucial first phase sets the stage for a subsequent O2 plasma treatment, which effectively removes nitrogen-rich surface layers, leading to the emission of volatile byproducts without the use of halogen compounds.

This cyclic etching method demonstrates significant advantages when compared to traditional processes. Studies reveal that the generated byproducts from the new technique exhibit high volatility, minimizing the risk of residue buildup on chamber walls, which can subsequently impair the performance of electronic devices. Such efficiency in byproduct management is a noteworthy aspect of the new approach, ensuring that the integrity of the etching environment is preserved.

Throughout the course of their research, the scientists meticulously adjusted the energy levels of N+ ions using radio-frequency power applied to the bottom electrode. This adjustment was instrumental in achieving a precise etch depth per cycle, consistently ranging between 0.023 and 0.107 nm. This level of control over the etching process symbolizes a crucial advancement in the capability for engineers to design and fabricate semiconductor components that demand increasingly tighter tolerances.

In addition to their innovative etching process, the researchers employed advanced in situ analytical techniques such as attenuated total reflection Fourier transform infrared spectroscopy and X-ray photoelectron spectroscopy, which proved invaluable in elucidating the underlying reaction mechanisms during the etching. These analyses confirmed the constant formation of Hf-N bonds via a ligand exchange mechanism, whereby nitrogen atoms effectively replaced surface oxygen atoms when exposed to nitrogen plasma. This scientific insight into the reactions was pivotal for optimizing the etching framework further, strengthening the reliability of their groundbreaking results.

Moreover, the effective cyclic nature of this new etching method also facilitated enhanced surface smoothing for HfO2 films. The research demonstrated a reduction in surface roughness by up to 60% after just 20 etching cycles. Such surface refinement is critical for the fabrications of semiconductor devices, ensuring maximal efficiency and performance, which is particularly vital for applications requiring ultrathin structures.

The implications of this halogen-free etching process extend far beyond mere technical achievement. With rising global emphasis on sustainable manufacturing practices, the ability to perform atomic-layer etching at room temperature without toxic byproducts presents a significant ecological advantage. By significantly reducing energy consumption associated with thermal processes and minimizing environmental impact, the newly developed method aligns with broader industry goals towards greener technology.

Professors Hsiao and Hori indicate that this achievement could influence various applications across the electronics landscape. As the semiconductor industry progresses towards integrating two-dimensional materials and advanced nonvolatile memory technologies, HfO2 remains a leading material for device architectures. Furthermore, as device scaling continues towards the atomic realm, the ability to achieve such precise control over material processing stands to redefine the possibilities within modern electronic fabrication.

The capability of this innovative etching technique to produce smooth, uniform surfaces suitable for ultra-thin applications solidifies its potential role in advancing electronic device performance. As the push for smaller, more efficient components increases, this halogen-free method exemplifies the intersection of scientific innovation and sustainability.

In conclusion, the research conducted by Hsiao, Hori, and their collaborative team marks a consequential step in the quest for sustainable semiconductor manufacturing, paving the way for eco-friendly yet efficient production techniques. By moving away from hazardous halogen gases and traditional high-temperature processes, this discovery not only enhances technical capabilities but also aligns with a global initiative toward environmental responsibility in the rapidly evolving field of electronics.

Subject of Research: Halogen-Free Anisotropic Atomic-Layer Etching of HfO2
Article Title: Halogen-Free Anisotropic Atomic-Layer Etching of HfO2 at Room Temperature
News Publication Date: 22-Jul-2025
Web References: Small Science
References: None
Image Credits: Shih-Nan Hsiao

Keywords: Hafnium oxide, atomic-layer etching, halogen-free, semiconductor devices, sustainable manufacturing, N2 plasma, O2 plasma, precision etching, materials science.