Spintronics, the field that exploits the spin of electrons rather than merely their charge, has long promised memory devices that combine non-volatility with high speed. In modern magnetic random-access memory, information is stored in the orientation of a nanoscale magnet and written by transferring angular momentum from a spin-polarized current, a mechanism known as spin–orbit torque. When a current flows through a heavy-metal layer adjacent to a ferromagnet, the resulting torque can switch the magnet’s direction, encoding a zero or a one. The efficiency of that process, however, is governed by the current pulses available from the surrounding circuitry, and this is precisely where the new work makes its mark.

Conventional electronic pulse generators struggle to deliver the combination of amplitude, duration and on-chip integration that aggressive magnetic switching demands. Fast transistors and modulated laser schemes have been explored, but each carries trade-offs in footprint, energy cost or compatibility with dense integrated circuits. The alternative demonstrated here is deceptively simple in concept: a nanoplasma switch embedded on the chip itself. When a modest voltage is applied across a nanoscale gap, the device undergoes a rapid ionization event, forming a miniature plasma discharge that conducts an intense burst of current for an extraordinarily brief interval before extinguishing itself.

The physics of these discharges is rooted in well-understood gas ionization and electron avalanche processes, yet the nanoscale confinement changes the picture considerably. Because the active region is so small, the plasma forms and collapses on timescales set not by bulky external electronics but by the intrinsic carrier dynamics within the gap. The result is a current pulse measured in picoseconds, far faster than the switching speeds of the transistors that would otherwise be needed. Importantly, the switch is not a laboratory curiosity built with exotic equipment; it is fabricated using processes compatible with standard chip manufacturing, which means pulse generation can sit directly alongside the magnetic elements it drives.

The central experimental finding reported in the underlying research is that pulses produced by these nanoplasma switches are fast enough and strong enough to control the magnetization of ferromagnetic heterostructures through spin–orbit torque. In such heterostructures — stacks in which a heavy metal with strong spin–orbit coupling is paired with a thin ferromagnetic layer — the direction of the applied torque depends on the direction of the current. A pulse that drives electrons one way can set the magnet to one orientation; a pulse in the opposite direction can set it to the other. Demonstrating reliable reversal under picosecond excitation is the critical milestone, because it shows that the write mechanism of spintronic memory can keep pace with the fastest pulse sources now available on chip.

Speed matters for more than bragging rights. As memory devices shrink, thermal fluctuations make their magnetic bits less stable, and the window of current amplitudes that switch the bit deterministically narrows. Ultrafast pulses change this balance: they deliver torque in a burst short enough that switching can complete before the accumulated heat spreads through the device, potentially improving energy efficiency while maintaining reliability. Prior studies have shown that sub-nanosecond currents can reduce switching energies relative to slower write operations, and the picosecond regime explored here pushes that trend toward its physical limits. The commentary also situates the result within a growing body of work on plasma-based ultrafast electronics, including earlier demonstrations of nanoscale discharge devices that achieved picosecond switching without semiconductors at all.

Integration is the second pillar of the advance. A pulse generator that lives on the same chip as the memory cell eliminates the parasitic losses of off-chip interconnects, which otherwise smear and attenuate fast pulses before they reach the magnetic element. By placing the nanoplasma switch adjacent to the heterostructure, the researchers ensure that the full amplitude and sharpness of the discharge current arrive where they are needed. This co-location is what makes the approach practical: it converts an impressive physics demonstration into a plausible circuit element. The switch behaves, in effect, as a self-contained nanoscale pulse source that the surrounding CMOS logic can trigger with ordinary voltage signals.

The implications reach beyond memory. Spin–orbit torque switching underlies proposals for magnetic neuromorphic computing, where nanoscale magnets act as artificial neurons, and for non-von Neumann architectures that blur the boundary between storage and computation. If write pulses can be generated on demand in picoseconds with minimal overhead, the operating envelope of such systems widens dramatically. Arrays of nanoplasma-switched magnetic bits could, in principle, be reconfigured at rates approaching terahertz-scale dynamics, although the commentary is careful to note that translating single-device demonstrations into large-scale arrays will require careful management of discharge repeatability, electrode wear and thermal design.

Indeed, the researchers and the commentary both acknowledge the engineering questions that remain. Plasma discharges involve energetic ions and electrons that can erode the electrodes over many switching cycles, and guaranteeing that every pulse has identical amplitude is essential if the switching statistics of the magnetic element are to remain deterministic across billions of operations. Understanding the discharge physics at the nanoscale — how the plasma ignites, how it evolves during the picosecond pulse, and how it decays — will be essential for modeling device lifetimes. The field has already seen rapid progress: recent theoretical and experimental studies of spin–orbit torque, together with related ultrafast switching demonstrations in plasma-based electronics, suggest a maturing toolkit from which robust designs can emerge.

For now, the demonstration marks a conceptual shift. Rather than building ever-faster transistors to drive magnetic devices, engineers can borrow a page from plasma physics and let a nanoscale discharge do the work. The commentary in Nature Electronics frames the result as a step toward ultrafast spintronic systems in which the pulse generation, the magnetic switching and the sensing circuitry all coexist on a single chip. If the remaining reliability and scaling challenges can be met, on-chip nanoplasma switching could become the standard heartbeat of the fastest memories and spin-based processors — devices that write their bits in trillionths of a second while drawing power budgets compatible with mainstream computing.

Subject of Research: On-chip nanoplasma switches generating picosecond current pulses for ultrafast spin–orbit torque switching in ferromagnetic heterostructures

Article Title: On-chip nanoplasma switches for ultrafast spintronics

Article References: Díaz, E. (2026). On-chip nanoplasma switches for ultrafast spintronics. Nature Electronics. https://doi.org/10.1038/s41928-026-01711-3

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01711-3

Keywords: spintronics, nanoplasma, spin–orbit torque, magnetic memory, picosecond pulses, Nature Electronics, ferromagnetic heterostructures, on-chip switching, magnetization reversal, nanoscale devices, MRAM, plasma electronics

Combinatorial optimization is everywhere in modern technology. Designing a chip’s wiring layout, routing vehicles through a delivery network, scheduling flights, and assigning radio frequencies all belong to this family of problems, in which the goal is to find the best configuration from an astronomically large set of possibilities. Many of these tasks are NP-hard, meaning that no known algorithm can solve them efficiently as they grow. Classical computers, built on the von Neumann architecture that separates memory from processing, grind through such problems by evaluating candidate solutions one after another, and the cost quickly becomes prohibitive.

Ising machines take an entirely different approach. They are physical systems engineered to mimic the Ising model, a mathematical framework from statistical physics in which each of many interacting binary variables, called spins, settles into a state that minimizes the total energy of the system. Because any combinatorial optimization problem can be mapped onto such an energy-minimization landscape, a well-engineered Ising machine can let physics do the searching: spins flip stochastically, interact with their neighbors, and collectively relax toward low-energy configurations that correspond to good, and sometimes optimal, solutions. The concept has been realized in quantum annealers, optical platforms built from lasers and fibers, and various electronic chips, each with its own trade-offs between speed, scale, and programmability.

The new machine, which the researchers call VSIM, stands out for the speed at which its spins can change state. At the heart of each spin is a magnetic tunnel junction, the same nanoscale element that stores bits in MRAM. Rather than switching deterministically between two stable states as memory cells do, the device exploits the voltage-controlled magnetic anisotropy effect, in which an applied voltage alters the energy barrier that separates the two magnetic orientations. By tuning the width of a voltage pulse, the team can dial the probability that a single pulse flips the junction anywhere from zero to one hundred percent. That probabilistic switching is exactly what an Ising machine needs, because stochastic spin updates allow the system to escape local energy minima where deterministic algorithms become trapped.

The numbers are striking. Spin updates take between 0.3 and 1 nanosecond, firmly in the sub-nanosecond regime that has eluded most alternative platforms, and each update consumes less than 40 femtojoules per spin. Because the magnetic tunnel junctions are integrated directly with CMOS circuitry, the machine combines the density and manufacturability of standard semiconductor technology with the intrinsic randomness of nanoscale magnetism. The write currents involved are low, another consequence of the voltage-based control mechanism, and the all-to-all connectivity on the chip means any spin can in principle influence any other, which matters greatly for faithfully encoding the interaction structure of real optimization problems.

To demonstrate that the machine is more than a laboratory curiosity, the team mapped two problems drawn directly from electronic design automation, the software domain that underpins the entire semiconductor industry. The first is global routing, the task of deciding how to connect millions of circuit components across a chip’s wiring grid while minimizing wire length and congestion. The second is layer assignment, which determines which of several metal layers each wire segment should occupy. Both are commercially critical steps in chip design, and both were encoded as Ising Hamiltonians and solved on the hardware. In an era when chip design complexity is straining conventional design automation tools, hardware solvers aimed squarely at this workflow have obvious practical appeal.

Benchmarked against standard Max-cut test problems, a canonical yardstick in the Ising machine literature, the chip delivered high-quality solutions at a system-level energy efficiency of 1.92 times ten to the fifth solutions per second per watt. That figure reflects not just the raw speed of the magnetic tunnel junctions but the whole pipeline: an FPGA board configures the couplings, drives the annealing schedule, and reads out the final spin configuration. The researchers also examined how robustly the machine performs in the face of device-to-device variation, an unavoidable reality of nanoscale fabrication, finding that solution quality holds up well provided the single-pulse switching probability stays above roughly sixty percent.

The work lands in a crowded and fast-moving field. Quantum annealers have demonstrated computations on thousands of superconducting qubits, coherent Ising machines built from optical fiber loops have handled 100,000-spin problems, and a parade of CMOS-based annealing chips has appeared at recent circuits conferences. Spintronic approaches, in which the spin itself is the stochastic element, have generally been limited to far smaller arrays. What distinguishes this demonstration is the combination of scale, at 96,000 spins, with sub-nanosecond update speed and full CMOS integration, a trio of attributes that no single previous platform has offered simultaneously.

There remain caveats and open questions. The reported demonstrations, while industrially relevant, are specific problem instances, and scaling the machine to the problem sizes encountered in full-scale chip design will require larger arrays, better coupling precision, and careful management of annealing schedules. The metrics used to compare heterogeneous Ising machines, spanning quantum, optical, and electronic implementations, are themselves still being debated by the community. And like all physics-based solvers, Ising machines provide high-quality solutions rather than guaranteed optima, which may or may not suffice depending on the application.

Even so, the demonstration points toward a future in which the memory devices inside every processor become active computational elements. The voltage-controlled magnetic tunnel junction at the center of this work is already the storage element of a commercial memory technology, which means the path from laboratory demonstration to embedded accelerator runs through established fabrication infrastructure rather than exotic physics. If spintronic Ising machines can keep pace in scale, they could take their place alongside GPUs and dedicated AI accelerators as specialized hardware for the optimization workloads that quietly underpin modern technology. The team has released its source data and code to the community, an invitation for researchers worldwide to stress-test this new class of machine against the hardest problems they can find.

Subject of Research: A CMOS-integrated spintronic Ising machine using magnetoresistive memory for fast, energy-efficient combinatorial optimization

Article Title: An Ising machine for combinatorial optimization based on sub-nanosecond CMOS-integrated magnetoresistive random-access memory

Article References: An Ising machine for combinatorial optimization based on sub-nanosecond CMOS-integrated magnetoresistive random-access memory. (n.d.). https://doi.org/10.1038/s41928-026-01700-6

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01700-6

Keywords: Ising machine, combinatorial optimization, spintronics, MRAM, magnetic tunnel junction, voltage-controlled magnetic anisotropy, Nature Electronics, electronic design automation, global routing, Max-cut, probabilistic computing, CMOS integration

The Ising model, borrowed from statistical physics, describes a collection of spins that can each point up or down, with interactions that either favor alignment or anti-alignment between neighboring spins. Finding the lowest-energy spin configuration of such a system is mathematically equivalent to a broad class of hard combinatorial problems, a correspondence that Andrew Lucas laid out systematically in a widely cited 2014 paper in Frontiers of Physics. Because of this equivalence, researchers have long been interested in building physical systems, so-called Ising machines, whose natural dynamics drive them toward low-energy states, allowing the hardware itself to perform the search that would otherwise demand enormous computational effort from conventional digital machines.

Several approaches to Ising machines have been explored over the past decade. In 2016, two landmark demonstrations appeared in Science: a team led by T. Inagaki and colleagues at NTT built a coherent Ising machine using a network of optical parametric oscillators, while Peter McMahon and collaborators at Stanford University demonstrated a similar photonic architecture with improved scaling and solution quality. These photonic systems showed that physical analog hardware could indeed compete with digital algorithms on certain problem instances, sparking a worldwide effort to find faster, cheaper and more compact physical substrates for Ising-style computation.

Magnetic devices entered this race for compelling reasons. A magnetic tunnel junction consists of two ferromagnetic layers separated by a thin insulating barrier, and its resistance depends on the relative orientation of the two magnetizations, parallel or antiparallel. Those two resistance states map naturally onto the two states of an Ising spin, up or down. Furthermore, each magnetic tunnel junction is, in effect, a tiny bar magnet with genuine thermal fluctuations, a property that Kerem Camsari, Rafatul Faria, Brian Sutton and Supriyo Datta exploited in 2017 in Physical Review X to propose stochastic units called p-bits, probabilistic bits that fluctuate between states with tunable bias and can implement powerful sampling-based optimization and inference algorithms when networked together.

The work highlighted in the new perspective, an article by S. Li and colleagues in Nature Electronics, advances this program by using voltage-controlled magnetic anisotropy to switch and modulate the magnetic tunnel junctions in an integrated array. Voltage-controlled magnetic anisotropy, first demonstrated prominently by W.-G. Wang, M. Li, S. Hageman and C. L. Chien in Nature Materials in 2012, allows the magnetic anisotropy of an ultrathin ferromagnetic film, and hence its energy barrier and preferred magnetization direction, to be tuned by applying a voltage across an adjacent gate dielectric. Because this mechanism acts through an electric field rather than a current, it promises dramatically lower energy per operation than current-based switching schemes, addressing one of the central bottlenecks for scaling magnetic logic and memory technologies.

In the architecture described by the perspective, the integrated array of magnetic tunnel junctions serves as a physical realization of Ising spins, while the coupling between spins, the analog of the exchange interactions in the Ising model, encodes the structure of the optimization problem being solved. By driving the array with appropriate voltage control, the system explores the configuration space and relaxes toward low-energy states that correspond to good, and in favorable cases optimal, solutions of the encoded problem. Crucially, the perspective emphasizes that this can be done quickly and with low energy consumption, two figures of merit that determine whether such hardware can move beyond laboratory demonstrations and into practical use for real workloads in logistics, finance, drug discovery and chip design.

The new report builds on a series of recent advances in magnetic Ising and probabilistic computing hardware. In 2023, Y. Shao and colleagues published work in Nanotechnology on magnetic tunnel junction-based approaches to Ising computation, and in 2024, J. Si and collaborators reported in Nature Communications on magnetic tunnel junction arrays for such applications. More recently, in 2026, M. A. Iftakher and colleagues described related stochastic magnetic computing concepts in Nature Communications. Together, these studies trace a rapid trajectory from single-device physics toward integrated, array-scale systems, and the Li and colleagues work reported in Nature Electronics represents an important consolidation of that progress into a functional, integrated platform for model optimization problems.

What makes the magnetic approach particularly attractive is its compatibility with existing semiconductor manufacturing. Magnetic tunnel junctions are already embedded in billions of consumer devices as memory cells, and the materials and process technology for fabricating them at scale is mature. A computing architecture that repurposes these devices as stochastic optimization elements could, in principle, be fabricated alongside conventional CMOS circuitry, opening a path toward hybrid chips in which a conventional processor offloads hard combinatorial kernels to a dense magnetic Ising fabric. The low switching energies enabled by voltage-controlled magnetic anisotropy further strengthen the case, since the energy cost of each spin update is a key determinant of overall system efficiency at scale.

Challenges nonetheless remain before magnetic Ising machines can challenge state-of-the-art algorithms and specialized processors on production-scale problems. The quality of solutions found by physical relaxations depends on the fidelity of the implemented couplings, the stability and controllability of the stochastic dynamics, the number of spins that can be integrated, and the efficiency of reading out and verifying results. Problems of practical interest often involve far more variables than any near-term chip can host, requiring embedding techniques that inflate problem size, and the performance of Ising machines against the best classical solvers continues to be debated. The authors of the perspective, who are affiliated with the George Washington University and the Physical Measurement Laboratory of the National Institute of Standards and Technology, note that demonstrating clear, reproducible advantages on benchmark problems will be essential for the field’s credibility.

Even so, the demonstration that an integrated array of magnetic tunnel junctions can rapidly and efficiently solve Ising-model optimization problems marks a significant milestone at the intersection of magnetism, memory technology and unconventional computing. It suggests that the devices built to remember bits may also be enlisted to search for them, turning the physics of nanoscale magnetism into a computational resource. As the hardware matures and couples more tightly with conventional electronics, magnetic Ising machines could become a practical accelerator for some of the hardest, most economically consequential computational problems that society routinely faces.

Subject of Research: Using integrated arrays of magnetic tunnel junctions with voltage-controlled magnetic anisotropy to accelerate Ising-model-based combinatorial optimization.

Article Title: Magnetic memory accelerates combinatorial optimization

Article References: Zhang, H., Borders, W. A., & Stiles, M. D. (2026). Magnetic memory accelerates combinatorial optimization. Nature Electronics. https://doi.org/10.1038/s41928-026-01713-1

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01713-1

Keywords: magnetic tunnel junctions, Ising machines, combinatorial optimization, voltage-controlled magnetic anisotropy, Nature Electronics, probabilistic computing, spintronics, low-power computing, p-bits, statistical physics, MRAM, unconventional computing

The significance of the result lies in what it removes from the equation. Spin–orbit torque (SOT) switching, the physical mechanism at the heart of the work, allows engineers to reverse the direction of magnetization in a nanoscale magnetic layer by injecting an in-plane current into an adjacent heavy metal. The current’s spin angular momentum is transferred to the magnet, exerting a torque that can tip its north and south poles. Because the effect is purely electrical, it has long been viewed as the natural write mechanism for next-generation magnetic random-access memory (MRAM), a technology that stores data in magnetic orientations rather than electric charges and therefore retains information even when power is removed. The catch has always been speed and energy: writing reliably with conventional electronics has typically required pulses lasting microseconds or longer, dissipating far more energy than an ideal memory cell should.

Picosecond pulses, by contrast, promise a dramatic shortcut. When the write pulse is compressed from microseconds down to a few trillionths of a second, the energy delivered scales down accordingly, and the magnetization dynamics themselves enter a faster, more coherent regime. But generating such pulses has traditionally demanded mode-locked laser systems and photoconductive switches, an approach that is bulky, expensive, power-hungry and fundamentally incompatible with the dense, CMOS-integrated architecture a commercial memory chip requires. The Singapore team’s answer was to abandon optics altogether and exploit a phenomenon more familiar to high-voltage engineers than to memory designers: the abrupt, avalanche-like breakdown of a plasma confined within a nanoscale gap.

The device works by charging a capacitor-like structure and then letting a nanometer-scale gap break down in a controlled discharge. When the voltage across the tiny gap exceeds a threshold, a nanoplasma forms almost instantaneously, and the stored charge dumps through the gap in a burst measured in picoseconds. Because the discharge is triggered purely by voltage, the entire pulse generator can be patterned lithographically alongside the magnetic devices it is meant to drive, making it genuinely chip-compatible. In their experiments, the researchers showed that the generator could produce pulses as short as 6.4 picoseconds with peak amplitudes above 100 volts, figures that place the device firmly in the territory previously accessible only to optical pump–probe setups.

Armed with this electrical pulse source, the team turned to their magnetic test structures: trilayers of cobalt separated and sandwiched with platinum, a configuration in which the two cobalt layers are antiferromagnetically coupled through the platinum spacer. This symmetry is not incidental. Field-free switching, meaning deterministic reversal of perpendicular magnetization without the aid of an external magnetic field, has been a long-standing goal in the SOT community, because an external field would be impractical to supply in a dense memory array. Earlier work from the same group and others had shown that synthetic antiferromagnetic trilayers can achieve field-free switching at sub-nanosecond timescales; the new study pushes that capability into the picosecond domain using a fully integrated electrical source.

The headline result is a sweeping energy comparison. When the researchers varied the pulse width from 100 microseconds all the way down to 6.4 picoseconds, they found that the energy required to switch the magnetization fell by four orders of magnitude. In other words, writing the same magnetic bit with a picosecond pulse costs roughly ten thousand times less energy than writing it with the microsecond pulses that have been standard in laboratory demonstrations. For an industry in which data-center memory power consumption is a growing fraction of global electricity use, a four-decade reduction in per-bit write energy is the kind of number that translates directly into real-world impact.

Perhaps the most intriguing part of the study is the physical explanation the authors offer for why the picosecond regime is so efficient. Naively, one might expect that a shorter pulse delivers less total torque and therefore makes switching harder, not easier. The team found instead that ultrafast Joule heating plays a constructive role: the intense, brief current pulse transiently heats the magnetic layer, lowering the energy barrier that the magnetization must overcome to reverse. This thermally assisted switching mechanism, the authors argue, contributes significantly to the enhanced efficiency observed in the picosecond regime. The idea echoes concepts from heat-assisted magnetic recording, where a laser briefly softens a recording medium before writing, but here the heating is delivered electrically, on the same timescale as the write operation itself, and confined to the immediate vicinity of the bit.

The researchers verified the switching behavior using magneto-optical Kerr effect (MOKE) microscopy, which images the out-of-plane magnetization of the devices before and after pulse application, confirming deterministic reversal under the 6.4-picosecond pulses. They also extended their analysis to ferrimagnetic films, examining how the critical current density and switching energy depend on pulse width across both ferro- and ferrimagnetic systems, a comparison that matters because compensated ferrimagnets are among the most promising materials for ultrafast, thermally robust spintronic memory.

The broader implications reach beyond a single memory technology. An on-chip source of picosecond, high-voltage electrical pulses is a tool, not just a component: the same generator that writes magnetic bits could, in principle, drive ultrafast electronics experiments, terahertz-scale signal generation, or other spintronic operations that have historically been gated by access to laser facilities. Because the nanoplasma switch builds on prior demonstrations of nanoplasma-enabled picosecond switching for ultrafast electronics, the work also signals a convergence between two previously separate research communities, high-speed electrical engineering and magnetism, that now share a common enabling device.

Challenges remain before such pulse generators appear inside commercial MRAM products. The discharge-based approach must prove its endurance over billions of write cycles, its uniformity across millions of cells on a wafer, and its compatibility with the back-end-of-line thermal budgets of CMOS manufacturing. The peak voltages involved, while modest in absolute terms, will need careful management in dense circuit environments. Still, the demonstration marks a conceptual milestone: picosecond spin–orbit torque switching, once the exclusive province of optics laboratories, can now be triggered by nothing more exotic than a voltage applied to a patterned on-chip structure. If the endurance and scalability questions can be answered, the all-electric nanoplasma pulse generator may well become the write engine of a new generation of memory, one that flips its bits in trillionths of a second while sipping, rather than gulping, energy.

Subject of Research: An all-electric on-chip nanoplasma pulse generator enabling picosecond field-free spin–orbit torque switching in magnetic heterostructures

Article Title: An all-electric on-chip nanoplasma pulse generator for picosecond field-free spin–orbit torque switching in magnetic heterostructures

Article References: Chen, X., Zhao, S., Pu, Y., Yang, Q., & Yang, H. (2026). An all-electric on-chip nanoplasma pulse generator for picosecond field-free spin–orbit torque switching in magnetic heterostructures. Nature Electronics. https://doi.org/10.1038/s41928-026-01699-w

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01699-w

Keywords: spin–orbit torque, nanoplasma, picosecond pulses, MRAM, magnetization switching, magnetic heterostructures, field-free switching, Joule heating, spintronics, Nature Electronics, energy-efficient memory, cobalt platinum trilayers