The research, led by Chien-Chih Tseng, Chang-Hsun Huang and Jui-Cheng Kao under the direction of Vincent Tung at the University of Tokyo, together with collaborators across Taiwan and Japan, reports the epitaxial growth of monolayer boron carbon nitride (BCN) with a field-effect hole mobility of 100 square centimeters per volt-second. Transistors built from the material switch with an on-off ratio of 10 to the eighth power, deliver on-currents exceeding 0.9 milliamperes per micrometer, and operate at a threshold voltage of minus 0.45 volts. Those numbers, achieved across wafer-scale arrays rather than on isolated champion devices, surpass the performance of every p-type 2D semiconductor reported to date, according to the authors. The work was published on 30 September 2026 and represents a collaboration spanning the University of Tokyo, National Taiwan University, National Yang-Ming Chiao Tung University, Academia Sinica, the National Institute for Materials Science, and Chang Gung University.

The difficulty of making a good p-type 2D semiconductor is rooted in fundamental physics. In many atomically thin materials, the valence band states that transport holes are strongly localized around particular atomic orbitals, which makes holes scatter easily off defects and phonons. Many candidate materials also exhibit a natural tendency toward electron doping, so their surfaces accumulate unwanted negative charge that degrades hole transport. Compounding these intrinsic problems is a synthetic one: to be useful in a fab, a 2D semiconductor must be grown as a continuous, single-crystal film over an entire wafer, with uniform composition and no grain boundaries that would scatter carriers or cause device-to-device variability. Achieving that uniformity for a ternary compound, in which three different elements must arrive at the growing surface in exactly the right proportions, is far harder than growing a binary crystal such as hexagonal boron nitride.

The team’s central insight concerns a problem they describe as a spatial and temporal mismatch in the delivery of boron, carbon and nitrogen atoms. The standard precursor chemistry for boron nitride growth relies on ammonia borane, a molecule that decomposes when heated. When carbon-bearing precursors are added to the mix to make BCN, the different decomposition pathways of the constituent molecules release boron, carbon and nitrogen species at different times and in different ratios. The growing lattice therefore receives an uneven supply of atoms, producing composition fluctuations, defects and discontinuous crystallization that wreck the electronic quality of the film. Rather than accepting this mismatch, the researchers engineered it away by carefully controlling the dehydrogenation and surface reaction pathways of two related precursors: monomethyl ammonia borane and ammonia borane itself.

Monomethyl ammonia borane carries a methyl group that serves as a built-in carbon source, and by tuning the balance between the two precursors the team synchronized the release of all three elements so that they arrived at the substrate together. Density functional theory calculations, performed with the VASP code, mapped the reaction landscape and identified the decomposition intermediates that would either help or hinder uniform growth. The calculations guided the choice of growth conditions, ensuring that carbon atoms and carbon dimers incorporated into the lattice at the right moment rather than segregating into graphene-like domains. The result is a film in which carbon substitutes primarily for nitrogen sites within a continuously crystallized boron nitride lattice, with local distortions around the carbon atoms but no breakdown of long-range order.

Verifying that atomic structure demanded some of the most advanced microscopy available. Aowen Li, Ryo Ishikawa and Naoya Shibata at the University of Tokyo performed high-resolution scanning transmission electron microscopy on the monolayer film, resolving individual atomic columns and confirming that carbon atoms and carbon dimers occupy nitrogen sites throughout the lattice. Complementary multi-scale characterizations, including Raman spectroscopy, X-ray photoelectron spectroscopy, Kelvin probe force microscopy and scanning tunneling spectroscopy, established the film’s composition, work function and electronic structure across the wafer. The measurements converged on a bandgap of 1.90 electronvolts, a value comfortably above the thermal energy that causes leakage in transistors, and one that places BCN squarely in the regime useful for low-power logic.

The electrical characterization is where the work becomes genuinely striking. The team fabricated arrays of p-channel field-effect transistors across the wafer, using a 20-nanometer hafnium dioxide dielectric as the gate insulator. Because the devices were measured in large numbers rather than as cherry-picked specimens, the reported figures carry statistical weight. A hole mobility of 100 square centimeters per volt-second may sound modest compared with the thousands achieved in the best silicon devices, but for a monolayer p-type 2D semiconductor it is a benchmark-setting result, and the on-current above 0.9 milliamperes per micrometer demonstrates that the material can deliver the drive current that real circuits demand. The 10-to-the-eighth on-off ratio means the transistor switches cleanly between conducting and insulating states, and the near-zero threshold voltage of minus 0.45 volts indicates that gates of practical strength can turn the devices on and off efficiently.

The broader significance lies in what BCN enables for three-dimensional monolithic integration. As silicon scaling approaches its physical limits, chipmakers are exploring stacking active layers vertically, growing one layer of 2D transistors directly on top of another to multiply transistor density without shrinking lateral dimensions. That vision requires 2D semiconductors that can be grown at temperatures compatible with the layers beneath them, with wafer-scale uniformity and both carrier polarities available. Previous work has demonstrated growth-based monolithic integration of single-crystal 2D semiconductors and complementary 2D circuits built from separate materials, but a single, scalable p-type platform grown epitaxially across a wafer has been missing. BCN, grown from simple molecular precursors on a crystalline substrate, fits the requirements in a way that exfoliated flakes or transferred films never could.

There is also a pleasing historical symmetry in the result. Boron carbon nitride was first proposed as a graphite-like material in 1987, and researchers have synthesized B-C-N nanotubes and hybrid graphene-boron nitride domains since the 1990s. Carbon impurities in hexagonal boron nitride have even been identified as the source of single-photon emission, a reminder that the BCN system has long been studied at the boundaries of materials science. What distinguishes the new work is control: by solving the precursor chemistry rather than fighting it, the team converted a notoriously inhomogeneous alloy into a device-grade semiconductor. The DFT calculations, experimental growth, atomic-resolution imaging and device engineering were all executed within a single coordinated effort, a model of how modern materials discovery increasingly proceeds from first-principles prediction straight to wafer-scale demonstration.

Challenges remain before BCN transistors appear in commercial chips. The growth is epitaxial, meaning it relies on a crystalline substrate that templates the film’s orientation, and transferring large-area 2D films without introducing damage remains an unsolved industrial problem. Contact engineering, dielectric integration and long-term stability under bias and heat will all need further refinement. The authors declare no competing interests, and the data and calculation inputs are available from the corresponding authors, which should help other groups reproduce and extend the results. But the conceptual barrier has fallen: a p-type 2D semiconductor with wafer-scale uniformity, a useful bandgap and benchmark hole transport now exists. If the result replicates across laboratories, the missing half of the 2D CMOS palette may finally be in place, and the path toward atomically thin, vertically stacked logic circuits becomes considerably more concrete.

Subject of Research: Wafer-scale epitaxial growth of p-type boron carbon nitride for two-dimensional CMOS electronics

Article Title: Wafer-scale epitaxy growth of high-mobility p-type boron carbon nitride

Article References: Wafer-scale epitaxy growth of high-mobility p-type boron carbon nitride. (n.d.). https://doi.org/10.1038/s41586-026-11047-9

Image Credits: AI Generated

DOI: 10.1038/s41586-026-11047-9

Keywords: boron carbon nitride, two-dimensional materials, p-type semiconductor, field-effect transistors, CMOS technology, epitaxial growth, chemical vapor deposition, hole mobility, bandgap engineering, monolithic 3D integration, scanning transmission electron microscopy, density functional theory

Monolithic 3D integration differs from the chip-stacking approaches used in today’s advanced packaging. Instead of fabricating separate dies and bonding them together with relatively coarse interconnects, monolithic 3D integration builds successive device layers sequentially on the same wafer. Each new tier of transistors is grown and patterned directly on top of the interconnect stack of the tier below. This allows extremely dense vertical connections between logic and memory, dramatically shortening the distances data must travel and opening the door to computing architectures in which memory and processing are woven together in three dimensions. The obstacle has always been thermal budget: conventional silicon processing requires temperatures that would destroy the metal interconnects and devices already in place beneath a new layer, so any channel material added on top must be deposited and processed at low temperatures.

The Purdue team, led by Peide D. Ye of the Elmore Family School of Electrical and Computer Engineering, turned to indium oxide deposited by atomic layer deposition, a technique in which the semiconductor film grows one atomic layer at a time through self-limiting surface reactions. Atomic layer deposition offers exceptional thickness control and superb conformality across large substrates, and the resulting amorphous indium oxide films can be processed at temperatures well within the tolerance of back-end-of-line metallization. Because the films are amorphous rather than crystalline, they sidestep the grain-boundary and lattice-matching problems that plague many alternative low-temperature channel materials, including two-dimensional semiconductors that have attracted enormous attention for the same application.

The demonstration is remarkable for its breadth of device functionality. On the 200-millimeter wafers, the researchers fabricated three tiers of devices spanning ferroelectric field-effect transistors for non-volatile memory, as well as enhancement-mode and depletion-mode field-effect transistors for logic. Ferroelectric transistors hold their stored state without power, enhancement-mode devices switch off cleanly at zero gate voltage, and depletion-mode devices conduct by default, so together they form a complete transistor toolkit suitable for real circuit design. The electrical statistics across the wafers are equally notable. Threshold voltage standard deviations as low as 0.04 volts were achieved, a level of uniformity that rivals commercial silicon devices and indicates that the low-temperature process is genuinely manufacturable rather than a laboratory curiosity. Average electron mobilities reached up to 91.6 square centimeters per volt-second, high enough to support fast switching and strong drive currents in dense vertical layouts.

Uniformity at wafer scale is arguably the central achievement here. Research groups have previously shown promising oxide semiconductor transistors on small chip-scale samples, but moving to a 200-millimeter platform subjects every device to the same statistical scrutiny that foundry engineers apply to silicon. The team systematically characterized how processing variations, including annealing temperatures and capping steps, affected each device family. They found that a surface-capping layer followed by a 300-degree-Celsius anneal substantially improved bias stability, suppressing the threshold voltage drift that can undermine reliability during sustained operation. Statistical distributions of subthreshold swing, threshold voltage, and memory window remained tight across hundreds of measured devices per condition, with sample sizes running into the hundreds for each device type tested.

Thermal robustness was verified layer by layer. Because each tier of devices must survive the processing of the tiers fabricated above it, the researchers subjected finished transistors to the full thermal sequence and re-measured them. Mobility, threshold voltage, and subthreshold characteristics were preserved with negligible shift after the complete stack processing, confirming that indium oxide can endure the cumulative thermal exposure of a multi-tier build. The team also engineered the channel thickness to select device behavior: thinner films of about 1.5 nanometers yielded enhancement-mode operation, while thicker films near 3.0 nanometers produced depletion-mode devices, giving circuit designers the complementary options they need for power-efficient logic within the same material system.

With three functional tiers established, the researchers went beyond device statistics and demonstrated fully functional cross-tier circuits, in which signals travel vertically through inter-tier vias connecting transistors on different layers. This vertical wiring capability is what transforms stacked transistors from a density trick into a genuine architectural opportunity. Logic and memory separated by microns of horizontal wiring in a conventional planar chip can instead sit directly atop one another, connected by short vertical links. The team used a custom process design kit built around compact models of their indium oxide transistors, including a standard cell library of eleven logic gates verified through D flip-flop simulations, to bridge the gap between measured device behavior and large-scale circuit design.

The system-level payoff was quantified in the design of a four-tier 3D computing-in-memory accelerator targeting large-language-model workloads. Computing-in-memory architectures perform matrix operations directly inside memory arrays, sidestepping the energy cost of shuttling data between separate memory and processor units, a bottleneck that dominates the power budget of modern artificial intelligence systems. By vertically interleaving logic and memory tiers made from the same low-temperature oxide platform, the proposed accelerator exploits the short inter-tier connections that monolithic integration uniquely enables. Benchmark simulations showed speed-ups of 1.4 times to 2.9 times over comparable two-dimensional baselines, together with comparable improvements in energy-delay product, a metric that captures both how fast a workload completes and how much energy it consumes.

The significance for the semiconductor industry lies in the convergence of manufacturability and application pull. Data centers running large language models are straining power grids, and the energy cost of moving data between memory and logic has become the defining constraint of AI hardware. A low-temperature, wafer-scale, CMOS-compatible platform for stacking logic and memory in three dimensions offers a way to attack that constraint directly, without abandoning the existing silicon infrastructure. Because the entire integration happens on standard 200-millimeter wafers using back-end-of-line-compatible processing, the approach could in principle be adopted as an additional module within existing foundry flows rather than requiring a wholesale reinvention of the fabrication plant.

Challenges remain before such stacks reach commercial products. The accelerator results reported here come from design and simulation benchmarked against the measured device data rather than from a fully fabricated four-tier chip, and scaling the demonstrated three-tier integration to four or more tiers will demand continued control of yield and variability across the stack. Nevertheless, the demonstration answers the question that has lingered over monolithic 3D integration for years: whether any low-temperature channel material can deliver both the electrical performance and the wafer-scale uniformity that real manufacturing requires. With atomic-layer-deposited indium oxide now shown to do so on an industry-standard substrate, the vertical dimension of computing has moved from concept toward the fabrication line.

Subject of Research: Monolithic 3D integration of atomic-layer-deposited indium oxide semiconductor devices on 200-mm silicon wafers for vertically stacked logic and memory in AI hardware

Article Title: Monolithic 3D integration of atomic-layer-deposited oxide semiconductors on 200-mm silicon wafers

Article References: Niu, C., Long, L., Zheng, L., Du, S., Lin, J.-Y., Nam, K., Lin, Z., Liu, C., Lu, J., Wang, H., Li, H., & Ye, P. D. (2026). Monolithic 3D integration of atomic-layer-deposited oxide semiconductors on 200-mm silicon wafers. Nature Nanotechnology. https://doi.org/10.1038/s41565-026-02276-0

Image Credits: AI Generated

DOI: 10.1038/s41565-026-02276-0

Keywords: monolithic 3D integration, indium oxide semiconductor, atomic layer deposition, 200-mm wafer, back-end-of-line processing, ferroelectric field-effect transistor, computing-in-memory, AI accelerator, large language models, CMOS compatibility, threshold voltage uniformity, three-dimensional chip stacking