Recent breakthroughs have turned the spotlight onto metallic two-dimensional (2D) materials, known for their atomically flat surfaces and compatibility with low-temperature processing techniques. These attributes make them ideal candidates for forming contacts with delicate monolayer semiconductors. While such contacts have been successfully implemented in n-type TMD-based transistors, extending this success to p-type devices has proven elusive. The primary roadblock has been WSe₂’s relatively large bandgap, which complicates the realization of high-performance p-type transistors.

Groundbreaking new research now demonstrates a compelling solution—using metallic layered Nb₀.₃W₀.₇Se₂ as a contact material for monolayer and bilayer WSe₂ field-effect transistors (FETs). This multidimensional approach leverages the inherent advantages of layered 2D metals, promoting seamless, low-resistance interfaces with p-type WSe₂ channels. The study reveals that these 2D–2D contacts enable transistor channel lengths down to 100 nm, marking a major stride toward the miniaturization necessary for modern integrated circuits.

A profound achievement of this research lies in the exceptional on-current densities attained. For monolayer WSe₂ transistors utilizing Nb₀.₃W₀.₇Se₂ contacts, on-current densities reach an impressive 358 µA µm⁻¹. Even more striking are the results for bilayer WSe₂ channels, which demonstrate on-current densities soaring to 1.1 mA µm⁻¹. These figures represent considerable enhancements over previous p-type devices, signalling the potential for these materials to unlock new paradigms in low-power, high-efficiency electronics.

The use of Nb₀.₃W₀.₇Se₂ as a contact metal also addresses one of the trickiest technical challenges in transistor fabrication—the formation of a high-quality, low-barrier interface without damaging the sensitive monolayer channel. Conventional metal deposition often necessitates elevated temperatures, which can introduce undesirable defects and strain. In contrast, the layered vdW metallic contacts employed here can be deposited at substantially lower temperatures, preserving the pristine nature of the 2D semiconductor surface and maintaining the integrity of electrical transport pathways.

Another technical milestone achieved in these devices is the integration of scaled gate dielectrics with an effective oxide thickness (EOT) of just 1.3 nm. Such aggressive gate scaling is essential for controlling the electrostatic environment around the transistor channel, thereby suppressing leakage currents and achieving steep subthreshold slopes. The resulting monolayer WSe₂ transistors boast a subthreshold swing as low as 88 mV dec⁻¹, underscoring the finely tuned interface properties and excellent gate control obtained through this innovative design.

This work also highlights the strategic advantage of using metallic Nb₀.₃W₀.₇Se₂ over traditional metal contacts. The unique chemical and electronic properties of this material facilitate a better energy level alignment with p-type WSe₂, reducing Schottky barrier heights, and enabling more efficient hole injection. This aspect is particularly vital in overcoming the intrinsic limitations posed by large bandgap semiconductors that typically suffer from high contact resistance when paired with conventional metals.

In addition to electrical characterization, the study provides compelling insights into the structural compatibility between Nb₀.₃W₀.₇Se₂ and WSe₂ layers. Atomic-level investigations confirm the formation of atomically sharp interfaces devoid of interfacial disorder or contamination that could degrade device performance. The layered nature of both materials ensures lattice matching and eliminates dangling bonds traditionally present in bulk semiconductor–metal interfaces, a common cause of electronic traps and scattering centers.

From an application perspective, the implications of these findings are enormous. The enhanced current densities and reduced contact resistance herald the possibility of fabricating ultrafast, energy-efficient p-type transistors which have long been the bottleneck in complementary metal-oxide-semiconductor (CMOS) technology scaling efforts. Moreover, the low thermal budget of the contact fabrication process paves the way for integrating these devices onto flexible and temperature-sensitive substrates, broadening their utility in wearable electronics and advanced sensor networks.

The approach also opens new avenues for exploring other metallic layered compounds as contact materials across a broader family of 2D semiconductors. By tuning composition and structural parameters, it may be possible to engineer a versatile suite of contact materials optimized for both n-type and p-type conduction across various TMDs. This modularity accelerates the path toward fully 2D-integrated circuits with unprecedented performance metrics and device densities.

Furthermore, this technology is poised to influence the ongoing shift towards heterogeneous material integration, where different 2D layers perform designated functions within a single compact device architecture. By employing all-2D materials for both channel and contacts, researchers can exploit unique electrical, mechanical, and optical properties intrinsic to atomically thin layers while avoiding the complications caused by bulky 3D metal contacts.

The achievement is also a testament to exceptional material synthesis and engineering capabilities. Precisely controlling the stoichiometry and uniformity of Nb₀.₃W₀.₇Se₂ layers is critical for reproducibility and device consistency. Advanced chemical vapor deposition and exfoliation methods have played pivotal roles, showcasing the interplay between materials science and device engineering in realizing functional pico- to nanometer scale electronics.

Looking ahead, the robustness of these 2D–2D contacts under various environmental conditions and operational stresses will be a subject of intense study. Stability against oxidation, thermal cycling, and electrical stress is essential to transition from lab-scale prototypes to commercial device platforms. Early indications suggest excellent mechanical and chemical stability, promising a pathway for durable and scalable technology.

This pioneering research not only bolsters the fundamental understanding of metal–semiconductor interfaces at the atomic scale but also represents a critical step toward fully exploiting the remarkable properties of 2D TMDs in practical applications. By surmounting the longstanding difficulty of creating low-resistance p-type contacts in monolayer WSe₂, the field moves significantly closer to realizing ultrathin, flexible, and highly efficient electronic devices that could revolutionize consumer electronics, computing, and sensing technologies.

In conclusion, the use of metallic layered Nb₀.₃W₀.₇Se₂ contacts in p-type WSe₂ field-effect transistors exemplifies a creative and effective materials engineering strategy to overcome one of the key hurdles in 2D semiconductor technology. The synergistic combination of low contact resistance, high on-current densities, and ultra-thin gate dielectrics positions these devices as frontrunners in next-generation electronic platforms. This advancement marks a seminal development in semiconductor device engineering, with profound implications for the future of nanoelectronics and beyond.

Subject of Research:
Low-resistance contacts in p-type monolayer tungsten diselenide (WSe₂) transistors using metallic layered Nb₀.₃W₀.₇Se₂.

Article Title:
Low-resistance contacts for p-type monolayer tungsten diselenide transistors using metallic layered Nb₀.₃W₀.₇Se₂.

Article References:
Sun, Z., Afzalian, A., Wu, P. et al. Low-resistance contacts for p-type monolayer tungsten diselenide transistors using metallic layered Nb₀.₃W₀.₇Se₂. Nat Electron (2026). https://doi.org/10.1038/s41928-026-01568-6

Image Credits: AI Generated

DOI: https://doi.org/10.1038/s41928-026-01568-6

The synthesis of monolayer MoS₂ begins with the meticulous preparation of the precursors. In this instance, molybdenum trioxide (MoO₃) and sulfur serve as the primary components, facilitating the growth of MoS₂ during the CVD process. The researchers executed this step by distributing a precisely measured amount of MoO₃ powder within an alumina boat, strategically positioned at the center of a single-zone tube furnace. Complementing this setup was a SiO₂ substrate, which was treated with a sodium hydroxide (NaOH) promoter to enhance the growth process. The controlled environment further included the placement of sulfur powder in a separate alumina boat, carefully positioned 17 centimeters upstream, optimizing the reaction dynamics during synthesis.

Prior to initiating the growth phase, the tube furnace underwent a purging process to remove any impurities or contaminants. Here, nitrogen gas was introduced at a flow rate of 460 standard cubic centimeters per minute (s.c.c.m.) while the furnace was heated to a temperature of 150°C. Once the environment was purged, the nitrogen flow rate was reduced, establishing an ideal backdrop for the growth of MoS₂. The MoO₃ source was subsequently heated to an impressive 720°C, a critical temperature that allows the synthesis reactions to take place efficiently. Meanwhile, sulfur stabilized at a temperature of around 230°C, ensuring that the reaction remained active yet controlled, thus yielding high-quality monolayer MoS₂.

Upon completion of the growth phase, careful attention was paid to cooling the tube back down. To maintain the integrity of the synthesized material, the sulfur source was withdrawn from the heating zone, and the nitrogen gas flow was resumed at 460 s.c.c.m. This cooling protocol was instrumental in preserving the structural characteristics of MoS₂. For the transfer of this material to target substrates, the researchers employed a polydimethylsiloxane (PDMS) dry transfer technique. This method is crucial for ensuring the integrity of the material as it transitions from one substrate to another, marking a significant step in its practical deployment.

In addition to the monolayer MoS₂, the researchers also explored the characteristics of few-layered MoS₂ and tungsten diselenide (WSe₂) samples, which were obtained through mechanical exfoliation from bulk crystals. This process utilized the blue tape method, known for its simplicity and effectiveness in producing high-quality few-layer materials. The substrates designated for these transferred materials mirrored those used for the CVD-grown samples, thereby ensuring consistency across the experimental components.

The substrates themselves played a critical role in the overall study. The research team utilized boron degenerately doped silicon substrates, which were further enhanced with layers of thermally grown SiO₂, atomic-layer-deposition-grown hafnium oxide (HfO₂), and zirconium oxide (ZrO₂). Each of these dielectric materials presented unique electrical and structural properties essential for the successful integration of MoS₂ within electronic devices. Understanding the deposition conditions and characterizations of these dielectrics remains paramount, as they influence the performance and efficiency of the overall devices.

Moreover, to investigate the electronic properties and interface characteristics of the materials, soft and hard X-ray photoelectron spectroscopy (XPS) measurements were conducted. Utilizing the advanced capabilities at beamline I09 at the Diamond Light Source in the UK, the researchers collected detailed spectral information. This data enabled them to determine the elemental composition and electronic states present within the MoS₂ samples. Notably, the high-energy analyzer employed demonstrated precision, capturing spectra that were crucial for confirming the absence of sample charging and beam damage, thereby ensuring the reliability of their results.

The binding energy scale utilized during these measurements was calibrated against the gold 4f core level, lending credibility to the data acquired. A meticulous approach was taken, which included repeated acquisitions to substantiate the findings. This careful consideration of experimental conditions signifies the researchers’ commitment to achieving high-quality results, demonstrating best practices in the synthesis and characterization of 2D materials.

The theoretical framework underpinning this research involved first-principles density functional theory (DFT) calculations. Utilizing the QuantumATK package, researchers applied the hybrid functional of Heyd-Scuseria-Ernzerhof (HSE06) to understand the electronic interactions at the MoS₂/dielectric interfaces. The study focused on various interface models, including those involving HfO₂ and ZrO₂, enabling a comprehensive investigation into their potential as substrates for MoS₂ applications. The DFT calculations supported the experimental findings, corroborating the ideal lattice parameters and structural properties of the materials.

In constructing the interface models, researchers deployed supercell strategies to capture the nuances of the interactions between the 2D TMDs and the dielectric layers. Multiple configurations were tested to optimize the alignment of the lattices, ensuring minimal strain and maximizing the quality of the heterojunctions. The results of these calculations revealed vital insights into the nature of the interactions occurring at the interfaces, highlighting the significance of van der Waals forces in stabilizing the heterostructures.

More practically, the electrical measurements of the synthesized materials were conducted using a Keithley 4200 current-voltage system. The intricate characterization allowed for the assessment of material performance under various conditions, reflecting their potential for real-world applications. Furthermore, photoluminescence (PL) and Raman spectroscopy data collected using a focused laser revealed critical vibrational modes and electronic transitions within the MoS₂ layers, indicating their viability for optoelectronic devices.

In addressing the physical topography of the samples, Atomic Force Microscopy (AFM) data imagery was captured to reveal surface characteristics and layer thicknesses. Employing the Dimension Icon device in peak-force tapping mode provided insights into nanoscale features critical for device engineering. The culmination of these efforts has positioned this research at the forefront of material science, facilitating the design of cutting-edge electronic devices that may redefine industry standards.

Through meticulous research and breakthrough techniques in synthesis and characterization, this work lays the groundwork for understanding and leveraging the attributes of monolayer and few-layer MoS₂ in contemporary technology. The advancement of 2D materials not only emphasizes their unique electronic and optical properties but also enriches the realm of nanoscale engineering, heralding a promising future for advanced electronic devices.

Subject of Research: Synthesis and characterization of monolayer MoS₂ and few-layer TMDs for advanced electronic applications.

Article Title: A clean van der Waals interface between the high-k dielectric zirconium oxide and two-dimensional molybdenum disulfide.

Article References: Yan, H., Wang, Y., Li, Y. et al. A clean van der Waals interface between the high-k dielectric zirconium oxide and two-dimensional molybdenum disulfide.
Nat Electron (2025). https://doi.org/10.1038/s41928-025-01468-1

Image Credits: AI Generated

DOI: 10.1038/s41928-025-01468-1

Keywords: MoS₂, two-dimensional materials, van der Waals interfaces, CVD, XPS, DFT, semiconductor applications.