The central innovation lies in the transistor itself. Molybdenum disulfide, a two-dimensional semiconducting material just a few atoms thick, forms the conducting channel of the device. Because the material is so thin, its electronic properties can be controlled with exceptional precision by electric fields applied from above and below. The researchers exploited this by constructing a dual-gate architecture: one gate tunes the channel’s conductivity in the conventional manner, while the second gate is made of a ferroelectric material whose polarization state can be flipped and retained without continuous power. This ferroelectric layer effectively gives the transistor a form of nonvolatile memory, allowing it to remember its configuration even when the device is switched off.

That combination of tunability and memory is what enables the reconfigurability at the heart of the new architecture. By adjusting the voltages applied to the two gates, the researchers can steer a single transistor between fundamentally different modes of operation. In one configuration, the device behaves as a spiking neuron, integrating incoming electrical pulses and firing an output spike only when the accumulated input crosses a threshold, mirroring the leaky integrate-and-fire dynamics of biological neurons. In another configuration, the same physical device operates as a logic transistor within a standard digital circuit, performing the deterministic switching operations on which conventional computing relies. No rewiring, no fabrication changes, and no additional components are needed to move between these modes; only gate voltages change.

Spiking neural networks represent a fundamentally different approach to computation compared with the artificial neural networks that dominate today’s AI landscape. Rather than exchanging continuous numerical values, spiking networks communicate through discrete electrical pulses, or spikes, much like the neurons in a biological brain. Information is encoded in the timing and frequency of these spikes, which allows the network to remain largely idle between events and consume power only when meaningful signals arrive. This event-driven behavior is the reason the human brain, running on roughly twenty watts, can outperform supercomputers on many perceptual tasks. Hardware that natively supports spiking dynamics could therefore deliver dramatic improvements in energy efficiency, particularly for edge applications such as wearable sensors, medical implants, and autonomous systems where power budgets are unforgiving.

Until now, building spiking hardware has typically required dedicated devices such as memristors, phase-change memory cells, or specialized neuron circuits, each fabricated separately from the logic elements of the surrounding system. That separation imposes penalties in chip area, fabrication complexity, and the energy cost of moving signals between distinct regions of a circuit. The new work collapses that distinction. Because every transistor in the architecture is potentially reconfigurable, a chip could dynamically allocate its resources, dedicating more of its fabric to spiking computation during sensory processing tasks and reprogramming sections for deterministic logic when precise arithmetic is required. This fluid boundary between neural and digital operation is what the researchers describe as a neural-network-in-logic architecture.

The ferroelectric gating mechanism deserves particular attention for what it implies about energy efficiency. Conventional transistor-based neuron circuits often need capacitors or feedback loops to accumulate charge and emulate neuronal integration, and they lose their state when power is removed. A ferroelectric gate, by contrast, stores its polarization intrinsically. In the spiking mode, the ferroelectric layer can integrate the effect of repeated input pulses by gradually shifting its polarization, acting as an intrinsic memory of recent activity. The result is a neuron whose history is physically encoded in the material itself, reducing the overhead associated with maintaining state and enabling genuinely event-driven operation. Because molybdenum disulfide channels are atomically thin, the electrostatic coupling between the ferroelectric polarization and the channel is unusually strong, which the researchers identify as essential to achieving reliable switching behavior at practical operating voltages.

Molybdenum disulfide has emerged as one of the most promising two-dimensional semiconductors for post-silicon electronics. Unlike graphene, which lacks a natural band gap, molybdenum disulfide is a semiconductor with favorable transport properties even in monolayer form. Its inert, dangling-bond-free surface means that interfaces with gate dielectrics are remarkably clean, reducing the scattering and variability that plague conventional scaled transistors. These properties have made it a favorite candidate for ultimately scaled electronics, and the new study demonstrates that the same material platform can serve functions far beyond simple switching. The combination of a two-dimensional channel with a ferroelectric gate effectively unites two of the most active research directions in device engineering into a single, multifunctional structure.

The demonstration of logic functionality alongside spiking behavior is more than a technical curiosity. Real-world intelligent systems rarely consist of neural computation alone; they require interfacing with digital peripherals, preprocessing data, and executing control decisions that demand exact, repeatable outcomes. A processor that can host both computational styles on a shared, reconfigurable fabric could avoid the energy and latency costs of shuttling data between separate neural and digital dies. The researchers show that individual transistors and small circuits built from them can be toggled between spiking and logic roles and reprogrammed repeatedly, establishing the foundation for architectures in which the boundary between inference and computation is drawn in software rather than silicon.

Significant engineering challenges remain before such devices could appear in commercial products. Ferroelectric materials integrated with two-dimensional semiconductors are still maturing, and questions of endurance, uniformity across large wafers, and long-term stability will need to be answered at scale. Fabricating high-quality molybdenum disulfide over the large areas required for industrial manufacturing remains an active area of research, although recent progress in wafer-scale growth of two-dimensional materials suggests the obstacle is one of engineering refinement rather than fundamental physics. The operating characteristics of the spiking elements, including threshold variability and response speed, will also need to be characterized and optimized for large networks.

Nevertheless, the significance of the demonstration is difficult to overstate. The semiconductor industry has spent decades pursuing ever finer transistors, but the diminishing returns of miniaturization have pushed researchers toward devices that do more with each switching element. A transistor that can remember, spike, and compute, reconfigurable on demand, represents exactly the kind of functional diversification that next-generation computing may require. If the reconfigurable molybdenum disulfide dual-gate architecture can be scaled to arrays of thousands or millions of devices, it could pave the way toward chips that learn, adapt, and compute within a single unified fabric, blurring the line between the machines we program and the brains that inspire them. For now, the work stands as a striking proof of concept that the boundary between neural and conventional computing can be drawn, and redrawn, atom by atom.

Subject of Research: Reconfigurable molybdenum disulfide dual-gate transistors with ferroelectric gating for spiking neural network-in-logic hardware architectures

Article Title: A spiking neural network-in-logic architecture based on reconfigurable molybdenum disulfide dual-gate transistors with ferroelectric gating

Article References: Li, L., Zheng, H., Li, C., Xiang, H., Wang, J., Zheng, F., Chen, M., Chien, Y.-C., Gao, J., Huo, J., Chi, D., Fong, X., Wan, Y., Meng, W., Li, L.-J., & Ang, K.-W. (2026). A spiking neural network-in-logic architecture based on reconfigurable molybdenum disulfide dual-gate transistors with ferroelectric gating. Nature Electronics. https://doi.org/10.1038/s41928-026-01706-0

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01706-0

Keywords: spiking neural networks, molybdenum disulfide, ferroelectric gating, dual-gate transistors, neuromorphic computing, two-dimensional materials, reconfigurable logic, Nature Electronics, energy-efficient computing, post-silicon electronics, neural-network-in-logic, nonvolatile memory

The underlying problem is well known to memory engineers. Crossbar arrays, in which memory elements sit at the intersections of perpendicular word lines and bit lines, offer the most compact possible memory layout and can be stacked in three dimensions. But in a passive crossbar without a selector, current sneaks through neighboring unselected cells along paths known as sneak currents, corrupting the readout of the intended cell. Selectors are two-terminal devices placed in series with each memory element—forming one-selector-one-resistor or one-selector-one-capacitor cells—to suppress these parasitic currents. An ideal selector must be extremely nonlinear, passing large current only at its selected operating voltage while blocking current at half or a fraction of that voltage, yet it must also survive trillions of switching cycles, respond in nanoseconds, remain stable across temperatures and operate identically from device to device. No single selector technology has satisfied all of these requirements simultaneously.

The USC-led team’s answer is a graded tunnel barrier realized entirely within a van der Waals heterostructure. Instead of a single uniform insulating barrier, the device stacks materials of different band alignments so that the effective barrier profile changes with applied voltage. At low voltages, the barrier remains thick and high, strangling leakage current to negligible levels. As the voltage across the device rises toward the read or write condition, the barrier is thinned and lowered in a controlled fashion, allowing electrons to tunnel through with high efficiency. The result is an exponential increase in current over a small voltage window—precisely the nonlinearity that crossbar selectors demand.

To move beyond trial and error, the researchers developed a theoretical model that predicts the electrical characteristics of selectors with graded tunnel barriers. Guided by this model, they designed and fabricated two specific device structures. In the first, the primary tunnel barrier is hexagonal boron nitride, the wide-bandgap insulator often called white graphene. In the second, the barrier is gallium sulfide, a layered semiconductor with a smaller bandgap. Both variants sandwich the barrier between two layers of molybdenum disulfide, with graphene sheets serving as the top and bottom electrodes, forming the complete five-layer stack graphene/molybdenum disulfide/barrier/molybdenum disulfide/graphene.

The performance of the hexagonal boron nitride device is striking. It exhibits a nonlinearity exceeding 10 million, meaning the current at the operating voltage is more than ten million times larger than the leakage current at reduced voltages—among the highest values reported for any two-terminal selector. Perhaps more impressive is its endurance: the device survived more than a trillion switching cycles without failure, a figure that dwarfs the lifetimes of many competing selector technologies and approaches what commercial memory products require. Switching occurs in less than 20 nanoseconds, the current-voltage characteristics show minimal temperature dependence, and the variation from one device to another is low—critical attributes for manufacturing, where billions of cells must behave nearly identically.

The gallium sulfide variant trades some nonlinearity for a dramatically reduced operating voltage. Because gallium sulfide has a smaller barrier height than hexagonal boron nitride, the device can deliver a nonlinearity above one million while operating at only 2.5 volts. Low-voltage operation matters enormously for modern memory, which must integrate with silicon circuitry whose supply voltages continue to shrink. A selector that requires high voltages to turn on forces the surrounding periphery circuitry to handle elevated stress; a selector that switches at 2.5 volts eases that burden and reduces overall energy consumption during write operations.

Beyond single devices, the team demonstrated that their selectors can be integrated into functional memory cells. They built one-selector-one-resistor cells by pairing the selectors with memristive devices, including a hafnium-oxide-based memristor stack with palladium electrodes, and they also demonstrated one-selector-one-capacitor configurations. This dual compatibility with both resistive nonvolatile memory and capacitive volatile memory suggests the selector technology is genuinely universal, applicable across different memory families rather than tied to a single cell type. The researchers benchmarked their devices against the broad landscape of existing selector technologies—including ovonic threshold switching chalcogenides, niobium oxide threshold devices, metal-insulator-metal tunnel diodes and mixed-ionic-electronic-conduction access devices—and found that the van der Waals approach uniquely combines high selectivity with trillion-cycle endurance, nanosecond speed, temperature stability and low variability.

Choosing van der Waals materials is central to the achievement. These layered crystals are held together by weak interlayer forces, so each atomic plane can be exfoliated and restacked like molecular building blocks without the dangling bonds and interfacial defects that plague conventional three-dimensional semiconductors. Atomically sharp interfaces mean the tunnel barrier thickness is controlled layer by layer, giving designers reproducible, deterministic barrier profiles. Graphene electrodes contribute their own advantages, providing chemically inert, highly conductive contacts that do not interdiffuse with the underlying layers. The same properties that have made van der Waals heterostructures a playground for condensed matter physics here translate directly into manufacturable device metrics: negligible cycling variation, minimal temperature dependence and good interdevice uniformity all flow from the crystalline perfection of the interfaces.

The implications extend toward the long-sought goal of three-dimensional memory stacking. Because the entire selector is built from vertically stacked two-dimensional layers, it is inherently stackable, unlike selectors that rely on complex oxide growth or electroforming processes that are difficult to repeat layer upon layer. Paired with scalable nonvolatile memories such as memristors and phase-change or resistive cells, these selectors could enable dense three-dimensional crossbar memories for storage-class memory, in-memory computing and neuromorphic artificial intelligence hardware, where analog crossbar arrays perform vector-matrix multiplications directly in hardware. The research team, whose work was supported by the Army Research Office, the Air Force Office of Scientific Research and the National Science Foundation, has also released the experimental and simulation data through the Harvard Dataverse, giving the broader community the tools to build on the design framework. As the demand for data storage and energy-efficient computation continues its relentless climb, devices that tame sneak currents with atomic precision may prove to be one of the quiet enablers of the next memory generation.

Subject of Research: Van der Waals tunnel-junction selector devices with graded tunnel barriers for high-density memory crossbar arrays

Article Title: High-performance tunnel-junction selectors with graded tunnel barriers based on five-layer van der Waals heterostructures

Article References: High-performance tunnel-junction selectors with graded tunnel barriers based on five-layer van der Waals heterostructures. (n.d.). https://doi.org/10.1038/s41928-026-01704-2

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01704-2

Keywords: van der Waals heterostructures, tunnel-junction selector, memory crossbar arrays, molybdenum disulfide, hexagonal boron nitride, gallium sulfide, memristors, nonlinearity, endurance, three-dimensional memory, nanoelectronics, Nature Electronics

The new work, published in Nature Sensors, centers on a heterostructure formed from antimony telluride and molybdenum disulfide, two layered materials that can be stacked together with atomic precision. The resulting two-terminal device is deceptively simple in appearance: two electrodes, a vertical stack of semiconductors, and nothing else. Yet when the researchers applied a low bias voltage across the terminals, they discovered that the device could be toggled, reversibly and in situ, between two fundamentally different optoelectronic operating modes. In one mode it behaves as a photodiode, generating a current that scales faithfully and linearly with the intensity of incident light, exactly what is needed for conventional image sensing. In the other mode it behaves as an opto-synaptic element, in which light triggers a response that persists, decays, and accumulates over time, mirroring the way a biological synapse integrates incoming spikes before deciding whether to pass a signal onward.

The significance of this switchability is difficult to overstate. In existing optoelectronic computing arrays, each pixel is typically hardwired to a single function. If a designer wants an array that can both sense images and perform synaptic computation, the usual approach is to build separate hardware for each task, multiplying device count, fabrication complexity, and cost. The new sensor sidesteps this trade-off entirely. Because a single pixel can be reconfigured between photodiode and opto-synaptic modes simply by adjusting the applied bias voltage, the same physical array can act as a classical image sensor at one moment and a neuromorphic processing fabric the next. Functional diversity, the researchers argue, no longer has to be purchased at the price of integration scale. The array can grow, and its capabilities can grow with it.

The physics underlying this multi-responsiveness lies in the band alignment between the two constituent materials. Antimony telluride and molybdenum disulfide form a junction whose potential barrier can be modulated by the external bias. At certain bias conditions, photoexcited carriers are swept across the junction in a drift-dominated regime, producing the fast, linear, reset-every-frame response characteristic of a photodiode. Shift the bias, and the transport regime changes: charge generated by light becomes trapped and released slowly at interfacial states, so each optical pulse leaves behind a lingering conductance change that fades over time. It is precisely this fading memory that allows the device to emulate synaptic behavior, with the weight of the “synapse” effectively set by the recent history of illumination.

Perhaps the most striking demonstration in the study is the device’s ability to reproduce the leaky integrate-and-fire dynamics of biological neurons, the canonical model of how real neurons accumulate inputs and spike when a threshold is crossed. When the researchers illuminated the sensor with focused light pulses, the device’s internal state integrated the successive pulses, but also “leaked,” losing accumulated charge between pulses. Once the integrated response reached a threshold, the device fired, producing a discrete output event before resetting. This is not a software simulation of a neuron running on conventional hardware; it is a physical two-terminal device exhibiting the intrinsic dynamics of a neuron in response to light alone. Such light-driven leaky integrate-and-fire behavior is a cornerstone capability for spiking neural networks, a class of computing systems prized for their extreme energy efficiency because they only transmit information when events occur, rather than continuously.

To show that these single-device behaviors could scale into a usable computing system, the team integrated an array of the sensors with diffractive optical components, passive optical elements that shape and route light by diffraction rather than refraction. This combination enabled what the researchers describe as multi-mode optoelectronic computing. In one configuration, the array operated as a conventional imager, capturing scenes for standard image processing. Switching operating modes, the same hardware performed convolution-like operations directly in the optical and optoelectronic domain, preprocessing images before any digital computation was needed. The architecture also handled video streams, where the temporal persistence of the opto-synaptic mode allowed the system to exploit information across frames rather than treating each frame in isolation.

The diffractive components add a crucial spatial dimension to this capability. By patterning light before it reaches the sensor array, they allow certain linear operations, effectively optical convolutions, to be performed at the speed of light and at essentially no energy cost, since passive optics consume no power. The sensor array then transduces and further processes the patterned light in its reconfigurable modes. The result is a computing pipeline in which sensing, analog preprocessing, and neuromorphic event generation are woven together into a single front-end, with the back-end digital processor relieved of the bulk of the workload.

The team went beyond image and video processing to demonstrate transfer learning enabled by optical spike encoding. In this scheme, visual information is converted into trains of optical spikes whose timing and statistics encode features of the input scene. Because the sensor’s synaptic response naturally integrates and fires on these spikes, downstream learning layers can be trained efficiently on the encoded representations and adapted to new tasks without retraining from scratch. This kind of transfer learning, performed on representations extracted physically by the front-end hardware rather than computed digitally, points toward vision systems that can adapt to new environments with minimal additional computation, a property that becomes essential when the computing platform must operate under strict power constraints.

The researchers emphasize that the architecture achieves a superior spatiotemporal dimensionality compared with existing approaches. Conventional image sensors operate in a purely spatial domain, capturing two-dimensional snapshots at fixed frame rates. Neuromorphic event cameras add temporal richness but typically sacrifice conventional imaging capability. The multi-responsive sensor spans both worlds: in photodiode mode it delivers spatial fidelity, while in opto-synaptic and spiking modes it captures temporal dynamics and event-driven information. This expanded representational space, the authors argue, is precisely what demanding real-world applications require, and they point to autonomous driving, satellite remote sensing, and robotics as fields poised to benefit.

The appeal for those domains is concrete. An autonomous vehicle must simultaneously perform conventional object recognition, which favors photodiode-mode imaging, and react to sudden temporal events such as a pedestrian stepping into the road, where spike-based, low-latency processing excels. A satellite remote-sensing platform, with limited power and bandwidth, would gain enormously from a front end that compresses and encodes visual information before transmission. Robots operating in unstructured environments need vision that is fast, adaptive, and frugal with energy. A single sensor platform that can be reconfigured to serve all these roles, without multiplying hardware, could reshape how such systems are engineered.

The broader context for this work is a vigorous international effort to move computation out of the back end and into the front end of vision systems, whether into the sensor itself or into free-space optics. Brain-inspired computing has matured rapidly over the past decade, with memristive devices, phase-change materials, and two-dimensional heterostructures all competing to deliver analog memory and neuromorphic dynamics in compact form factors. What distinguishes the present advance is the combination of simplicity and versatility: a two-terminal device, requiring no complex three-terminal gating or embedded memory elements, that nonetheless offers two distinct photonic operating modes plus intrinsic neuronal firing dynamics, all switchable under low-voltage control.

Challenges remain before such sensors find their way into commercial systems. Array-scale uniformity, long-term endurance under repeated mode switching, integration with readout electronics, and compatibility with large-area fabrication will all need to be demonstrated at production quality. The energy savings promised by front-end computing are only realized in full when the surrounding system, from optics to readout circuits to back-end processors, is co-designed around the sensor’s capabilities. Nevertheless, the demonstration of reversible, in-situ reconfiguration within a single heterostructure marks a meaningful step toward vision hardware that behaves less like a passive camera and more like the retina and early visual cortex it takes as its model.

If the approach scales, the implications extend well beyond efficiency. A sensor that computes blurs the line between perception and cognition, suggesting machines whose first contact with the visual world already carries meaning: edges weighted by context, motion encoded in spike timing, salient events flagged before a single digital multiplication occurs. In a future where cameras multiply into billions of devices, from vehicles to satellites to embedded robots, pushing even a fraction of that interpretive work into the sensor itself could save staggering amounts of energy. The retinomorphic sensor described in this study offers a glimpse of that future, one in which the eye does not merely see but begins, at the moment of seeing, to think.