The core insight behind Tiny-STM is that object permanence, the cognitive ability to understand that things continue to exist when hidden from view, does not require a learned memory mechanism of the kind used in large transformer-based systems. Instead, the researchers, Swarnajit Bhattacharya of National Yang Ming Chiao Tung University in Taiwan and Ian Chao of the University of Washington, paired a standard four-gate Long Short-Term Memory network with a deterministic four-slot coordinate bank. Each slot stores the most recently observed three-dimensional position of one task object. When a cube disappears behind a stack of other blocks, its stored coordinate simply holds steady until the camera sees it again, a scheme the authors describe as a zero-order-hold update rule.

The architecture itself is deliberately conventional. The LSTM takes a seven-dimensional input vector combining the vector from the gripper tip to the target object’s stored position, the current tip position, and a one-dimensional infrared range reading from a Sharp GP2Y0A41SK0F sensor mounted on the gripper. A hidden state of 128 dimensions feeds a linear output layer that predicts an incremental three-dimensional displacement of the end effector. With 70,019 parameters in total, the network is tiny by modern standards, and after INT8 quantization through the TensorFlow Lite Micro pipeline it occupies just 68.4 KB, a small fraction of the ESP32’s 520 KB of static RAM.

Training relied on remarkably little data. The authors manually guided a Waveshare 5-DOF RoArm-M3 robotic arm through exactly 30 pick-and-place demonstrations, recording joint angles, cube centroids from a side-mounted camera, and infrared range measurements at each control step. Backpropagation through time with mean-squared-error loss and the Adam optimizer at a learning rate of 0.001 produced the deployed checkpoint. This data efficiency stands in sharp contrast to imitation-learning platforms such as ALOHA, which achieve 80 to 90 percent success on fine-grained bimanual tasks but require roughly ten minutes of teleoperated demonstrations and substantially more powerful compute.

The division of labor between hardware components is a key part of the design. A host PC or single-board computer captures camera frames and performs deterministic color-thresholding segmentation, converting detected pixel centroids into three-dimensional workspace coordinates through a calibrated pinhole camera model. The camera was calibrated with 25 checkerboard images using Zhang’s method, yielding a mean reprojection error of 0.3 pixels, while camera-to-base extrinsic calibration over 12 known points achieved a root-mean-square alignment error of 1.18 millimeters. The ESP32 then handles everything on the control side: the recurrent forward pass, analytical inverse kinematics, and PWM servo command generation, all in a measured 2.80 milliseconds.

The inverse kinematics routine reduces the five-degree-of-freedom arm problem to a planar three-degree-of-freedom calculation, exploiting the fact that the task uses a top-down grasp with a vertically oriented gripper. Base rotation comes from an arctangent of the target coordinates, while the shoulder and elbow angles follow from two-link geometry via the law of cosines. The authors handle three degenerate cases explicitly: base singularity when the target lies on the rotation axis, arm singularity near full extension where the Jacobian becomes ill-conditioned, and unreachable targets outside the geometric annulus defined by the link lengths, which are simply rejected so the arm retains its previous pose.

Physical evaluation consisted of 20 trials in which the arm sorted four labeled cubes from randomized positions into an ordered arrangement, including a vertical stacking sequence in which the fourth block becomes completely hidden behind the first three before its final grasp. The single deployed INT8 checkpoint completed 17 of 20 trials, an observed success rate of 85.0 percent with a two-sided 95 percent exact binomial confidence interval of 62.1 to 96.8 percent. The authors are careful to note that this interval describes uncertainty in the 20 observed outcomes of one checkpoint, not variability across independently trained models, since the original training seed and stopping rule were not retained.

The three failures are instructive. Mechanical backlash in the servo gearboxes introduced joint-level positional uncertainty of roughly 1.5 to 2.5 millimeters, which can accumulate across joints. Fixed color thresholds proved vulnerable to strong lighting changes and shadows that shifted pixel values out of range, degrading the segmentation masks. And when an occluded object was physically moved while hidden, the stored coordinate became stale, causing the controller to reach toward a position where the object no longer was; the gripper tolerance is approximately 18 millimeters. The authors formalize this limitation in a corollary showing that if an occluded object is displaced, the memory error grows at least in proportion to the displacement.

On latency, the measured ESP32 computation of 2.80 milliseconds combines with the nominal 33.3-millisecond camera period at 30 frames per second, profiled segmentation and Wi-Fi communication times, and a datasheet-based actuator response allowance to yield an aggregated end-to-end latency estimate of 92.6 milliseconds, equivalent to roughly 10.8 hertz. The authors emphasize that this figure is an estimate assembled from components rather than a single timed end-to-end measurement. Peak SRAM usage on the microcontroller was 94.8 KB, or 18.23 percent of capacity, leaving substantial headroom. Offline comparisons suggest the FP32 model would occupy 273.5 KB with an estimated 11.20 milliseconds of inference, underscoring the value of INT8 quantization for embedded deployment.

The study is notable as much for its honesty about boundaries as for its results. The authors explicitly state that no ablation was performed to separate the contribution of the coordinate memory from that of the recurrent state, that no numerical comparison with RT-2, OpenVLA, TinyVLA, or Diffusion Policy is possible given different tasks and hardware, and that the color-thresholding front end was never validated against ground-truth masks. Future work, they write, should include matched ablation studies with multiple training seeds, documented reproducibility protocols, perception validation, tests of behavior when occluded objects are displaced, and scaling experiments beyond four tracked objects. Even so, Tiny-STM offers a compelling demonstration that a form of object permanence can live in 68 kilobytes, bringing occlusion-aware manipulation within reach of the cheapest embedded hardware.

Subject of Research: Lightweight recurrent neural network controllers with external coordinate memory for occlusion-aware robotic manipulation on microcontrollers

Article Title: Lightweight LSTM-based memory architecture for occlusion-aware robotic manipulation on microcontrollers

Article References: Bhattacharya, S., & Chao, I. (2026). Lightweight LSTM-based memory architecture for occlusion-aware robotic manipulation on microcontrollers. Discover Informatics, 1(1), Article 23. https://doi.org/10.1007/s44564-026-00023-0

Image Credits: AI Generated

DOI: 10.1007/s44564-026-00023-0

Keywords: TinyML, LSTM, robotic manipulation, object permanence, occlusion, ESP32, microcontroller, imitation learning, inverse kinematics, INT8 quantization, embedded robotics, recurrent neural networks

The core idea is deceptively simple: instead of asking patients how much it hurts, listen to their bodies. Pain triggers well-documented physiological responses across the autonomic nervous system. Heart rate and pulse change, breathing patterns shift, skin conductance rises as sweat gland activity increases, and body temperature can fluctuate. The Spanish team combined four low-cost sensors into a single wearable setup: a pulse sensor, a respiratory rate sensor, a body temperature sensor and a galvanic skin response sensor, which measures the electrical conductance of the skin. Each of these signals has previously been linked to pain in the clinical literature, but the Sevilla group’s contribution lies in fusing them together on hardware that costs a fraction of what conventional clinical monitoring equipment does.

The choice of hardware is central to the project’s ambition. Rather than streaming data to a cloud server or a powerful workstation, the researchers deployed their machine learning models directly onto a low-cost microcontroller, an approach known as EdgeAI. This matters for several reasons. First, running inference at the edge means the system can deliver pain predictions in real time without depending on network connectivity, which is essential in busy hospital wards and rehabilitation gyms. Second, keeping physiological data on the device rather than shipping it to remote servers reduces privacy risks, an increasingly important consideration for sensitive health information. Third, microcontrollers are cheap and power-efficient, meaning a finished system could plausibly be scaled to many patients without prohibitive cost.

To make the EdgeAI approach work, the team turned to shallow machine learning algorithms rather than the deep neural networks that dominate headlines. Deep models are powerful but computationally hungry; they generally cannot fit within the memory and processing constraints of a small microcontroller. The researchers instead trained and compared several classic algorithms: artificial neural networks with modest architectures, J48 decision trees, instance-based k-nearest-neighbors classifiers, and random forests. Each model was tasked with the same job: taking the physiological readings from the four sensors and classifying the patient’s state into one of three categories: mild, moderate or severe pain.

A crucial part of the effort was the dataset itself. No off-the-shelf repository of sensor readings matched to pain labels existed for this exact configuration, so the team collected data specifically for the study, annotating recordings with pain levels. This is where the inherent difficulty of the problem becomes visible. Pain perception varies enormously between individuals and is influenced by culture, sex, psychological state and context, factors that the authors themselves acknowledge complicate data collection, annotation and inference. The labels attached to any physiological recording are therefore approximations, filtered through the same subjective reporting the system is trying to supplement. Despite this noise, the models found meaningful structure in the signals.

The results are encouraging for such a constrained platform. The random forest architecture emerged as the clear winner, achieving an accuracy of 83.60 percent in distinguishing between mild, moderate and severe pain. All tested approaches exceeded 65 percent accuracy, well above the roughly 33 percent that random guessing across three classes would achieve. Beyond raw accuracy, the team reported a battery of complementary metrics that paint a fuller picture of performance. The Kappa statistic, which measures agreement above chance, reached 0.7306, generally considered substantial. The area under the ROC curve, a measure of the model’s ability to discriminate between classes across all thresholds, hit 0.9440, a strong result. Error measures were correspondingly modest: mean absolute error of 0.1590, root mean square error of 0.2815, relative absolute error of 0.3942 and relative squared error of 0.6268.

Those numbers should be read with appropriate caution, as the authors are careful to note. An 83.60 percent accuracy in a three-class problem with subjective labels is promising but not clinical perfection, and the system is proposed as a decision-support tool rather than a replacement for clinical judgment. Still, the fact that such performance is achievable with shallow models on a microcontroller is the real headline. It suggests that the physiological signature of pain, however noisy, is strong enough to be captured by cheap hardware and simple algorithms, democratizing a capability that previously required expensive laboratory equipment or complex multimodal setups involving brain imaging or facial video analysis.

The potential applications are broad. The researchers highlight rehabilitation sessions, where physiotherapists need continuous, objective feedback about how much pain a patient is experiencing during exercises, information that patients themselves may minimize or exaggerate. The system could also be useful during surgeries and postoperative monitoring, where anesthetized or sedated patients cannot report pain at all. Perhaps most strikingly, it could serve patients with speech disorders, who currently have no reliable way to communicate their pain level to caregivers. In all these scenarios, a continuous, wearable, automatic monitor could catch pain spikes that periodic verbal check-ins miss, leading to faster interventions and better pain management strategies.

The work also fits into a rapidly growing research landscape. Machine learning approaches to pain assessment have accelerated in recent years, with studies using electrodermal activity, facial video analysis, electroencephalography and multimodal neuroimaging to predict clinical pain. Many of these efforts rely on heavy computational resources, cloud processing or specialized sensors. The Sevilla system’s distinctive contribution is its radical pragmatism: four commodity sensors, one microcontroller, four classic algorithms and a mobile application that presents the predicted pain level to the user or clinician. The mobile app completes the loop, turning raw sensor streams into an interpretable evaluation that can inform care in real time.

Challenges remain before such a system reaches routine clinical use. The subjectivity of pain perception affects every stage of the pipeline, from how training data is labeled to how well a model generalizes to new patients whose baseline physiology differs from those in the training set. Larger and more diverse datasets, longitudinal validation in real hospitals, and regulatory scrutiny will all be necessary. Yet the direction of travel is clear. As edge computing hardware grows more capable and biosensors cheaper, objective, continuous pain monitoring is moving from the research lab toward the clinic. The Spanish team’s study, supported by the Andalusian DAFNE project and the Spanish Ministry of Science’s NEKOR project, offers a concrete demonstration that meaningful pain assessment does not need a supercomputer, just well-chosen signals, well-trained models and a chip small enough to wear.

Subject of Research: Automatic pain assessment using EdgeAI machine learning and low-cost physiological sensors

Article Title: Automatic pain assessment system based on EdgeAI and low-cost sensors

Article References: García Flores, J., Cabello Arango, C. A., Duran-Lopez, L., Cerezuela-Escudero, E., & Dominguez-Morales, J. P. (2026). Automatic pain assessment system based on EdgeAI and low-cost sensors. Neural Computing and Applications, 38(18), Article 740. https://doi.org/10.1007/s00521-026-12474-5

Image Credits: AI Generated

DOI: 10.1007/s00521-026-12474-5

Keywords: pain assessment, EdgeAI, machine learning, biosensors, microcontroller, random forest, galvanic skin response, rehabilitation, wearable sensors, embedded systems, neural networks, pain management

The Electrical Testing Board, described in the open-access journal HardwareX by a research team led by Geu M. Puentes-Conde of the Universidad Autónoma de Ciudad Juárez, is a four-layer FR-4 board measuring 187 by 160 millimeters, complete with an integrated carrying handle and an 88-pin gold-finger edge connector designed for backplane integration. Rather than attempting to replace a full-scale industrial test station, the platform is positioned as a compact, reproducible alternative for circuit prototyping, academic instruction and small-scale manufacturing, where the economics of full in-circuit testing infrastructure remain prohibitive. The hardware is released under the CERN Open Hardware License v2.0, its firmware under the GNU General Public License v3.0, and its documentation under Creative Commons Attribution 4.0.

In-circuit testing verifies the values and structural integrity of individual components soldered onto a board, while functional testing validates the overall operational behavior of the finished device. Both methodologies are indispensable in industry because defects can arise from many sources: improper material handling, components that fall outside parametric tolerances, failures in surface-mount assembly equipment, or simple human error. Commercial systems from vendors such as Keysight Technologies, Teradyne and SPEA apply voltage or current stimuli through test nodes, route the resulting signals through multiplexers and conditioning stages involving amplification, filtering and linearization, and finally digitize the analog result to yield electrical parameters such as resistance, capacitance, inductance, voltage, current and short- or open-circuit status. The new board follows this same architectural logic, but in a radically miniaturized and democratized form.

At the heart of the design is a three-board modular stack. A main PCB houses the functional test modules, a relay PCB carries the switching matrices, and a pluggable MCU PCB hosts the primary controller, a Microchip PIC32MX795F512L running at 80 megahertz. Because the core module is a daughterboard, a failed microcontroller can be swapped in seconds without any desoldering. Two slave PIC18F4620 microcontrollers, managed over the I2C bus, drive the relay matrices and handle auxiliary input and output tasks. Sixteen test nodes connect the device under test to four relay-based switching buses, labeled V+, M+, M− and G−, which route signals among the programmable power supplies, the digital multimeter subsystem, comparators, programmable pull-up and pull-down networks, and protection circuitry. The reed relays at the center of these matrices, Coto 9012-12-11 units, actuate in roughly 0.35 milliseconds, allowing a complete in-circuit or functional measurement cycle of 10 to 50 milliseconds per device.

The measurement capabilities are broad. The onboard digital multimeter offers voltmeter ranges of 0 to 10 volts and 0 to 100 volts through a 16-bit successive-approximation ADC paired with a low-drift 10-volt precision reference, ammeter ranges from 1 microampere to 1 milliampere across three calibrated gain stages built around a transimpedance amplifier, resistance measurements from 0.5 ohms to 1 megohm using a ratiometric voltage-divider method, and capacitance measurements from 10 nanofarads to 220 microfarads. Rather than replicating the expensive AC voltammetry and synchronous phase-detection approach used in commercial systems, the designers adopted a direct interface circuit technique: the unknown capacitor is charged and then discharged through a known reference resistor while an embedded timer measures the interval until a comparator threshold is crossed, from which capacitance follows from simple logarithmic relations. The method trades some accuracy at the low end of the range for dramatic reductions in circuit complexity and cost.

Validation against reference instrumentation suggests the trade-offs are manageable for its intended audience. Benchmarked against an HP 34401A six-and-a-half-digit multimeter, the voltmeter stayed within 0.14 percent relative error at low-voltage test points of 1, 3.3 and 5 volts, with error and variance growing at higher voltages, reaching about 0.91 percent at 90 volts, a divergence the authors attribute to attenuation networks and parasitic loading in the high-voltage path. The ammeter achieved sub-percent errors at points such as 5 microamperes and 150 microamperes, though deviations grew near the top of each subrange. Resistance measurements remained below 1 percent relative error across 1 kilohm to 1 megohm, while the lowest point, 0.5 ohms, showed an 11.31 percent error driven by relay contact resistance, a systematic offset the firmware can compensate through tare calibration. Capacitance accuracy was weakest at 10 nanofarads, with errors above 30 percent, but settled to roughly 8 to 10 percent for bulk values of 100 and 220 microfarads.

Beyond raw metrology, the platform is designed for integration into automated test equipment environments. It communicates with a host computer or programmable logic controller over RS-232, opto-isolated UART buses, or Ethernet through a Microchip LAN8720 physical layer transceiver, using a checksum-protected packet protocol in which command bytes select tasks such as automated testing, limit transmission and data retrieval. Up to 12 boards can be daisy-chained under a single host controller, each addressed by a dedicated digital selection line and monitored through a busy-status output. In a demonstration implementation, eight boards ran parallel end-of-line tests across a multi-cavity fixture pallet, performing power-up sequencing, firmware register extraction over UART, harness continuity checks, battery voltage profiling, quiescent current measurement, pneumatic actuation of buttons via high-current relay outputs, busbar presence verification and even acoustic pattern validation through the onboard audio conditioning circuit, a capability absent from the commercial systems the authors compared against.

The team is candid about the limits of the platform. It supports a single device under test per board, offers 16 test nodes compared with up to 2,592 on a two-module Keysight i3070 system, and its practical analog bandwidth is deliberately limited to DC to 10 kilohertz by the relay switching network. It cannot measure inductance, does not support IEEE 1149.1 JTAG boundary-scan testing, and is not certified for industrial deployment, restricting its scope to controlled laboratory, prototyping and small-production settings operated by qualified engineering personnel. Long-term relay endurance, thermal drift, fault injection robustness and full metrological characterization were also left as explicit future work. Power consumption, however, is modest: roughly 2.5 watts at idle and between 3.1 and 6 watts during typical testing routines.

The economic argument is nevertheless compelling. Where a complete commercial system with instrument cards, chassis and enclosure can run into six figures, the proposed assembly costs about $790 to fabricate, or an estimated $3,500 for a full system including host controller, enclosure, cables and test probes, still roughly an order of magnitude below the entry point of industrial hardware, which typically demands $25,000 to $250,000. All design files, schematics, firmware, bill of materials and even a debugging enclosure are openly available through a public repository, enabling any competent electronics laboratory to replicate or adapt the platform.

The implications extend beyond manufacturing quality control. The authors envision materials scientists using the programmable switching matrices and multimeter to map resistance and capacitance across novel conductive polymers or biological tissue samples, applied physics laboratories replacing bulky benchtop instruments in automated experiments, environmental researchers deploying the opto-isolated inputs and Ethernet interface as a ruggedized sensor node layer, and embedded acoustics teams exploiting the audio conditioning chain for voice and frequency pattern work. Future development will focus on integrating machine learning directly into the firmware layer to shorten test cycles and enable predictive fault isolation, along with expanding the physical node architecture to widen signal routing capacity and test coverage. For a field in which the cost of entry has quietly determined who can afford rigorous electrical verification, an open, sub-$1,000 testing platform may prove to be one of the more quietly disruptive hardware releases of the year.

Subject of Research: A low-cost modular open-hardware PCB assembly for in-circuit and functional testing of electronic devices

Article Title: A low-cost modular PCB assembly for functional and in-circuit testing

Article References: Puentes-Conde, G. M., Sifuentes, E., Molina, J., Enríquez-Aguilera, F., Bravo, G., & Ávila, A. H. (2026). A low-cost modular PCB assembly for functional and in-circuit testing. HardwareX, 28, Article e00844. https://doi.org/10.1016/j.ohx.2026.e00844

Image Credits: AI Generated

DOI: 10.1016/j.ohx.2026.e00844

Keywords: in-circuit testing, functional testing, open-source hardware, printed circuit board, automated test equipment, digital multimeter, relay switching matrix, electronics manufacturing, small and medium enterprises, microcontroller, capacitance measurement, HardwareX