The underlying problem is well known to memory engineers. Crossbar arrays, in which memory elements sit at the intersections of perpendicular word lines and bit lines, offer the most compact possible memory layout and can be stacked in three dimensions. But in a passive crossbar without a selector, current sneaks through neighboring unselected cells along paths known as sneak currents, corrupting the readout of the intended cell. Selectors are two-terminal devices placed in series with each memory element—forming one-selector-one-resistor or one-selector-one-capacitor cells—to suppress these parasitic currents. An ideal selector must be extremely nonlinear, passing large current only at its selected operating voltage while blocking current at half or a fraction of that voltage, yet it must also survive trillions of switching cycles, respond in nanoseconds, remain stable across temperatures and operate identically from device to device. No single selector technology has satisfied all of these requirements simultaneously.

The USC-led team’s answer is a graded tunnel barrier realized entirely within a van der Waals heterostructure. Instead of a single uniform insulating barrier, the device stacks materials of different band alignments so that the effective barrier profile changes with applied voltage. At low voltages, the barrier remains thick and high, strangling leakage current to negligible levels. As the voltage across the device rises toward the read or write condition, the barrier is thinned and lowered in a controlled fashion, allowing electrons to tunnel through with high efficiency. The result is an exponential increase in current over a small voltage window—precisely the nonlinearity that crossbar selectors demand.

To move beyond trial and error, the researchers developed a theoretical model that predicts the electrical characteristics of selectors with graded tunnel barriers. Guided by this model, they designed and fabricated two specific device structures. In the first, the primary tunnel barrier is hexagonal boron nitride, the wide-bandgap insulator often called white graphene. In the second, the barrier is gallium sulfide, a layered semiconductor with a smaller bandgap. Both variants sandwich the barrier between two layers of molybdenum disulfide, with graphene sheets serving as the top and bottom electrodes, forming the complete five-layer stack graphene/molybdenum disulfide/barrier/molybdenum disulfide/graphene.

The performance of the hexagonal boron nitride device is striking. It exhibits a nonlinearity exceeding 10 million, meaning the current at the operating voltage is more than ten million times larger than the leakage current at reduced voltages—among the highest values reported for any two-terminal selector. Perhaps more impressive is its endurance: the device survived more than a trillion switching cycles without failure, a figure that dwarfs the lifetimes of many competing selector technologies and approaches what commercial memory products require. Switching occurs in less than 20 nanoseconds, the current-voltage characteristics show minimal temperature dependence, and the variation from one device to another is low—critical attributes for manufacturing, where billions of cells must behave nearly identically.

The gallium sulfide variant trades some nonlinearity for a dramatically reduced operating voltage. Because gallium sulfide has a smaller barrier height than hexagonal boron nitride, the device can deliver a nonlinearity above one million while operating at only 2.5 volts. Low-voltage operation matters enormously for modern memory, which must integrate with silicon circuitry whose supply voltages continue to shrink. A selector that requires high voltages to turn on forces the surrounding periphery circuitry to handle elevated stress; a selector that switches at 2.5 volts eases that burden and reduces overall energy consumption during write operations.

Beyond single devices, the team demonstrated that their selectors can be integrated into functional memory cells. They built one-selector-one-resistor cells by pairing the selectors with memristive devices, including a hafnium-oxide-based memristor stack with palladium electrodes, and they also demonstrated one-selector-one-capacitor configurations. This dual compatibility with both resistive nonvolatile memory and capacitive volatile memory suggests the selector technology is genuinely universal, applicable across different memory families rather than tied to a single cell type. The researchers benchmarked their devices against the broad landscape of existing selector technologies—including ovonic threshold switching chalcogenides, niobium oxide threshold devices, metal-insulator-metal tunnel diodes and mixed-ionic-electronic-conduction access devices—and found that the van der Waals approach uniquely combines high selectivity with trillion-cycle endurance, nanosecond speed, temperature stability and low variability.

Choosing van der Waals materials is central to the achievement. These layered crystals are held together by weak interlayer forces, so each atomic plane can be exfoliated and restacked like molecular building blocks without the dangling bonds and interfacial defects that plague conventional three-dimensional semiconductors. Atomically sharp interfaces mean the tunnel barrier thickness is controlled layer by layer, giving designers reproducible, deterministic barrier profiles. Graphene electrodes contribute their own advantages, providing chemically inert, highly conductive contacts that do not interdiffuse with the underlying layers. The same properties that have made van der Waals heterostructures a playground for condensed matter physics here translate directly into manufacturable device metrics: negligible cycling variation, minimal temperature dependence and good interdevice uniformity all flow from the crystalline perfection of the interfaces.

The implications extend toward the long-sought goal of three-dimensional memory stacking. Because the entire selector is built from vertically stacked two-dimensional layers, it is inherently stackable, unlike selectors that rely on complex oxide growth or electroforming processes that are difficult to repeat layer upon layer. Paired with scalable nonvolatile memories such as memristors and phase-change or resistive cells, these selectors could enable dense three-dimensional crossbar memories for storage-class memory, in-memory computing and neuromorphic artificial intelligence hardware, where analog crossbar arrays perform vector-matrix multiplications directly in hardware. The research team, whose work was supported by the Army Research Office, the Air Force Office of Scientific Research and the National Science Foundation, has also released the experimental and simulation data through the Harvard Dataverse, giving the broader community the tools to build on the design framework. As the demand for data storage and energy-efficient computation continues its relentless climb, devices that tame sneak currents with atomic precision may prove to be one of the quiet enablers of the next memory generation.

Subject of Research: Van der Waals tunnel-junction selector devices with graded tunnel barriers for high-density memory crossbar arrays

Article Title: High-performance tunnel-junction selectors with graded tunnel barriers based on five-layer van der Waals heterostructures

Article References: High-performance tunnel-junction selectors with graded tunnel barriers based on five-layer van der Waals heterostructures. (n.d.). https://doi.org/10.1038/s41928-026-01704-2

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01704-2

Keywords: van der Waals heterostructures, tunnel-junction selector, memory crossbar arrays, molybdenum disulfide, hexagonal boron nitride, gallium sulfide, memristors, nonlinearity, endurance, three-dimensional memory, nanoelectronics, Nature Electronics