The new study, published in Frontiers in High Performance Computing, describes how researchers took their previously published neural network, SpeckleNN, and rebuilt it as a specialized version that runs on a field-programmable gate array (FPGA). The original model, designed to classify speckle patterns across multiple biological samples, contained roughly 5.6 million parameters. That was far too large to fit on an FPGA, whose computational resources are modest compared with the sprawling silicon of a modern GPU. Through systematic architectural pruning, the team shrank the network to just 64,600 parameters, a reduction of 98.8%, while retaining 90% classification accuracy, down from the original model’s 98%.

That trade-off, the researchers argue, is precisely what makes edge deployment possible. The original SpeckleNN used two convolutional layers with 32 and 64 filters respectively, feeding into dense layers of 512 and 128 units. The optimized version cuts the first convolutional layer to just 7 filters of 5 by 5 pixels and the second to 3 filters, with dense layers reduced to 100 and 50 units. The team also compressed the latent embedding space from 128 dimensions down to 50. The dramatic reduction revealed that the larger model carried substantial redundancy, and the compact architecture ensures that each remaining parameter contributes effectively to the final classification decision.

SpeckleNN itself is built on a contrastive learning approach using twin neural networks, a technique that maps speckle patterns into a unified embedding vector space where classification is performed by measuring Euclidean distances between vectors. This design allows robust few-shot classification even when labeled examples are sparse or portions of the detector are missing, a common challenge in single-particle imaging experiments where generating extensive labeled datasets is impractical at the scale required for real-time operation.

To translate the optimized model into hardware, the team used the SLAC Neural Network Library (SNL), a framework designed specifically for deploying machine learning inference on FPGAs in high-throughput, low-latency environments. SNL converts PyTorch-defined architectures into C++ parameter templates within the Xilinx Vitis platform, representing weights and biases as memory-mapped interfaces. Data flows between layers through streaming interfaces without intermediate storage, minimizing latency and maximizing throughput. Critically, SNL supports dynamic weight loading, meaning that when a model is retrained online, the new parameters can be loaded onto the FPGA without resynthesizing the entire hardware design, a process that would otherwise be time-consuming and disruptive.

The implementation was demonstrated on a Xilinx KCU1500 FPGA board, where it consumed 71% of available digital signal processors, 75% of look-up tables, 48% of flip-flops, and 25% of block RAM. According to the Vivado post-implementation report, the board drew an average of just 9.4 watts. The team chose to run inference at 32-bit floating-point precision rather than quantizing to lower bit widths, prioritizing accuracy preservation given the already aggressive model compression, though they note that future work will explore quantization to squeeze out further resource savings.

Performance measurements were striking. Using an Integrated Logic Analyzer to track the complete inference frame from the arrival of the first pixel to the generation of the final 50-dimensional latent output, the FPGA completed the operation in approximately 9,003 clock cycles at a 5-nanosecond clock period, yielding a total latency of about 45.05 microseconds. Running the same inference on an NVIDIA A100 GPU, by contrast, took around 400 microseconds and consumed roughly 73 watts. The FPGA therefore delivered an 8.9-fold speedup and a 7.8-fold reduction in power consumption compared with the GPU implementation.

Because GPUs typically require batch processing to achieve optimal throughput, they introduce latency and memory constraints that are problematic when data must be streamed continuously from a detector and immediate feedback is required. The FPGA, by contrast, processes individual data points with minimal latency, eliminating the bottlenecks associated with batch size constraints and the overhead of transferring data to and from a remote compute node. This per-image processing capability is what makes real-time vetoing of speckle patterns feasible directly at the point of data acquisition.

To verify that the hardware implementation faithfully reproduced the software original, the team conducted a layer-by-layer comparison between SNL’s C-simulation and PyTorch, examining convolution, ReLU activation, max-pooling, and the dense layers. The two frameworks produced nearly identical feature maps, with pixel-wise differences mostly confined to the range of negative 0.0005 to positive 0.0005, attributable to floating-point precision variations and framework-specific optimizations. In the dense layer, prominent activation spikes appeared around neurons 60 through 70 in both frameworks, directly reflecting the high-activation regions captured in the central portions of the convolutional feature maps. These small numerical discrepancies, while noticeable in certain neurons, remained negligible relative to the overall magnitude of neuron outputs, which ranged from approximately negative 20,000 to positive 20,000.

The implications extend well beyond single-particle imaging. The researchers note that the same constraints of bandwidth, latency, and compute limitations apply across data-intensive scientific domains, including high-energy physics and electron microscopy, where adaptive FPGA-based inference could similarly transform experimental workflows. By enabling real-time adaptive classification and efficient vetoing of unusable frames, the FPGA-accelerated SpeckleNN reduces storage demands, supports online decision-making, and allows models to be continuously retrained and redeployed as experimental conditions evolve. As X-ray free-electron laser facilities push toward ever higher repetition rates, the ability to make intelligent decisions at the detector itself, rather than downstream in a computing center, may prove essential to keeping pace with the data deluge of next-generation photon science.

Subject of Research: FPGA-accelerated neural network for real-time X-ray single-particle imaging at XFEL facilities

Article Title: FPGA-accelerated SpeckleNN with SNL for real-time X-ray single-particle imaging

Article References: Dave, A., Wang, C., Russell, J., Herbst, R., & Thayer, J. (2025). FPGA-accelerated SpeckleNN with SNL for real-time X-ray single-particle imaging. Frontiers in High Performance Computing, 3, Article 1520151. https://doi.org/10.3389/fhpcp.2025.1520151

Image Credits: AI Generated

DOI: 10.3389/fhpcp.2025.1520151

Keywords: FPGA, SpeckleNN, X-ray single-particle imaging, XFEL, machine learning, SLAC Neural Network Library, edge computing, neural network compression, real-time inference, LCLS, GPU comparison, scientific computing