The work, published in Frontiers in Electronics, tackles a problem that has long frustrated automated inspection: wafer maps are low-resolution grids in which each die on a wafer is marked simply as background, pass, or fail. Subtle patterns such as thin scratches or localized clusters of failing dies are easy to miss, and the publicly available benchmark dataset, WM-811K, is severely imbalanced. Of roughly 811,000 collected wafer maps, only about 55,000 carry reliable labels, and the dominant category is not a defect at all but the background “None” class, which accounts for nearly 94 percent of the cleaned training data. Rare but operationally critical patterns like Donut, Edge-Ring, and Scratch can be outnumbered by factors of hundreds.

Accuracy metrics alone can be deeply misleading in this setting. A model that simply predicts “None” for most wafers would score well overall while missing nearly every genuine defect. The research team, led by Mst. Rokeya Khatun of Chittagong University of Engineering and Technology together with collaborators in Malaysia and South Korea, therefore evaluated their model using macro-averaged precision, recall, and F1 scores, which give equal weight to every class regardless of how many examples it contains.

The architecture itself is deliberately spare. Two convolution-pooling stages, the first with 32 output channels and the second with 64, form the backbone, and each pooling step is followed by a modified version of the convolutional block attention module, or CBAM. Channel attention is computed through a shared two-layer multilayer perceptron stabilized by batch normalization, which suppresses feature channels dominated by uninformative background. Spatial attention then uses parallel convolutional filters of three different kernel sizes, allowing the network to respond simultaneously to fine scratches, compact defect clusters, and broad annular rings. A residual skip connection guards against over-suppression of minority-class signals. The entire network totals just 153,261 parameters, roughly 0.6 megabytes in 32-bit floating point, with a computational cost of only 0.02 gigafloating-point operations per inference.

Placing attention after pooling rather than before it proved to be a key design decision. At the standardized 26-by-26 input resolution, the two convolution stages already produce an effective receptive field covering most of the wafer surface, making deeper backbones redundant. Applying attention on the small 11-by-11 and 4-by-4 feature maps that result from pooling enhances defect saliency at minimal cost, letting the model discriminate thin rings, edge bands, and localized anomalies without the memory and latency penalties of heavyweight architectures.

Class imbalance was handled entirely at the data level, and only during training. A compact convolutional autoencoder with about 40,500 parameters learned to encode real training wafers into a latent representation. By injecting small amounts of Gaussian noise into that latent code and decoding the result, the team generated roughly 2,000 label-consistent synthetic samples for each minority class, preserving ring continuity, edge localization, and clustered failure patterns while introducing useful variability. Meanwhile, the dominant None class was downsampled from 13,489 to 2,489 examples, an 81.6 percent reduction. Crucially, validation and test sets remained entirely real and untouched, eliminating any risk of data leakage inflating the results.

Under a fixed-seed protocol with a stratified 70/10/20 train-validation-test split, the model reached 99.88 percent test accuracy with near-ceiling macro-F1, all while running on the free CPU tier of Google Colab. Baseline comparisons revealed a striking pattern: heavyweight networks such as VGG16, ResNet-50, and EfficientNet-B0, which require between 5.3 million and 138 million parameters, performed well on globally structured patterns like Edge-Ring and Near-Full but stumbled on the fine, localized Loc and Scratch classes, with recall dropping as low as 0.55. The lightweight attention-equipped model compressed per-class performance into a narrow, high-accuracy band, lifting recall on the difficult classes to between 0.96 and 0.99.

Ablation studies confirmed that both the augmentation strategy and the attention modules contributed measurably. Removing augmentation cost 1.3 points of macro-F1, while removing CBAM entirely cost 1.9 points, the largest single drop. Within the attention module, the multi-scale spatial branch proved the more important component. Robustness checks showed graceful degradation rather than collapse: with only 10 percent of the training data, macro-F1 remained above 96 percent, and adding Gaussian noise at test time reduced accuracy only moderately.

Perhaps most importantly for factory deployment, the researchers subjected their model to three complementary explainability analyses. Grad-CAM highlighted class-level morphologies such as annular rims for ring defects and peripheral bands for edge-localized patterns. Integrated gradients traced pixel-level attributions along thin boundaries and fragmented structures, while occlusion sensitivity identified the regions whose removal most reduced the classification score. The three methods converged on the same physically meaningful defect regions, indicating that the model’s decisions rest on interpretable wafer geometry rather than spurious background cues.

The authors note limitations, including the small number of random seeds used for statistical analysis and the model’s computational cost relative to some specialized lightweight designs, and they point toward multi-label classification, domain adaptation across fabrication tools, open-set recognition, and hardware-aware quantization as future directions. But the core message stands: high accuracy, compactness, and transparency need not be traded off against one another. For inline wafer screening on resource-constrained fab equipment, a 0.15-million-parameter network that explains its own decisions may be exactly what the industry needs.

Subject of Research: Lightweight attention-based deep learning for wafer map defect classification in semiconductor manufacturing

Article Title: CBAM-enhanced lightweight CNN for wafer map defect classification

Article References: Khatun, M. R., Farid, F. A., Dhar, S., Islam, M. S., Uddin, J., & Abdul Karim, H. B. (2026). CBAM-enhanced lightweight CNN for wafer map defect classification. Frontiers in Electronics, 7, Article 1750707. https://doi.org/10.3389/felec.2026.1750707

Image Credits: AI Generated

DOI: 10.3389/felec.2026.1750707

Keywords: wafer map defect classification, convolutional neural network, CBAM attention module, WM-811K dataset, class imbalance, convolutional autoencoder augmentation, explainable AI, Grad-CAM, integrated gradients, lightweight deep learning, semiconductor manufacturing, edge AI