The achievement addresses one of the central manufacturing challenges facing high-temperature silicon carbide electronics: producing many small, consistent devices on a single wafer. The university team adapted much of the JFET fabrication process used in its earlier chip-scale work to wafer scale, taking account of manufacturability at industrial standards. To overcome the equipment limitations of a university laboratory, the researchers collaborated with Phenitec Semiconductor Corp., which operates a mass-production fabrication plant. The resulting transistor was fabricated on a 6-inch SiC epitaxial wafer, and the successful process transfer provides an experimental basis for developing integrated circuits based on the device structure.

Kyoto University described the result as a technical milestone because integrated circuits require large numbers of compact, electrically similar transistors rather than a single laboratory component. The reported threshold-voltage measurement provides evidence of within-wafer consistency, but the release does not characterize the full electrical performance, yield, reliability or long-term behavior of devices across the entire wafer. It also does not establish that complete integrated circuits or practical commercial products have already been produced. Instead, the study shows that the established JFET fabrication sequence can be implemented at wafer scale and that the first trial produced uniform devices in the wafer center, an outcome the research team said was better than anticipated.

The devices build on the team’s previous work on a silicon carbide transistor that operates at 600°C. That temperature tolerance is the defining performance claim relevant to electronics intended for extreme environments, although the present announcement focuses on scaling the fabrication process rather than introducing a new operating-temperature record. The combination of the earlier high-temperature device research and the current wafer-scale demonstration broadens the reported manufacturing path toward silicon carbide integrated circuits. Potential application areas identified by the research team include jet-engine sensors, geothermal-resource development and exploration of Venus, but the release presents these as prospective areas rather than demonstrated uses of the fabricated transistors.

First author Mitsuaki Kaneko said the researchers had expected wafer-scale device fabrication itself to succeed but were surprised by the degree of uniformity in the center region during the first fabrication trial. He also emphasized the distance between creating a device in a laboratory and deploying it in society. The Kyoto University–Phenitec collaboration was intended to help close that gap, and the researchers are aiming to establish a startup, although they acknowledge that substantial challenges remain. The immediate scientific achievement is therefore not a finished silicon carbide circuit or a ready-made extreme-environment sensor; it is the successful transfer of a previously laboratory-scale JFET process to a 6-inch wafer, accompanied by a measured demonstration of threshold-voltage uniformity and a step toward evaluating the technology at production-relevant scale.

Subject of Research: Experimental wafer-scale fabrication of 600°C silicon carbide junction field-effect transistors for extreme-environment integrated circuits.

Article Title: Lab to fab at the wafer-scale for SiC

Article References: Lab to fab at the wafer-scale for SiC. Original publication (Bibliographic details unavailable.)

Image Credits: AI Generated

DOI: Not provided

Keywords: silicon carbide, JFETs, wafer-scale fabrication, high-temperature electronics, integrated circuits, threshold-voltage uniformity, ion implantation, Kyoto University, Phenitec Semiconductor, semiconductor manufacturing, wafer-scale, scientific research

The challenge the researchers set out to solve is one of the most stubborn in condensed matter physics and device engineering. A conventional transistor is not made of one material but of several fundamentally different ones working in intimate contact. A semiconductor carries the current, a dielectric insulator controls it through an applied gate voltage, and metallic or semimetallic contacts allow charge to enter and exit. As silicon devices shrink toward their physical scaling limits, atomically thin two-dimensional semiconductors have been heralded as natural successors. Yet for more than two decades, the obstacle to practical 2D electronics has rarely been the performance of the semiconductor itself. It has been the integration problem: how to attach the other components without destroying the delicate atomic sheet they must sit upon.

The surfaces of two-dimensional semiconductors are chemically inert in a troublesome way. They contain few dangling bonds or reactive sites where other materials can anchor, which makes it extraordinarily difficult to deposit a gate dielectric uniformly across them. Conventional dielectric deposition tends to produce patchy, leaky films on such surfaces. Direct metal deposition is equally problematic, since the energetic process can damage the atomically thin semiconductor or create large contact barriers that choke off the flow of charge. Mechanical transfer methods, in which separate 2D materials are peeled, aligned, and stacked one by one, offer an alternative, but they are slow, difficult to scale uniformly over large areas, and poorly suited to the demands of mass production.

The IBS team’s answer was to stop thinking of the crystal as just the semiconductor and start treating it as the raw material for everything. They began with multilayer tungsten diselenide, a two-dimensional semiconductor whose electrical character can be altered by replacing the atoms surrounding the tungsten layer. By preserving the tungsten framework while selectively swapping those surrounding atoms, the researchers changed the electronic identity of individual regions without rebuilding the crystal from scratch. The upper layers were first oxidized into insulating tungsten oxide, and that oxide could then be further converted through vapor-phase reactions into either tungsten disulfide, an n-type semiconductor, or tungsten ditelluride, a semimetal. Regions left untouched retained the original tungsten diselenide semiconductor behavior. In this way, semiconducting, insulating, and semimetallic functions were created directly within different layers and locations of the same parent crystal.

The precision of the method rests on a remarkably elegant physical principle: the tiny gaps between neighboring atomic layers act as natural barriers that confine the chemical reaction. By tuning the reaction temperature and gas pressure, the researchers could halt the conversion after a chosen number of layers, achieving depth control of roughly 0.7 nanometers per tungsten diselenide monolayer. That is the thickness of a single atomic sheet, meaning the process can be steered with a resolution measured in individual atomic planes. This layer-by-layer chalcogen substitution, as the technique is known, effectively turns a crystal-growth problem into a controllable chemical editing problem, one atomic layer at a time.

The most consequential demonstration involved converting the upper layers of tungsten diselenide into tungsten oxide directly above the semiconductor channel. The resulting oxide served as the gate dielectric without any need to deposit a separate high-permittivity material, forming an insulating layer with an effective thickness below one nanometer while maintaining strong insulating performance. This is a significant achievement, because the gate dielectric is where many would-be 2D devices fail. A dielectric that is too thick or too leaky wastes voltage and allows current to slip through when the transistor should be off. A dielectric grown from the channel material itself, atom-for-atom matched to the surface beneath it, sidesteps the interface problems that have plagued conventional deposition.

The electrical performance of the resulting devices came astonishingly close to theoretical ideals. Using this self-grown oxide, the researchers fabricated tungsten diselenide transistors in which a change of only 61.3 millivolts in gate voltage increased the current tenfold. That figure sits very near the theoretical room-temperature limit of about 60 millivolts per decade, the so-called Boltzmann limit that defines the most efficient switching any conventional transistor can achieve. The devices also achieved an on/off current ratio exceeding ten million, meaning the difference between the transistor’s conducting and blocking states spans more than seven orders of magnitude. For low-power electronics, where every wasted millivolt translates into wasted energy, these numbers represent the kind of switching efficiency that device engineers spend careers pursuing.

The contact side of the problem was addressed with equal precision. When the upper layers were converted into tungsten ditelluride, a semimetal, the resulting contacts reduced the barrier for charge injection to about one-third of what was observed with direct platinum contacts. Lower injection barriers mean charge carriers can enter the semiconductor more freely, cutting the parasitic resistance that has historically limited the performance of 2D transistors. The semimetal-to-semiconductor junction created by chemical conversion is also atomically clean by construction, since it forms within the same crystal lattice rather than across the boundary between two separately grown materials.

To show that the method extends beyond individual devices, the team fabricated n-type molybdenum disulfide transistors using the same tungsten oxide dielectric, and then stacked p-type and n-type transistors vertically to construct a complementary van der Waals inverter, a basic building block of digital logic. The successful voltage inversion demonstrated that the technique is not merely a laboratory curiosity for single transistors but a plausible foundation for more highly integrated circuitry. Vertical stacking of complementary devices is particularly attractive for future electronics, because it multiplies functional density without shrinking lateral dimensions further, a direction the industry finds increasingly costly.

The implications reach well beyond one material system. The study combines fundamental materials science based on atomic-scale manipulation with modern semiconductor technology, addressing what Jo Moon-Ho described as the central integration challenge in two-dimensional semiconductor research: not simply finding better semiconductors, but securing equally suitable dielectrics and electrical contacts. By directly converting selected regions of a two-dimensional crystal into different electronic functions, the approach could provide a new route toward ultralow-power, ultrascaled, and vertically integrated semiconductor devices. If the method can be scaled to wafer dimensions with the same layer-by-layer precision demonstrated here, the era in which a complete transistor is grown rather than assembled may be closer than the industry dared expect.

Subject of Research: Layer-by-layer chemical conversion of a single 2D crystal into semiconducting, insulating, and semimetallic regions for integrated transistors

Article Title: Turning single 2D crystal into a complete high-performance transistor

Article References: Turning single 2D crystal into a complete high-performance transistor. (n.d.). Original publication

Image Credits: AI Generated

DOI: Not provided

Keywords: two-dimensional materials, tungsten diselenide, transistors, gate dielectric, chalcogen substitution, van der Waals heterostructures, semiconductors, tungsten ditelluride, low-power electronics, integrated circuits, Institute for Basic Science, atomic-scale fabrication

To appreciate why this matters, it helps to understand what a phononic integrated circuit, or PnIC, actually is. Just as photonic integrated circuits guide light through nanoscale channels, phononic circuits guide mechanical vibrations—phonons—through engineered waveguides. At gigahertz frequencies, these vibrations have wavelengths measured in mere hundreds of nanometers, roughly five orders of magnitude shorter than electromagnetic waves of the same frequency. That enormous shrinkage factor means acoustic devices can pack resonators, filters, and delay lines into a footprint far smaller than any radio-frequency electromagnetic equivalent. This is precisely why acoustic filters already sit inside nearly every smartphone, converting crowded radio signals into clean channels. The catch has been that most existing acoustic platforms force engineers to choose: they can have low-loss waveguides, or high-quality resonators, or efficient transducers, but rarely all of these on one chip.

The Virginia Tech and University of Virginia collaboration set out to break that trade-off. Their ideal platform, as described in the paper, should simultaneously support four building blocks: low-loss acoustic waveguides, high-quality-factor resonators, high-performance modulators, and efficient electromechanical transducers. The material pairing they chose is chemically and mechanically elegant. Lithium niobate is a ferroelectric crystal famous for its strong piezoelectric properties, meaning it converts electrical signals into mechanical motion—and back again—with exceptional efficiency. It also possesses large electro-optic and acoustic velocities that make it a favorite in modern integrated photonics. Silicon nitride, by contrast, is one of the lowest-loss optical materials known, forms ultrasmooth films, and is compatible with standard semiconductor foundry processes. By patterning thin-film silicon nitride directly on lithium niobate, the team created a hybrid structure in which each material does what it does best: lithium niobate drives and senses the vibrations, while the carefully shaped silicon nitride confines and directs them.

The headline performance metric of the new platform is the propagation frequency-quality factor product of its acoustic waveguides, which reached 4.22 × 10^13. In the world of resonant and wave-based systems, the quality factor, or Q, measures how many oscillation cycles a wave or resonator completes before its energy dissipates. Multiplying Q by frequency yields a figure of merit that is largely independent of scale, allowing fair comparison across platforms. A frequency-Q product above 10^13 places these acoustic waveguides in an elite class of coherent information carriers, comparable to the best optical waveguides in relative terms. Practically, it means that a gigahertz sound wave traveling through the team’s circuits retains its energy over distances long enough to build complex, multi-element circuits—delays, filters, interferometers—without the signal fading into heat. For quantum applications, where a single phonon must survive long enough to be manipulated and read out, such low loss is not a luxury but a prerequisite.

Waveguides alone do not make a circuit, however; engineers also need ways to split and combine acoustic signals with minimal waste. The team demonstrated directional couplers—devices in which two waveguides run close enough that vibrational energy gradually transfers from one to the other through evanescent coupling, the same physics that lets a vibrating tuning fork set a neighboring fork ringing. Their couplers achieved controllable power transfer at an insertion loss of just 3.5 dB. Insertion loss quantifies how much signal is lost simply by passing through a component, and every decibel counts when signals are weak or when photons and phonons must be conserved at the quantum level. A 3.5 dB figure means that roughly 55 percent of the acoustic power survives the coupling process, a level the authors identify as a key enabler for routing phonons between resonators, delay lines, and transducers on the same chip.

Storage is the third pillar, and here the platform delivered ring resonators with a loaded quality factor of up to 17,925. An acoustic ring resonator is a closed loop of waveguide in which sound circulates, resonating at frequencies whose wavelengths fit an integer number of times around the ring. The loaded Q includes the coupling losses to the outside world, not just the intrinsic material loss, making it the number that matters in real systems. A loaded Q near 18,000 at gigahertz frequencies corresponds to phonons persisting for microseconds—a long time on the scale of microwave electronics. Long-lived acoustic resonances are the heart of the spectral processing that makes radio-frequency acoustic filters so selective, and they are equally the heart of proposed quantum memories, where mechanical modes would buffer quantum states between optical photons or superconducting qubits.

The team then assembled these building blocks into a showcase application: a 1-gigahertz phononic oscillator built around one of their ring resonators. An oscillator is the metronome of electronics—a device that produces a perfectly periodic signal used to time everything from radio transmitters to radar systems to quantum logic gates. The best electronic oscillators achieve their stability by referencing a high-Q mechanical or electromagnetic resonance, and the new phononic oscillator leverages the platform’s 17,925 loaded Q to spectacular effect. It reached a phase noise of −159.0 dBc/Hz at a 100-kilohertz offset from the carrier. Phase noise describes the rapid, random fluctuations in an oscillator’s timing; lower is better, and the decibel scale here means the noise power is 159 billion times smaller than the carrier power within a one-hertz bandwidth at that offset. That figure rivals the performance of much bulkier, power-hungry microwave oscillators, in a device etched onto a chip.

The implications ripple outward across several fields at once. For microwave acoustics, the platform offers a path toward integrated radio-frequency processors that are smaller, cleaner, and more stable than today’s surface-acoustic-wave and bulk-acoustic-wave components, which typically rely on suspended or bulky geometries. For quantum phononics, low-loss gigahertz phonons are a sought-after resource: they can couple to superconducting qubits through piezoelectric transduction, interface with solid-state defects such as those in diamond or silicon carbide, and bridge to optical photons in hybrid quantum networks. Lithium niobate’s piezoelectricity makes that electromechanical link natural, while silicon nitride’s optical excellence makes the photonic link equally promising. The authors point to integrated hybrid systems combining phonons, photons, superconducting qubits, and solid-state defects as the long-term destination—and this platform is designed from the outset to host all of them.

The research was conducted with support from several major United States funding programs, including the Air Force Office of Scientific Research, the Defense Advanced Research Projects Agency’s OPTIM, SynQuaNon, and GRYPHON programs, and fabrication was performed at the Center for Nanophase Materials Sciences, a Department of Energy Office of Science user facility. The work also reflects a growing trend in which Virginia’s university ecosystem—through the Commonwealth Cybersecurity Initiative—invests in the intersection of quantum devices and secure communications. The paper, received in March 2026 and accepted in September 2026, is open access, allowing engineers and physicists worldwide to build on its results immediately.

What makes this demonstration genuinely exciting is its completeness. Many platform papers showcase a single impressive component; this one delivers waveguides, couplers, resonators, and a working oscillator, all on the same material system, all at gigahertz frequencies, and all with numbers that stand up against the best specialized devices in each category. The phonon, long treated as the awkward cousin of the photon, now has an integrated circuit platform worthy of its ambitions. If the trajectory of silicon photonics is any guide, the coming years could see these sound-based circuits shrink radar front ends, sharpen quantum sensors, and serve as the mechanical backbone of hybrid quantum machines—proof that sometimes the future of computing hums at a frequency we cannot hear, in a material we cannot see, on a chip smaller than a fingernail.

Subject of Research: Low-loss gigahertz phononic integrated circuits on a silicon nitride–lithium niobate platform

Article Title: Low-loss phononic integrated circuits based on a silicon nitride-lithium niobate platform

Article References: Ji, J., Thomas, J. G., Xi, Z., Liu, R., Fang, K., Qin, Y., Beling, A., Yi, X., Zhu, Y., & Shao, L. (2026). Low-loss phononic integrated circuits based on a silicon nitride-lithium niobate platform. Communications Engineering. https://doi.org/10.1038/s44172-026-00795-1

Image Credits: AI Generated

DOI: 10.1038/s44172-026-00795-1

Keywords: phononics, integrated circuits, silicon nitride, lithium niobate, acoustic waveguides, ring resonators, quality factor, oscillators, phase noise, quantum phononics, microwave acoustics, piezoelectricity

The breakthrough, published in the prestigious international journal Science, was led by Prof. Jianhua Hao, Head of the Department of Physics and Materials, Chair Professor of Materials Physics and Devices and Associate Director of the PolyU-Wuhan Technology and Innovation Research Institute at PolyU. The collaboration included researchers from the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. Dr. Zehan Wu, Research Assistant Professor in the same department, is the first author of the research article. Their work addresses what the International Roadmap for Devices and Systems (IRDS) has identified as one of the most pressing bottlenecks in modern microelectronics, and it does so using a device architecture that the roadmap itself has flagged as the most promising successor to today’s dominant transistor design.

To appreciate why this matters, it helps to understand how the transistors inside every laptop, smartphone, and data centre actually work. Integrated circuits are built from complementary metal–oxide–semiconductor field-effect transistors, or MOSFETs, which switch electrical current by raising or lowering an energy barrier. In the OFF state, charges face a barrier they cannot cross; when a gating voltage is applied, charges gain enough thermal energy to spill over the top of that barrier in a process called thermionic emission. The steepness of this transition, measured by a figure known as the subthreshold swing (SS), determines how much voltage is needed to flip the transistor from OFF to ON. Here nature intervenes: because thermionic emission depends on the thermal distribution of electron energies, the subthreshold swing of any MOSFET cannot fall below 60 millivolts per decade of current at room temperature. That is the Boltzmann limit, and it is not an engineering shortfall but a consequence of statistical mechanics itself.

The consequences of this limit are profound. As chipmakers pack more transistors onto each processor, the 60 mV decade⁻¹ floor forces operating voltages to remain far higher than ideal, which means wasted power, wasted heat, and a hard ceiling on energy efficiency. Advanced MOSFETs typically require gate-voltage ranges of around 800 millivolts to operate, and every millivolt of that overhead is multiplied billions of times across a modern chip. For the artificial intelligence accelerators now driving enormous growth in global electricity consumption, the inability to switch transistors at lower voltages has become one of the defining engineering challenges of the decade. Breaking the 60 mV barrier is therefore not an incremental improvement but a potential inflection point for the entire industry.

The escape route identified by physicists is quantum tunnelling. Instead of forcing electrons to climb over an energy barrier, a tunnelling field-effect transistor (TFET) allows them to pass straight through it, exploiting the quantum-mechanical probability that particles can traverse barriers that would classically be impenetrable. Because tunnelling probability depends on the barrier’s width and height rather than on the thermal energy of the electrons, a TFET can in principle achieve subthreshold swings steeper than 60 mV decade⁻¹ even at room temperature. The IRDS has singled out TFETs as the most promising alternative to MOSFETs precisely for this reason. In practice, however, experimental TFETs have struggled for years with a frustrating trade-off: devices that achieved steep switching typically delivered painfully low output currents, undermining their usefulness in real circuits.

Prof. Hao’s team solved this problem with an elegantly engineered material system. Using pulsed laser deposition (PLD), a technique in which intense laser pulses vaporise a target material so that it recondenses as an ultra-thin film, the researchers fabricated an alternating heterostructure of two-dimensional bismuth (Bi) and indium selenide (InSe) layers. The choice of bismuth is the crucial insight. In its bulk form, bismuth is a semi-metal, a material that is neither a proper conductor nor a proper semiconductor. But when reduced to two-dimensional form with precise control over the layer structure at the nanoscale, bismuth transforms into a semiconductor. This transformation allowed the team to engineer an ideal energy band alignment between the bismuth and the indium selenide, creating exactly the conditions needed for charge carriers to tunnel efficiently from one material into the other through the quantum tunnelling mechanism.

The performance figures reported in the study are striking. The resulting Bi/InSe TFET achieved subthreshold swing values well below the 60 mV decade⁻¹ thermionic limit, and it maintained this steep switching behaviour across six orders of magnitude of current, a range that matters enormously for practical digital logic, where transistors must remain reliably OFF across many conditions rather than only at a single operating point. Remarkably, the device accomplished all of this at room temperature, on standard centimetre-scale silicon substrates, without exotic cryogenic cooling or specialised wafer treatments. The operating gate-voltage range required was only 160 millivolts, a fraction of the roughly 800 millivolts demanded by advanced MOSFETs, translating directly into the kind of power savings that next-generation computing demands.

Just as importantly, the device resolved the long-standing weakness of previous experimental TFETs. The PolyU-led team demonstrated a high output current of up to several microamps per micrometre alongside an exceptionally high ON/OFF current ratio. Output current is not a vanity metric: it determines whether a single transistor can drive multiple downstream logic gates, a capability engineers call fan-out, and whether signals propagate through a circuit with minimal delay. A steep-switching transistor that cannot deliver adequate current would force designers into cumbersome workarounds and erode the very efficiency gains it promises. By combining steep slopes with robust current drive, the Bi/InSe device demonstrates compatibility with existing integrated-circuit design practices and even the potential for a generational upgrade of current chips rather than a disruptive replacement.

The manufacturing dimension of the work may prove as consequential as the physics. Pulsed laser deposition has long been valued in research laboratories for its precision, but questions have lingered about whether it can serve high-precision, wafer-scale production of two-dimensional materials. This study demonstrates the practical viability of PLD for exactly that role, producing uniform ultra-thin heterostructures on silicon substrates that are the backbone of the existing semiconductor industry. Because the device integrates seamlessly with traditional silicon-based manufacturing processes, the researchers argue that their approach provides a scalable roadmap toward energy-efficient microchips, rather than a laboratory curiosity that would require an entirely new industrial ecosystem to deploy. That compatibility with ultra-short channel lengths, which two-dimensional materials are particularly well suited to support, positions the technology for the transistor geometries that future process nodes will demand.

The implications extend well beyond the laboratory bench. Ultra-low-power, high-performance integrated circuits built on tunnelling transistors could reshape the energy economics of artificial intelligence, where specialised hardware already consumes power on the scale of entire cities, and where every reduction in switching voltage compounds across billions of operations per second. Prof. Hao has emphasised that the technology paves the way for the ICs essential to emerging AI chips and advanced semiconductor applications, and the publication of the findings in Science signals that the broader research community regards the result as a landmark. For decades, the Boltzmann limit has stood as an immovable fact of life for chip designers, a boundary drawn by thermodynamics itself. By replacing thermionic emission with quantum tunnelling in a carefully crafted two-dimensional heterostructure, the PolyU-led team has shown that the boundary can be crossed, and in doing so has brought a long-awaited experimental technology a decisive step closer to commercial reality.

Subject of Research: A quantum-tunnelling field-effect transistor based on two-dimensional bismuth and indium selenide heterostructures that overcomes the Boltzmann switching limit in integrated circuits

Article Title: PolyU develops quantum-tunnelling field-effect transistor to overcome barriers to integrated-circuit chip development

Article References: PolyU develops quantum-tunnelling field-effect transistor to overcome barriers to integrated-circuit chip development. (n.d.). Original publication

Image Credits: AI Generated

DOI: Not provided

Keywords: quantum tunnelling, tunnelling field-effect transistor, TFET, two-dimensional materials, bismuth, indium selenide, Boltzmann limit, subthreshold swing, pulsed laser deposition, integrated circuits, low-power electronics, AI chips