The device architecture at the heart of this investigation is designed to maximize tunneling efficiency while suppressing leakage. It features a Germanium source, whose relatively low bandgap of 0.66 electron-volts enables high levels of carrier injection, paired with a Silicon drain and channel regions whose wider bandgap of 1.12 electron-volts reduces off-state leakage. A heavily doped p+ pocket layer, just 10 nanometers thick, sits at the source-channel junction to create steeper band bending and narrow the tunneling barrier width. The silicon body is vertically segmented into this p+ pocket and an n+ channel layer, each 10 nanometers thick, separated by a silicon dioxide layer. The total gate length is 70 nanometers, including a 30-nanometer lightly doped channel region that suppresses ambipolar conduction by physically distancing the drain junction from the tunneling hotspot. A hetero-dielectric gate stack comprising 2 nanometers of SiO2 and 7 nanometers of high-κ HfO2 reduces the equivalent oxide thickness without increasing physical gate leakage, while the gate metal work function is set to 4.25 electron-volts for optimal threshold characteristics.

What makes this study particularly timely is the growing recognition that interface traps—loose bonds or structural mismatches at the oxide-semiconductor interface—can randomly capture or emit carriers, leading to fluctuations in threshold voltage, on-current, and subthreshold swing. While the impact of random dopant fluctuation and line edge roughness has been extensively studied, the statistical variability arising from spatially localized interface traps in heterojunction devices remained a unique area of investigation. Previous variability studies had largely assumed uniform trap distributions across the entire interface, obscuring the physical reasons for heterostructure TFET degradation. The researchers addressed this critical gap by employing an interface segmentation-based statistical framework to explicitly compare the impact of trap localization within the pocket and channel regions.

Using Synopsys Sentaurus TCAD, the team modeled the device physics with an extended set of physical models. The dynamic non-local band-to-band tunneling model based on Kane’s formulation calculated the tunneling generation rate, evaluating tunneling probability across the complete spatial energy barrier rather than at a single point. This non-local formulation is particularly important for the abrupt Ge-source/Si-pocket heterojunction, where strong spatial band variation and non-uniform electric fields exist near the tunneling junction. The Shockley-Read-Hall recombination model simulated the impact of interface traps, with trap occupancy depending dynamically on local carrier concentrations and the trap energy level. Fermi-Dirac statistics accounted for the degenerate carrier concentrations in the highly doped source and pocket regions, while Old Slotboom bandgap narrowing models accurately represented the reduction in effective bandgap caused by high doping concentrations.

To investigate the impact of spatially localized traps, the researchers adopted the Interface Segmentation Approach, dividing the oxide-semiconductor interface along the 70-nanometer gate length into uniform 5-nanometer segments. Each segment’s interface trap density was treated as a random variable with a Gaussian distribution, centered at the mid-bandgap with an energy standard deviation of 0.1 electron-volts. The mean trap density was 4.96 × 10¹² cm⁻²eV⁻¹ with a spatial standard deviation of 2.88 × 10¹² cm⁻²eV⁻¹. A total of 100 randomized device instances were simulated for each study case to generate statistically significant distributions of the electrical parameters. Four distinct scenarios were considered: a baseline ideal device with no interface traps, traps randomized exclusively in the segments overlapping the n+ channel region, traps randomized exclusively in the segments overlapping the p+ pocket region, and traps randomized across the entire interface to mimic a realistic process scenario.

The baseline simulation established a stable on-current of 1.208 × 10⁻¹⁰ A/µm and an extremely low off-current of 1.71 × 10⁻¹³ A/µm, with a threshold voltage of 0.3137 volts. The mean electron velocity in the channel was recorded at 1.37 × 10⁸ cm/s, providing a reference for transport efficiency. The minimum subthreshold swing for the baseline device was found to be 38.4 mV/dec. Contour plots confirmed that the tunneling generation was strictly confined to the heterojunction interface between the Ge source and the Si pocket, validating the point-tunneling mechanism operated by the electric field peak. No significant Shockley-Read-Hall activity in the active region indicated that leakage mechanisms were effectively suppressed in the ideal device.

When interface traps were infused in the oxide region overlapping the n+ channel, the statistical analysis revealed a clear degradation in transport. The mean on-current dropped to 1.192 × 10⁻¹⁰ A/µm, a reduction of approximately 1.3 percent. Most critically, the electron velocity showed a significant drop from the baseline 1.37 × 10⁸ cm/s to 7.85 × 10⁷ cm/s—a reduction of approximately 42 percent. This confirms that channel traps strongly perturb carrier transport, reducing drift velocity drastically even though the tunneling injection remains stable. The spatial separation between the tunneling junction and the channel trap region ensures that the electrostatics at the Ge-source/p+-pocket interface remain largely unperturbed, preserving the peak electric field and tunneling width governing band-to-band tunneling. Meanwhile, the minimum subthreshold swing increased to a mean value of 148.12 mV/dec with a standard deviation of 4.12 mV/dec, indicating trap-induced broadening of the subthreshold transition through trap-assisted tunneling leakage and potential fluctuations.

In stark contrast, when traps were introduced in the heavily doped p+ pocket region—the zone typically regarded as the most sensitive in TFETs because of its proximity to the tunneling junction—the device demonstrated remarkable robustness. The band-to-band tunneling and Shockley-Read-Hall profiles were almost identical to the trap-free case, confirming a powerful screening effect. The primary transport parameters showed near-zero statistical variability, with the mean on-current and threshold voltage remaining identical to the baseline values. The minimum subthreshold swing showed a mean value of 142.94 mV/dec with a small standard deviation of 2.41 mV/dec. This immunity arises from the strong electrostatic screening in the heavily doped pocket, where the carrier concentration of 5 × 10¹⁹ cm⁻³ makes the Debye screening length sufficiently short, enabling mobile carriers to effectively screen localized interface-trap charges. Consequently, trap-induced potential perturbations decay rapidly, preventing significant alteration of the tunneling barrier and local electric field. The peak electric field of 1.067 × 10⁵ V/cm at the Ge-source/p+-pocket interface remained unchanged, preserving the tunneling probability.

When traps were distributed across both the pocket and channel regions, mimicking the natural by-products of gate stack fabrication and interface process steps, the statistical parameters were almost identical to the channel-only case. The on-current remained at 1.192 × 10⁻¹⁰ A/µm, and the minimum subthreshold swing gave a mean of 148.35 mV/dec with a standard deviation of 3.69 mV/dec—values very close to the channel-only case of 148.12 ± 4.12 mV/dec. This confirms that the reliability of the HDDG TFET is limited solely by the channel interface, as the source-pocket junction is guarded by the screening mechanism. The pocket region remains electrically isolated from trap-induced disturbances even under mixed-trap scenarios, highlighting the strength of the source-pocket junction design.

The comparative analysis against recently reported TFET structures, using their respective worst-case post-trap-analysis values, further validates the proposed architecture. While absolute values vary considerably across different device architectures, material systems, geometries, and bias conditions, the HDDG TFET demonstrates localized trap immunity within the heavily doped pocket region while the degradation caused by channel-localized traps remains spatially distinguishable. Despite the reduction in on-current under the worst-case trap condition, the device maintains low leakage and a post-trap subthreshold swing that remains comparable to, and in some cases better than, previously reported degraded TFET characteristics. The transfer characteristics obtained under trap-free, Gaussian, and uniform trap distributions exhibited only moderate variations, confirming the effectiveness of the heavily doped p+ pocket in suppressing trap-induced electrostatic perturbations.

These findings carry significant implications for reliability-aware low-power device design. For the HDDG architecture, process optimization should focus on improving the quality of the channel interface rather than the heterojunction boundary, maximizing reliable performance. The study reveals that device sensitivity is predominantly transport-limited: traps localized at the oxide-n+ channel interface act as scattering centers that reduce the mean electron velocity by 42 percent and degrade on-current by 1.3 percent, while the critical source-pocket tunneling junction demonstrates statistical immunity to interface traps. These insights are expected to guide future TFET process improvement strategies, particularly for interface engineering and high-κ dielectric integration in ultra-low power and variability-aware device design. As the semiconductor industry continues to push toward aggressively scaled tunneling devices for energy-constrained applications, understanding precisely where interface traps strike hardest—and where heavy doping can provide electrostatic armor—will be essential for translating the promise of sub-60 mV/decade switching into commercial reality.

Subject of Research: Nanoelectronics

Article Title: Role of trap position variation on electrical parameters in hetero-dielectric double gate TFET

Article References: Dutta, R., Bose, A., Hoque, S., & Saha, R. (2026). Role of trap position variation on electrical parameters in hetero-dielectric double gate TFET. Frontiers in Nanotechnology, 8, Article 1961029. https://doi.org/10.3389/fnano.2026.1961029

Image Credits: AI Generated

DOI: 10.3389/fnano.2026.1961029

Keywords: tunnel field-effect transistor, TFET, interface traps, Germanium source, hetero-dielectric double gate, band-to-band tunneling, subthreshold swing, reliability, variability analysis, Debye screening, trap-assisted tunneling, low-power electronics