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The significance of the 48 V-to-12 V conversion stage becomes clearer when viewed against the broader architecture of modern data center power delivery. In a typical server rack, electricity arrives at 48 V from the rectifier and must ultimately be reduced to sub-1 V levels for the processor cores themselves. Each intermediate conversion stage introduces losses, and because these losses accumulate multiplicatively across the chain, even single-digit percentage improvements at the intermediate bus level translate into meaningful savings at the facility scale. A converter operating at 98.8% peak efficiency dissipates only about 12 watts of loss per kilowatt delivered, whereas a converter at 95% efficiency would dissipate more than 50 watts over the same output. Across thousands of converters in a hyperscale facility, that difference compounds into megawatts of avoided heat generation, reduced cooling load, and lower operating expenditure.

The choice of a resonant switched-capacitor topology for this 4:1 step-down ratio reflects a deliberate trade-off analysis. Traditional hard-switched switched-capacitor converters suffer from transient current spikes at every switching event, because the flying capacitors momentarily connect to nodes at different potentials with only parasitic resistance limiting the current. Inserting a small resonant inductor into the charge path reshapes these current pulses into smooth sinusoidal segments, and when the switching frequency is matched to the resonant frequency, the current naturally reaches zero at the moment each switch turns off. This is the essence of zero-current switching: the device transitions while carrying no current, eliminating the overlap of voltage and current that constitutes the dominant switching loss mechanism. The 20 to 40 nanosecond dead time reserved between complementary gate signals further guards against shoot-through conduction, in which both switches of a half-bridge would briefly conduct simultaneously and create a destructive low-impedance path across the supply.

It is worth noting the distinction between zero-current switching and the zero-voltage switching strategies adopted in some competing designs. Zero-voltage switching turns a device on while its terminal voltage has been driven to zero, which is particularly advantageous for MOSFETs whose output capacitance would otherwise discharge abruptly through the channel. The cited comparison in the source literature found that zero-voltage switching reduced switching loss by roughly half relative to zero-current switching at light loads, achieving over 97% efficiency even at 3% of rated load. However, zero-current switching offers its own benefits, including simpler control requirements and naturally sinusoidal current waveforms that reduce electromagnetic interference. The selection between these soft-switching families often depends on the operating load profile of the target application, and a data center intermediate bus converter that spends most of its life at moderate-to-heavy load may favor the zero-current approach demonstrated here.

The thermal management findings in this work deserve particular attention because they address a frequently underappreciated aspect of power converter design. Every watt dissipated as heat in a converter must ultimately be removed by the data center cooling infrastructure, and the thermal resistance between a hot semiconductor junction and the ambient air determines how much temperature rise accompanies that dissipation. Printed circuit boards are not merely electrical interconnect substrates; they are also the primary thermal conduction path for surface-mounted power devices. Copper planes act as lateral heat spreaders, while vias function as vertical thermal conduits connecting heat-generating components on the surface to internal layers and to copper pours that can couple to heatsinks or chassis metal.

The reported comparison between six-layer and eight-layer board constructions quantifies this effect with unusual clarity. By adding copper layers and optimizing via placement beneath and around the power devices, the designers reduced the temperature rise of key components by 9.6 degrees Celsius while simultaneously improving conversion efficiency by 1.5 percentage points. These two outcomes are causally linked rather than coincidental. The resistance of copper increases with temperature at a rate of roughly 0.4% per degree Celsius, so cooler copper traces and windings exhibit lower conduction losses, which in turn reduces heat generation, creating a modest but genuine positive feedback loop in the favorable direction. Additionally, MOSFET on-state resistance rises with junction temperature, so cooler switches conduct more efficiently. The 1.5% efficiency gain from substrate optimization therefore represents not just better heat removal but an interruption of the loss-heating-loss spiral that degrades conventional designs.

The physics of via construction helps explain why stack-up optimization matters so much at high currents. A typical via is plated with copper only on its cylindrical wall, and for a standard 0.3 mm diameter via this wall may be only tens of micrometers thick, presenting a surprisingly high resistance to current flowing vertically through the board. When tens of amperes must traverse from one layer to another, designers must place many vias in parallel and fill or plug them where possible. Thermal vias arranged in arrays under power pads serve double duty, carrying heat downward while sharing electrical current. The eight-layer architecture presumably provided more horizontal copper area for current spreading and more vertical pathways for heat extraction, and the experimental confirmation that these geometric changes yield measurable efficiency and temperature benefits validates the growing practice of treating PCB stack-up design as a first-order element of power converter engineering rather than an afterthought.

Contextualizing the full-load figure of 96.1% at 70 A also requires understanding how efficiency curves behave across the load range. Switched-capacitor and resonant converters typically exhibit peak efficiency at some intermediate load, where conduction losses scale with the square of current but remain small, while fixed losses from gate driving and control circuitry have already been amortized. At full load, conduction losses in the MOSFET channel resistances, capacitor equivalent series resistance, and copper traces dominate, pushing efficiency downward from the peak. The fact that this design retains 96.1% at 70 A, only 2.7 percentage points below its peak, indicates a well-balanced loss distribution in which no single mechanism dominates. Designs with poorly optimized magnetics or excessive switch resistance often show much steeper droop at heavy load, and the comparative examples cited in the source article, such as a dual-bus architecture achieving only 85.05% full-load efficiency, illustrate the practical consequences of that imbalance.

The loss breakdown reported for competing approaches also illuminates where the remaining losses in this design are likely concentrated. In the cited dual-bus converter, copper loss in inductors and conduction loss in MOSFETs accounted for 70% of total losses, and the 2-ounce copper layers of the PCB contributed up to 25% of total loss under high current. These figures underscore that at high currents, the passive interconnect infrastructure, including traces, planes, and vias, becomes a loss contributor comparable to the active devices themselves. This is precisely why the present work’s emphasis on PCB structural optimization is scientifically coherent: when conduction paths carry 70 amperes, even milliohm-level resistances dissipate watts, and the cumulative effect across an entire power stage is substantial.

The resonant switched-capacitor approach also carries implications for component selection and reliability. Because the resonant inductors can be small, often realized as air-core or low-value ferrite components or even as deliberately added parasitic inductances of the layout itself, the design avoids the saturation limits that constrain magnetic components in conventional topologies. The source article notes that magnetic components constrained by core saturation flux remain a persistent challenge in the field, and a topology that minimizes magnetic energy storage sidesteps this limitation. Similarly, the requirement for multiple capacitors in parallel to mitigate component tolerance in high step-down converters is partially relaxed by the resonant operation, which is less sensitive to exact capacitance values than hard-switched charge transfer.

From a systems integration perspective, the demonstrated stability across a wide load range matters because data center loads are inherently dynamic. Processor workloads fluctuate on microsecond timescales, and power delivery networks must respond without excessive voltage excursion or efficiency collapse at light load. A converter that maintains excellent electrical characteristics across its operating envelope can be deployed without elaborate load-dependent mode switching, simplifying control architecture and improving fault tolerance. The N+1 redundancy strategies mentioned in the context of vertical power delivery architectures similarly depend on converters that behave predictably when individual units are taken offline or brought online.

The broader trajectory of this research area suggests several directions for future development. The integration of autotuning and adaptive zero-current-switching control, referenced in the surrounding literature, points toward converters that can retune their resonant frequency as component values drift with temperature and aging, preserving soft-switching operation over the full service life. Advances in wide-bandgap semiconductors, particularly gallium nitride devices with low gate charge and minimal output capacitance, would further reduce both switching and conduction losses in this topology. Meanwhile, the continued densification of data center hardware, driven by the thermal and power demands of artificial intelligence accelerators, will keep pressure on power density metrics, and the 4700 W/in3 figures achieved by cascaded resonant designs in the literature indicate the scale of what optimized implementations can reach. The present demonstration, combining near-99% peak efficiency with quantified thermal benefits from substrate engineering, provides a reproducible template for how circuit topology and physical layout must be co-optimized to meet the exacting requirements of next-generation high-performance computing power delivery.

Subject of Research: …

Article Title: A 98.8%-efficiency, thermally-optimized 48 V-to-12 V DC–DC converter for high-power data centers

Article References: A 98.8%-efficiency, thermally-optimized 48 V-to-12 V DC–DC converter for high-power data centers. (n.d.). https://doi.org/10.3389/felec.2026.1697781

Image Credits: AI Generated

DOI: 10.3389/felec.2026.1697781

Keywords: efficiency, thermally-optimized, V-to-12, converter, high-power, data, centers, scientific research