The architecture uses a pipelined, scale-free CORDIC datapath. Carry-lookahead adders are incorporated into timing-critical stages to shorten critical-path delay, while hybrid configurations retain ripple-carry adders in less critical paths. The study presents this selective arrangement as a way to balance computational performance against hardware cost rather than using the faster adder type throughout the entire circuit.

The design also employs mutually exclusive micro-rotation techniques. According to the researchers, these techniques reduce the number of CORDIC iterations and eliminate the need for scale-factor compensation. Together with the pipelined datapath and hybrid adder arrangement, these changes are intended to improve the efficiency of hardware-based sine and cosine generation.

FPGA implementation on a Xilinx Artix-7 device confirmed accurate sine and cosine outputs at a reported power consumption of 0.175 W. The authors also evaluated a standard-cell ASIC implementation using the open SkyWater 130 nm process design kit and the Yosys–OpenROAD flow. This version achieved a core area of 0.88 mm², an achievable clock frequency of 32 MHz and total power consumption of 10.2 mW.

The ASIC design completed timing closure with zero violations across all sign-off corners, providing evidence that the proposed architecture can be implemented beyond FPGA prototyping. The reported results are tied to the specific FPGA, process technology and synthesis flow used in the study, so they describe the tested implementations rather than universal performance across other hardware platforms.

Subject of Research: FPGA and ASIC hardware acceleration of CORDIC-based trigonometric signal generation

Article Title: High-speed FPGA implementation of the CORDIC algorithm using carry lookahead adders

Article References: Kanadal, K. M., Pradhan, A. K., S, A., & Roy, C. (2026). High-speed FPGA implementation of the CORDIC algorithm using carry lookahead adders. Scientific Reports. https://doi.org/10.1038/s41598-026-74995-2

Image Credits: AI Generated

DOI: 10.1038/s41598-026-74995-2

Keywords: CORDIC algorithm, FPGA, ASIC design, carry-lookahead adder, trigonometric generation, hardware acceleration, pipelined architecture, SkyWater 130 nm, Yosys, OpenROAD, High-speed, implementation

The filter at the heart of the study is an extended Kalman filter, or EKF, the workhorse algorithm engineers use to estimate the state of a dynamic system from noisy measurements. The EKF works by linearizing the system’s motion model around the current estimate, predicting where the target should be, and then correcting that prediction with each new seeker measurement. For tracking problems with mild, well-behaved Gaussian noise, this recipe is remarkably effective. But real seeker data is rarely so cooperative. Glint effects, countermeasures, clutter, and abrupt target maneuvers all inject outliers—measurements that are wildly inconsistent with the statistical assumptions the filter relies on. A standard EKF treats every measurement as trustworthy, so a handful of bad readings can drag the state estimate far off course at precisely the moment accuracy matters most.

The researchers’ answer is to replace the filter’s least-squares cost function with the Huber cost function, a classic tool from robust statistics. The Huber function behaves like a quadratic for small residuals, where ordinary least squares is optimal, but switches to a linear penalty for large residuals. The practical consequence is that outlier measurements still influence the estimate, but their influence is capped rather than allowed to dominate. The resulting Huber-based extended Kalman filter, or HEKF, has been studied before in applications ranging from GPS navigation to spacecraft attitude estimation, and it consistently delivers more reliable estimates under non-Gaussian noise. The catch is computational: instead of a single closed-form update, the Huber formulation requires an iterative optimization loop that must converge on every filter cycle, multiplying the arithmetic workload by an order that embedded flight computers cannot easily absorb.

That bottleneck is what drove the team—Nayeon Kim, SeongJin Yoon, Heoncheol Lee of Kumoh National Institute of Technology, and Ikchan Lim, Changyeol Lee, and Jangseong Park of defense contractor LIGNEX1—toward hardware acceleration. Their target platform was an FPGA, a reconfigurable silicon chip whose logic fabric can be wired into custom digital circuits. Unlike a CPU, which executes instructions sequentially on a handful of cores, an FPGA can instantiate hundreds of arithmetic units that all operate in parallel, each one dedicated to a specific piece of the algorithm. For an iterative filter that must complete its entire predict-and-correct cycle within the tight timing budget of a seeker’s sampling rate, that architectural difference is decisive.

The centerpiece of the implementation is a custom intellectual property block, or IP core, built specifically to evaluate the Huber function and the iterative minimization it drives. Rather than letting a general-purpose processor grind through the optimization in software, the designers encoded the Huber computation directly into hardware datapaths, pipelined so that successive iterations and matrix operations overlap in time. The result is high-throughput, low-latency execution of the very step that makes the HEKF so expensive. In their evaluation, the Huber IP alone ran 6.79 times faster than the same computation on the processing system—the ARM-class CPU portion of the system-on-chip—while the complete HEKF, with the Huber core integrated into the filter pipeline, achieved an overall 3.71-fold acceleration.

Speed means little if accuracy collapses, so the team benchmarked the hardware implementation against the software version on denoising performance and estimation accuracy. The two proved comparable: the FPGA version preserved the robust filter’s ability to suppress measurement noise and track the line-of-sight rate through the nonlinear, outlier-ridden conditions that motivated the design in the first place. In other words, the researchers did not trade estimation quality for throughput; they simply removed the computational excuse for not using the more robust algorithm in real time. For guidance engineers, that is the crucial result, because it means the theoretically superior filter can finally be flown, not just simulated.

The work fits into a broader and rapidly accelerating trend of moving onboard aerospace algorithms from processors into reconfigurable hardware. Previous studies from overlapping research groups have parallelized particle filters and particle swarm optimization on FPGAs for ballistic target tracking, and accelerated convolutional neural network inference for routing in low-Earth-orbit satellite networks. GPU acceleration has been explored for related problems, including model predictive control in integrated missile guidance systems, but FPGAs hold particular appeal for flight hardware because they combine deterministic timing with low power consumption and resistance to the software overheads that plague general-purpose platforms. Comparisons of FPGA, CPU, GPU, and ASIC acceleration for neural network workloads have repeatedly highlighted the FPGA’s sweet spot: customizable parallelism without the fabrication cost of a fixed application-specific chip.

What makes the new study technically interesting is the marriage of robust estimation theory with register-transfer-level design. Kalman filtering on FPGAs is not new in itself—researchers have built hardware accelerators for EKF-based simultaneous localization and mapping, battery state estimation, and other applications—but the Huber variant introduces an iterative inner loop that resists naive parallelization. Each iteration depends on the previous one, so the designers must pipeline carefully, reusing hardware for matrix operations while keeping the convergence loop tight. The custom Huber IP solves this by treating the optimization as a dedicated hardware subroutine, effectively giving the filter a silicon-fast engine for the one part of the algorithm that software cannot execute quickly enough. The approach builds on the team’s earlier 2025 work on parallelized Huber-based EKF implementations, refining it into the present system-level evaluation.

The practical implications extend beyond missiles. Any platform that must estimate the state of a fast, maneuvering, poorly characterized target from noisy sensors faces the same trade-off between robustness and compute budget: drones tracking ground vehicles, radar systems following debris, autonomous vehicles fusing lidar returns, and spacecraft determining attitude in the presence of faulty star tracker readings. A hardware recipe that makes robust filtering affordable in real time is a template that transfers across those domains. The Korean work was funded by the Defense Acquisition Program Administration through the Korea Research Institute for Defense Technology Planning and Advancement, under a program developing design technology for an integrated guidance and control simulator incorporating weapon datalink and seeker systems—signaling that the intended path from laboratory FPGA board to operational guidance hardware is already mapped.

There remain, of course, the usual caveats of early hardware research. The reported speedups were measured against the processing system of the development platform, and further gains will depend on floating-point precision choices, clock rates, and how much of the remaining filter arithmetic migrates into custom logic. Certification of reconfigurable hardware for safety-critical flight systems carries its own regulatory burden. But the direction of travel is unmistakable. As seekers grow more capable and targets grow faster, the algorithms that keep interceptors on course are becoming too computationally demanding for conventional processors alone. By proving that a robust, outlier-resistant Kalman filter can run in hardware at full seeker speed—3.71 times faster than before, with accuracy intact—this study offers a concrete glimpse of where real-time guidance computing is headed: away from software loops and into the fabric of the chip itself.

Subject of Research: FPGA hardware acceleration of a Huber-based extended Kalman filter for robust real-time line-of-sight target tracking

Article Title: FPGA Implementation of Huber-Based Extended Kalman Filter for Real-Time High-Speed Target Tracking

Article References: Kim, N., Yoon, S., Lee, H., Lim, I., Lee, C., & Park, J. (2026). FPGA Implementation of Huber-Based Extended Kalman Filter for Real-Time High-Speed Target Tracking. International Journal of Aeronautical and Space Sciences. https://doi.org/10.1007/s42405-026-01216-5

Image Credits: AI Generated

DOI: 10.1007/s42405-026-01216-5

Keywords: FPGA, extended Kalman filter, Huber function, target tracking, missile guidance, line-of-sight rate, hardware acceleration, robust estimation, embedded systems, parallelization, seeker, real-time computing