The architecture uses a pipelined, scale-free CORDIC datapath. Carry-lookahead adders are incorporated into timing-critical stages to shorten critical-path delay, while hybrid configurations retain ripple-carry adders in less critical paths. The study presents this selective arrangement as a way to balance computational performance against hardware cost rather than using the faster adder type throughout the entire circuit.

The design also employs mutually exclusive micro-rotation techniques. According to the researchers, these techniques reduce the number of CORDIC iterations and eliminate the need for scale-factor compensation. Together with the pipelined datapath and hybrid adder arrangement, these changes are intended to improve the efficiency of hardware-based sine and cosine generation.

FPGA implementation on a Xilinx Artix-7 device confirmed accurate sine and cosine outputs at a reported power consumption of 0.175 W. The authors also evaluated a standard-cell ASIC implementation using the open SkyWater 130 nm process design kit and the Yosys–OpenROAD flow. This version achieved a core area of 0.88 mm², an achievable clock frequency of 32 MHz and total power consumption of 10.2 mW.

The ASIC design completed timing closure with zero violations across all sign-off corners, providing evidence that the proposed architecture can be implemented beyond FPGA prototyping. The reported results are tied to the specific FPGA, process technology and synthesis flow used in the study, so they describe the tested implementations rather than universal performance across other hardware platforms.

Subject of Research: FPGA and ASIC hardware acceleration of CORDIC-based trigonometric signal generation

Article Title: High-speed FPGA implementation of the CORDIC algorithm using carry lookahead adders

Article References: Kanadal, K. M., Pradhan, A. K., S, A., & Roy, C. (2026). High-speed FPGA implementation of the CORDIC algorithm using carry lookahead adders. Scientific Reports. https://doi.org/10.1038/s41598-026-74995-2

Image Credits: AI Generated

DOI: 10.1038/s41598-026-74995-2

Keywords: CORDIC algorithm, FPGA, ASIC design, carry-lookahead adder, trigonometric generation, hardware acceleration, pipelined architecture, SkyWater 130 nm, Yosys, OpenROAD, High-speed, implementation

The new study, published in Frontiers in High Performance Computing, describes how researchers took their previously published neural network, SpeckleNN, and rebuilt it as a specialized version that runs on a field-programmable gate array (FPGA). The original model, designed to classify speckle patterns across multiple biological samples, contained roughly 5.6 million parameters. That was far too large to fit on an FPGA, whose computational resources are modest compared with the sprawling silicon of a modern GPU. Through systematic architectural pruning, the team shrank the network to just 64,600 parameters, a reduction of 98.8%, while retaining 90% classification accuracy, down from the original model’s 98%.

That trade-off, the researchers argue, is precisely what makes edge deployment possible. The original SpeckleNN used two convolutional layers with 32 and 64 filters respectively, feeding into dense layers of 512 and 128 units. The optimized version cuts the first convolutional layer to just 7 filters of 5 by 5 pixels and the second to 3 filters, with dense layers reduced to 100 and 50 units. The team also compressed the latent embedding space from 128 dimensions down to 50. The dramatic reduction revealed that the larger model carried substantial redundancy, and the compact architecture ensures that each remaining parameter contributes effectively to the final classification decision.

SpeckleNN itself is built on a contrastive learning approach using twin neural networks, a technique that maps speckle patterns into a unified embedding vector space where classification is performed by measuring Euclidean distances between vectors. This design allows robust few-shot classification even when labeled examples are sparse or portions of the detector are missing, a common challenge in single-particle imaging experiments where generating extensive labeled datasets is impractical at the scale required for real-time operation.

To translate the optimized model into hardware, the team used the SLAC Neural Network Library (SNL), a framework designed specifically for deploying machine learning inference on FPGAs in high-throughput, low-latency environments. SNL converts PyTorch-defined architectures into C++ parameter templates within the Xilinx Vitis platform, representing weights and biases as memory-mapped interfaces. Data flows between layers through streaming interfaces without intermediate storage, minimizing latency and maximizing throughput. Critically, SNL supports dynamic weight loading, meaning that when a model is retrained online, the new parameters can be loaded onto the FPGA without resynthesizing the entire hardware design, a process that would otherwise be time-consuming and disruptive.

The implementation was demonstrated on a Xilinx KCU1500 FPGA board, where it consumed 71% of available digital signal processors, 75% of look-up tables, 48% of flip-flops, and 25% of block RAM. According to the Vivado post-implementation report, the board drew an average of just 9.4 watts. The team chose to run inference at 32-bit floating-point precision rather than quantizing to lower bit widths, prioritizing accuracy preservation given the already aggressive model compression, though they note that future work will explore quantization to squeeze out further resource savings.

Performance measurements were striking. Using an Integrated Logic Analyzer to track the complete inference frame from the arrival of the first pixel to the generation of the final 50-dimensional latent output, the FPGA completed the operation in approximately 9,003 clock cycles at a 5-nanosecond clock period, yielding a total latency of about 45.05 microseconds. Running the same inference on an NVIDIA A100 GPU, by contrast, took around 400 microseconds and consumed roughly 73 watts. The FPGA therefore delivered an 8.9-fold speedup and a 7.8-fold reduction in power consumption compared with the GPU implementation.

Because GPUs typically require batch processing to achieve optimal throughput, they introduce latency and memory constraints that are problematic when data must be streamed continuously from a detector and immediate feedback is required. The FPGA, by contrast, processes individual data points with minimal latency, eliminating the bottlenecks associated with batch size constraints and the overhead of transferring data to and from a remote compute node. This per-image processing capability is what makes real-time vetoing of speckle patterns feasible directly at the point of data acquisition.

To verify that the hardware implementation faithfully reproduced the software original, the team conducted a layer-by-layer comparison between SNL’s C-simulation and PyTorch, examining convolution, ReLU activation, max-pooling, and the dense layers. The two frameworks produced nearly identical feature maps, with pixel-wise differences mostly confined to the range of negative 0.0005 to positive 0.0005, attributable to floating-point precision variations and framework-specific optimizations. In the dense layer, prominent activation spikes appeared around neurons 60 through 70 in both frameworks, directly reflecting the high-activation regions captured in the central portions of the convolutional feature maps. These small numerical discrepancies, while noticeable in certain neurons, remained negligible relative to the overall magnitude of neuron outputs, which ranged from approximately negative 20,000 to positive 20,000.

The implications extend well beyond single-particle imaging. The researchers note that the same constraints of bandwidth, latency, and compute limitations apply across data-intensive scientific domains, including high-energy physics and electron microscopy, where adaptive FPGA-based inference could similarly transform experimental workflows. By enabling real-time adaptive classification and efficient vetoing of unusable frames, the FPGA-accelerated SpeckleNN reduces storage demands, supports online decision-making, and allows models to be continuously retrained and redeployed as experimental conditions evolve. As X-ray free-electron laser facilities push toward ever higher repetition rates, the ability to make intelligent decisions at the detector itself, rather than downstream in a computing center, may prove essential to keeping pace with the data deluge of next-generation photon science.

Subject of Research: FPGA-accelerated neural network for real-time X-ray single-particle imaging at XFEL facilities

Article Title: FPGA-accelerated SpeckleNN with SNL for real-time X-ray single-particle imaging

Article References: Dave, A., Wang, C., Russell, J., Herbst, R., & Thayer, J. (2025). FPGA-accelerated SpeckleNN with SNL for real-time X-ray single-particle imaging. Frontiers in High Performance Computing, 3, Article 1520151. https://doi.org/10.3389/fhpcp.2025.1520151

Image Credits: AI Generated

DOI: 10.3389/fhpcp.2025.1520151

Keywords: FPGA, SpeckleNN, X-ray single-particle imaging, XFEL, machine learning, SLAC Neural Network Library, edge computing, neural network compression, real-time inference, LCLS, GPU comparison, scientific computing

The study, authored by Mohammad Waseem of Jamia Millia Islamia in New Delhi, takes an unusually broad view of the field. Rather than focusing on a single function, it critically assesses 120 research articles and review papers to build a system-level picture of how artificial intelligence and machine learning are transforming battery management across state estimation, cell balancing, thermal management, fault diagnosis, predictive maintenance, intelligent charging, edge computing, and cloud connectivity. According to the review, this integrated perspective is what previous surveys have lacked, and it reveals both how far the technology has come and where its most stubborn bottlenecks remain.

At the heart of every battery management system, or BMS, lies a deceptively simple question: what is the battery actually doing right now? Two quantities dominate the answer. The state of charge, or SoC, describes how much energy remains in the pack relative to its nominal capacity, while the state of health, or SoH, captures how much the battery has degraded over its lifetime. Neither can be measured directly. Both must be inferred from voltage, current, and temperature readings using computational algorithms, a task made harder by the fact that lithium-ion cells behave in strongly nonlinear ways that shift with temperature, aging, and driving patterns.

Conventional BMS architectures have long relied on model-based techniques such as coulomb counting, equivalent circuit models, and Kalman filtering to estimate these hidden states. These methods have served the industry well, but the review highlights a fundamental weakness: they struggle to represent the nonlinear electrochemical behavior of lithium-ion batteries under varying operating conditions. As battery packs in modern electric vehicles grow larger and more complex, the amount of real-time sensor data they generate has outstripped what traditional models can meaningfully process, and subtle degradation patterns slip through the cracks.

This is where machine learning enters the picture. Artificial neural networks have been widely applied to state of charge estimation because of their ability to capture complex nonlinear battery dynamics, and experimental studies cited in the review show that ANN-based models can achieve significantly improved accuracy compared with conventional estimation techniques, particularly under dynamic operating conditions. Support vector machines and ensemble learning methods have proven effective at detecting battery faults and abnormal operating conditions at early stages, flagging problems before they escalate into safety hazards. The trade-off is real, however: these models demand large training datasets and substantial computational resources, which can complicate deployment on the embedded processors that actually live inside a vehicle.

Deep learning has pushed the frontier further. Long short-term memory networks, convolutional neural networks, and deep neural networks have been extensively explored for predicting battery degradation and remaining useful life, the parameter known as RUL. LSTM networks are particularly well suited to this task because they excel at analyzing time-series data and capturing the temporal dependencies that characterize how batteries age. The review notes that studies published in leading energy journals have demonstrated that deep learning models can achieve high prediction accuracy and improved robustness compared with traditional analytical models, though the price is longer training times and heavier computational demands.

Beyond estimation, artificial intelligence is reshaping how batteries are charged and protected. Reinforcement learning algorithms learn optimal charging policies through interaction with the battery system and its environment, dynamically adjusting charging rates based on real-time inputs such as state of charge, state of health, temperature, and grid conditions. The goal is to balance charging speed against battery longevity while avoiding degradation mechanisms like lithium plating and thermal stress. The review reports that reinforcement learning approaches have shown improved energy efficiency and reduced battery aging compared with traditional charging methods, although they require extensive training cycles and carefully designed reward functions to perform stably.

Thermal management represents another critical frontier. Because lithium-ion battery performance and safety are tightly coupled to temperature, improper thermal regulation can accelerate degradation and, in the worst case, trigger thermal runaway, a failure mode characterized by uncontrolled heat generation and potential fire. Smart BMS designs now incorporate per-cell or per-module temperature sensing using thermistors and integrated sensing devices, feeding real-time thermal data into control units that dynamically activate cooling or heating mechanisms and adjust charge and discharge limits. Convolutional neural networks and autoencoders have proven especially effective at detecting thermal anomalies and hidden fault patterns in sensor data, giving the BMS an early warning system that rule-based logic alone cannot match.

The review also spotlights two emerging hardware and infrastructure trends that could define the next generation of battery management. The first is FPGA-based edge implementation, in which field-programmable gate arrays and embedded processors execute machine learning models with the low latency required for safety-critical real-time control. Recent work on FPGA-based intelligent battery management units demonstrates dynamic power distribution techniques, though the review cautions that these platforms bring higher implementation cost and design complexity. The second is IoT-enabled cloud integration, in which distributed sensors transmit battery data to centralized platforms where machine learning models perform fleet-level optimization, predictive diagnostics, and over-the-air updates. Prototype systems integrating these technologies have demonstrated improved reliability and predictive maintenance capabilities, but they introduce new concerns around cybersecurity, communication latency, and data management at scale.

Perhaps the review’s most consequential conclusion is that no single artificial intelligence technique is universally optimal. Artificial neural networks and LSTM models deliver high estimation accuracy for state of charge and state of health, convolutional architectures excel at fault diagnosis, and support vector machines and random forests offer robust performance with lower computational requirements that suit embedded systems. The most promising pathway forward, the author argues, lies in hybrid approaches that combine model-based methods with data-driven algorithms, leveraging the physical understanding embedded in equivalent circuit models and Kalman filters alongside the pattern-recognition power of machine learning. Future directions identified in the review include physics-informed machine learning, digital twins, edge intelligence, and cloud-connected battery ecosystems, all of which point toward battery management systems that are not merely protective but genuinely predictive and autonomous.

Subject of Research: AI and machine learning applications in smart battery management systems for electric vehicles

Article Title: AI/ML enabled smart battery management systems in electric vehicles

Article References: Waseem, M. (2026). AI/ML enabled smart battery management systems in electric vehicles. Frontiers in Batteries and Electrochemistry, 5, Article 1883201. https://doi.org/10.3389/fbael.2026.1883201

Image Credits: AI Generated

DOI: 10.3389/fbael.2026.1883201

Keywords: battery management system, electric vehicles, lithium-ion batteries, machine learning, artificial intelligence, state of charge, state of health, deep learning, thermal management, predictive maintenance, FPGA, IoT

The motivation is fundamentally computational. Traditional software simulations of large-scale brain networks, typically run on general-purpose CPUs or GPUs, are powerful but slow, energy-hungry, and rarely capable of true real-time performance when thousands of interconnected neurons must exchange spikes continuously. The Chinese team, led by Chuanguang Wang and corresponding authors Xiaotian Pan and Fang Zheng, argues that this bottleneck matters clinically: if researchers ever want brain-machine interfaces or closed-loop anesthetic delivery systems that respond to a patient’s brain state as it unfolds, the underlying model must run at biological speed. FPGAs, with their massive parallelism, deterministic timing, low latency, and exceptional energy efficiency, offer a way to map the structure of a neural network directly onto digital hardware rather than simulating it sequentially in software.

The network itself is biologically grounded. It comprises 10,000 spiking neurons divided in the same 4:1 ratio found in the neocortex: 8,000 excitatory neurons and 2,000 inhibitory ones. Each neuron obeys the Izhikevich model, a two-dimensional system of differential equations celebrated for reproducing realistic firing patterns at a fraction of the computational cost of biophysically detailed Hodgkin-Huxley models. The excitatory population is tuned for regular spiking behavior, while the inhibitory neurons are configured for fast spiking, mirroring the principal cell types of the mammalian cortex. Rather than connecting neurons randomly, the team mapped them onto a two-dimensional spatial grid and defined connection probability as an exponentially decaying function of physical distance, capturing the wiring economy that real brains exploit to minimize axonal length while preserving integration.

That spatial realism came with a hard engineering constraint. To fit the entire connectivity matrix within the FPGA’s on-chip Block RAMs and avoid the severe latency penalties of external DRAM, the researchers aggressively bounded the spatial decay, yielding a sparse topology of exactly 68,608 physical synapses across the network, an average of roughly 6.86 synapses per neuron. The decay constant was not chosen arbitrarily; it was analytically derived from percolation theory to guarantee that the network forms a single giant connected component without isolated sub-graphs. The team is candid that this extreme sparsity is a hardware-necessitated abstraction rather than a biological replica, and it forced a compensating choice: the simulated awake state settles at an artificially elevated firing rate of around 20 Hz, far above the sparse 2-5 Hz typical of in vivo cortical recordings, because a massively reduced point-neuron population needs that synthetic excitability to sustain network criticality and prevent spontaneous activity from collapsing entirely.

With the network in place, the researchers turned it into an anesthesia laboratory. Drugs such as propofol do not uniformly silence neurons; they disrupt the balance of excitation and inhibition, most commonly by enhancing GABAergic inhibition, prolonging inhibitory postsynaptic currents, and hyperpolarizing target neurons. The team captured this pharmacology by dynamically modulating two parameters: the inhibitory synaptic decay time constant and the absolute magnitude of inhibitory synaptic weights. In the baseline awake state, the network fires asynchronously at high rates. As the simulated anesthetic concentration increases, prolonged inhibitory kinetics force the population into a synchronized oscillatory regime, visible in raster plots as distinct vertical bands of collective firing that mimic the slow-wave dynamics characteristic of light general anesthesia. At the deepest simulated state, overwhelming inhibition combined with reduced excitatory background drive suppresses firing below 1 Hz, reproducing the profound attenuation of cortical dynamics seen before major surgery.

The spectral analysis is where the model’s clinical relevance becomes tangible. The researchers computed a surrogate local field potential, a temporally smoothed population spike count, and examined its power spectral density across the three states. In the awake condition, relative delta-band power (0.5-4 Hz) accounted for a mere 0.01 percent of total spectral power. Under light anesthesia, enhanced GABAergic influence synchronized the network and pushed relative delta power up to 2.86 percent. In deep anesthesia, slow waves dominated, with the delta band contributing 8.28 percent of spectral power. That monotonic surge of low-frequency power closely mirrors the spectral trends observed clinically during general anesthesia, where delta-band dominance serves as a recognized marker of anesthetic depth. The authors are equally explicit about what the model cannot do: because it implements an isolated intracortical network without thalamic inputs, it cannot reproduce the prominent alpha-band rhythms that thalamocortical loops generate during light anesthesia, and its surrogate LFP is a mesoscopic proxy rather than true clinical EEG.

Perhaps the most striking result comes from statistical physics. Accumulating evidence suggests the awake cortex operates near a critical phase transition, an optimal regime for information processing, and a hallmark of that state is the emergence of neuronal avalanches, cascades of spontaneous spiking whose size distribution follows a power law with a critical exponent near 1.5. The team extracted avalanches from their simulated network and found exactly that: in the awake state, the size distribution followed a power law with an exponent of 1.492 (95 percent confidence interval 1.481-1.503), and a power-law model outperformed an exponential alternative with R-squared above 0.999. As simulated anesthesia deepened, the power law broke down, an exponential cutoff emerged in the distribution tail, and the branching parameter declined monotonically from roughly 1 toward markedly lower values. In effect, the chip demonstrates mechanistically how anesthetic agents extinguish the brain’s critical dynamic equilibrium, fragmenting the large-scale cascades that integrate cortical activity.

The hardware engineering is as notable as the neuroscience. Rather than instantiating 10,000 discrete neuron circuits, which would cause prohibitive routing congestion, the architecture time-multiplexes a shared, deeply pipelined compute core across all neurons, exploiting the FPGA’s 100 MHz clock to update every state variable within a fraction of a biological millisecond. Constant multiplications in the Izhikevich equations were replaced by arithmetic shift-and-add operations, producing a nearly multiplier-less datapath that consumes just 4 of the chip’s 840 DSP slices. Fixed-point arithmetic, 24-bit Q8.16 format for membrane potentials and 16-bit Q4.12 for synaptic weights, halved the memory footprint without degrading dynamics. Spike routing is event-driven: when a neuron crosses the 30 mV threshold, only its index enters a FIFO, and a compressed sparse row structure fetches just the active synaptic destinations. The full implementation occupies less than 2 percent of the Kintex-7 FPGA’s logic resources, 25 percent of its Block RAM, and an estimated 1.24 W of power, roughly 12.5 picojoules per synaptic operation.

Timing analysis confirms the real-time claim. The worst case occurs during the highly active awake state, when about 235 neurons spike per biological millisecond; even then, the complete compute-and-route cycle consumes 11,847 clock cycles, finishing a biological millisecond in just 118.5 microseconds, roughly 8.4 times faster than real time. In suppressed deep-anesthesia states, routing cycles collapse further. Crucially, the fixed-point hardware was validated against its floating-point software counterpart through a closed-loop, self-checking testbench in which both systems started from identical states and were compared cycle by cycle. Across awake, light, and deep anesthesia benchmarks, firing rate errors stayed within 1.3 to 1.6 percent, and Pearson correlations exceeded 0.98 at both the population level and in single-neuron membrane potential trajectories, demonstrating that hardware efficiency was achieved without sacrificing scientific accuracy.

The authors stress that the system has been validated only against software simulations, not clinical EEG or patient data, so direct clinical deployment remains a future objective. But the framework points toward three concrete applications: depth-of-anesthesia monitoring, where the model could provide biophysically plausible ground truth for testing EEG-based indices; closed-loop anesthesia control, where real-time neuromorphic execution would let engineers prototype adaptive drug delivery controllers in a safe in-silico environment; and education, where the platform links synaptic-scale drug mechanisms to network-level clinical signatures. Future work will focus on integrating clinical EEG data to calibrate the network in real time and expanding the architecture to multi-regional brain simulations, potentially scaling from 10,000 to 100,000 neurons by instantiating four parallel compute cores. If that calibration succeeds, the path from a silicon chip replaying anesthesia to smarter, safer operating rooms may prove shorter than anyone expected.

Subject of Research: Large-scale neuromorphic modeling of cortical networks on FPGA for investigating anesthetic-induced neural dynamics

Article Title: Large-scale neuromorphic modeling of cortical networks on FPGA for investigating anesthetic-induced neural dynamics

Article References: Wang, C., Pan, X., Chen, S., Cheng, H., Yao, Y., Zhang, G., & Zheng, F. (2026). Large-scale neuromorphic modeling of cortical networks on FPGA for investigating anesthetic-induced neural dynamics. Frontiers in Systems Neuroscience, 20, Article 1866947. https://doi.org/10.3389/fnsys.2026.1866947

Image Credits: AI Generated

DOI: 10.3389/fnsys.2026.1866947

Keywords: Large-scale, neuromorphic, modeling, cortical, networks, FPGA, investigating, anesthetic-induced, neural, dynamics, scientific research

Spiking neural networks differ fundamentally from the conventional artificial neural networks behind today’s machine-learning boom. Instead of passing continuous values between layers, they communicate through discrete spike events and incorporate temporal dynamics into their neuron models, a scheme far closer to biological neural processing. Because their activity is sparse, event-driven hardware can skip unnecessary computation and data movement, which makes them attractive for real-time inference on energy-constrained devices. Yet the Madrid team is careful about the hype: the efficiency advantages depend strongly on network architecture, encoding method, workload and implementation platform, and cannot simply be assumed for every application. Real energy savings, they stress, must be demonstrated with physical implementations rather than inferred from spike sparsity alone.

The gap between software and silicon is where most spiking projects stall. A broad ecosystem of libraries, many built on PyTorch, can simulate and train spiking networks, but moving a trained model onto hardware typically requires a separate design flow. Engineers must decide on data representation, neuron and synapse organization, memory allocation, communication schemes and temporal execution before a synthesizable circuit emerges. Existing frameworks that partially automate this translation differ in their input representations, supported neuron models, synthesis methodologies and dependence on vendor-specific tools, leaving a need for accessible workflows that keep the software model connected to the generated hardware while allowing the result to be inspected and customized at the hardware-description level.

ReSNNance attacks this problem with a Python-based workflow. Users define the network architecture, neuron parameters, numerical precision and target configuration, and the framework generates the corresponding hardware modules, parameter files and interconnections. Internally, a network is represented as a Model composed of an ordered sequence of Layer objects, each linked to a parameterized VHDL template. During compilation, the toolchain maps the network topology, trained weights and additional parameters onto these templates and stitches the modules together sequentially using a network-level template, producing a standalone synthesizable implementation. The Jinja template engine substitutes network parameters and structural information into the hardware templates, and the framework can even generate build environments for synthesis with AMD Vivado and simulation with GHDL.

The current implementation supports sequential feed-forward networks built from fully connected Dense layers, two-dimensional Conv2D layers and average-pooling layers, all based on a simplified fixed-point leaky integrate-and-fire (LIF) neuron whose decay behavior is configured through an integer parameter. A distinctive feature is the input-conversion layer, which transforms non-spiking inputs such as images into spike trains through discrete-time stochastic rate encoding. The circuit stores 8-bit fixed-point input values in RAM and, at each simulation time step, performs a Bernoulli trial: a pseudorandom number generated by a low-resource linear feedback shift register (LFSR) is compared against a probability threshold proportional to the input pixel value, producing a spike whenever the random value falls below the threshold. This scheme approximates a homogeneous Poisson process while consuming minimal hardware resources.

Connecting the framework to the training world required solving a subtle software-hardware mismatch. Networks are trained in SpikingJelly, a PyTorch-based environment for defining, training and simulating spiking models, but the standard SpikingJelly LIF neuron does not directly reproduce the update order and parameterization of the simplified LIF neuron in the ReSNNance hardware templates. SpikingJelly expresses decay with a real-valued time constant, whereas the hardware uses an integer parameter, and the order in which synaptic integration and membrane-potential decay are applied differs. The team therefore developed a hardware-equivalent neuron class, RsnnNode, that inherits from the SpikingJelly base node and implements the hardware-compatible update through its neuronal_charge function, ensuring the software model follows the same numerical update employed by the generated VHDL. A corresponding BlockContainer pairs each synaptic layer with an RsnnNode and provides a conversion function that generates the ReSNNance layer representation, carrying over trained weights, neuron parameters and connectivity information.

Before synthesis, the generated hardware was functionally verified through VHDL simulation using self-checking testbenches. Deterministic input spike trains and quantized parameters were applied to both the ReSNNance software model and the generated VHDL implementation, and their output spike trains were compared cycle by cycle over 25 simulation time steps across representative layer sizes, convolutional kernels and numerical formats. No mismatches were observed between software and VHDL output spike trains for any evaluated configuration, a result the authors regard as essential evidence that the automatic translation preserves the trained model’s behavior exactly.

The first case study, a spiking LeNet-5 convolutional network, demonstrated the seamless integration of fully connected, convolutional and pooling hardware modules into a complete architecture. Weights were quantized to signed 8-, 6- and 4-bit representations, revealing clear design trade-offs. Reducing precision from 8 to 6 bits cut look-up table and flip-flop utilization by roughly 12 percent with only a 0.20 percentage-point drop in accuracy, from 99.06 to 98.86 percent. At 4 bits, resource utilization fell by about 35 percent for LUTs and 26 percent for flip-flops while the maximum operating frequency rose by nearly 23 percent to 356.9 MHz, at the cost of a 0.89 percentage-point accuracy reduction. Remarkably, none of the configurations required dedicated DSP blocks or block RAM: because synaptic contributions are accumulated upon spike arrival rather than computed through multiply-accumulate operations, the event-driven architecture eliminates the need for dedicated arithmetic resources, mapping weights and neuron states to distributed logic instead.

The second case study pushed the framework to its limits with a large fully connected network containing 1,237,152 weights, arranged as 784-784-784-10 to match the MNIST input dimensions. Hidden layers were added progressively until the available FPGA resources were exhausted. At 8-bit precision, the implementation occupied 88.50 percent of the device’s look-up tables while maintaining 98.52 percent classification accuracy. Quantization again proved powerful: dropping to 4-bit weights halved LUT utilization and raised the maximum operating frequency to 192.4 MHz with only a 0.34 percentage-point accuracy penalty. Power analysis, based on switching activity captured from post-implementation simulation with real MNIST samples, showed logic power falling from 750 milliwatts at 8-bit precision to 307 milliwatts at 4 bits, while static device power remained nearly constant at around 620 milliwatts. Complete inference over 25 simulation time steps required just 416.7 microseconds for this network, and 3675.7 microseconds for the LeNet-5 pipeline.

Compared with existing FPGA-based spiking frameworks such as NeuroFlow, SyncNN, E3NE and Spiker+, ReSNNance stands out for compiling models directly from a Python front-end into plain synthesizable VHDL without relying on high-level synthesis or hand-crafted RTL libraries, and for being the only evaluated framework whose implementations rely exclusively on distributed memory. The authors acknowledge limitations: the current version supports only sequential feed-forward architectures with a simplified LIF neuron, recurrent connections and alternative neuron models are not addressed, and all results were obtained on a single FPGA device with the AMD Vivado toolchain. The practical network size remains constrained by the resources, routing capacity and timing characteristics of the target device. Still, the modular organization provides a basis for incorporating additional hardware templates, neuron models, layer types and memory architectures without changing the core software-to-VHDL approach. For researchers exploring neuromorphic edge computing, ReSNNance offers a practical path from software-defined spiking models to functional silicon, with the generated VHDL remaining readable and configurable so hardware designers can inspect, modify and integrate the circuits into larger systems.

Subject of Research: Neuromorphic Computing

Article Title: ReSNNance: an HDL generation framework for spiking neural networks

Article References: López-Asunción, S., Bermúdez-Martín, C., Ituero, P., & Lopez-Vallejo, M. (2026). ReSNNance: an HDL generation framework for spiking neural networks. Frontiers in Neuroscience, 20, Article 1958451. https://doi.org/10.3389/fnins.2026.1958451

Image Credits: AI Generated

DOI: 10.3389/fnins.2026.1958451

Keywords: spiking neural networks, FPGA, VHDL, neuromorphic computing, edge computing, ReSNNance, hardware generation, generation, framework, spiking, neural, networks

The device, called a self-powered angular displacement sensor (SPADS), is built on the triboelectric nanogenerator, or TENG, a technology first introduced by Wang and colleagues that converts mechanical friction into electrical signals through contact electrification. TENG-based sensors have already found roles in energy harvesting, vibration detection and flow monitoring, prized for their simple structure, low cost and broad material adaptability. But when it comes to measuring displacement, TENG sensors have long faced a frustrating trade-off: improving resolution traditionally requires narrower electrodes and denser electrode grids, which in turn weakens the output signal and forces the sensor to grow larger to compensate.

The SPADS breaks this deadlock by borrowing a trick from an entirely different measurement tradition: time-grating technology. Instead of subdividing electrodes ever more finely, the researchers transform the angular position information into the phase of a traveling wave. The sensor consists of a stator and a rotor, both manufactured with standard printed circuit board techniques. Ten dual-sinusoidal copper electrodes, each spanning an 18-degree fan angle, are patterned on the rotor, while the stator carries forty annular fan-shaped electrodes with 8-degree sectors separated by 1-degree gaps. A thin PTFE film covers the stator, serving both as protection and as the high-performance triboelectric material that generates charge during sliding.

As the rotor turns, charge on its copper electrodes attracts opposite charges to the upper surface of the PTFE film, while the stator electrodes compensate through charge flow in the external circuit. The induced potential is proportional to the coupling area between rotor and stator electrodes, and because the rotor electrodes are shaped as sinusoids, the resulting signals vary smoothly as sine waves with rotation angle. Every four stator electrodes are wired together to form one of four output channels, and two non-adjacent channels produce a pair of sinusoidal signals that are spatially orthogonal—offset by exactly 90 degrees of phase.

The clever part comes in the signal processing. The two orthogonal sinusoids are multiplied by a pair of high-frequency reference signals and then summed, producing a traveling wave whose phase encodes the rotor’s angular position. This spatial-to-temporal conversion means that resolution is no longer dictated by electrode width. Instead, it depends on how finely the phase difference between the traveling wave and the reference can be timed. The signals are converted to square waves by comparators and fed into an FPGA with a 50 MHz crystal oscillator, which counts clock pulses between rising edges to determine the phase. With ten pole pairs and a 5 kHz modulation frequency, the theoretical resolution works out to just 5.18 arcseconds—remarkable for a device with no external power supply.

The team validated the design through extensive simulation and laboratory testing. Finite element modeling in COMSOL confirmed the analytical capacitance model, showing how the open-circuit voltage varies sinusoidally with position. The simulations also guided optimization: thinner PTFE films yield stronger output because less charge is trapped within the dielectric, while wider electrodes boost voltage at the cost of resolution. The researchers settled on an 8-degree electrode width as a balance, noting that similar output can be recovered by lengthening the electrodes radially without sacrificing angular precision.

Performance testing with a servo motor and a Keithley 6514 electrometer revealed the sensor’s characteristics across speeds and loads. Open-circuit voltage proved largely independent of rotational speed, since it depends only on the coupling area, while short-circuit current rose with speed—reaching peaks of 0.0042, 0.0089 and 0.0119 microamperes at 10, 20 and 30 rpm respectively. Under a 5-gigohm load, the sensor delivered a peak voltage of 3.64 volts, and output power peaked at roughly 9 nanowatts near 2 gigohms. A 3600-second stability test showed the output voltage remained essentially unchanged throughout, demonstrating robust long-term operation.

Measurement accuracy was assessed over full rotations at various speeds, with the sensor tracking complex motion sequences including reversals, pauses and speed changes. The maximum error stayed within ±716 arcseconds across the entire 360-degree range, with repetitive positioning errors of ±0.352 degrees under uniform motion and ±0.278 degrees under reciprocal motion. The error distribution showed a periodic pattern tied to the cyclic electrode arrangement but no systematic accumulation. The output frequency also tracked rotational speed with a correlation coefficient of 0.9998, confirming the signal’s suitability for precise angle computation.

How does this stack up against the competition? Conventional optical encoders achieve sub-arcsecond to arcsecond resolution but demand external power and occupy moderate to large diameters. Brushless resolvers offer accuracies in the tens to hundreds of arcseconds but require AC excitation and draw more power in larger volumes. Among TENG-based displacement sensors, the comparison is even more striking. The researchers introduce a metric called the resolution conversion rate—the ratio of resolution to electrode width—and the SPADS achieves a value of 1.8×10⁻⁴, orders of magnitude better than previous devices ranging from 0.03 to 1.6. In plain terms, it extracts far more angular precision from a given electrode size than any prior triboelectric sensor.

The implications reach well beyond the laboratory bench. For industrial robotic arms, humanoid robots and UAVs where every gram and every milliwatt counts, a sensor that generates its own signal while resolving rotation to arcseconds could reshape how motion feedback is designed. The SPADS demonstrates that the long-standing tension between resolution and output in triboelectric sensing can be dissolved not by cramming in more electrodes, but by shifting the measurement into the time domain—a conceptual leap that may well define the next generation of self-powered machine perception.

Subject of Research: A self-powered angular displacement sensor based on a triboelectric nanogenerator with time-grating signal processing for high-resolution rotation measurement.

Article Title: A High‐Resolution Self‐Powered Angular Displacement Sensor Based on Triboelectric Nanogenerator With Time‐Grating

Article References: Wang, S., An, D., Liu, S., & Wu, Z. (2026). A High‐Resolution Self‐Powered Angular Displacement Sensor Based on Triboelectric Nanogenerator With Time‐Grating. Advanced Science, 13(56), Article e76634. https://doi.org/10.1002/advs.76634

Image Credits: AI Generated

DOI: 10.1002/advs.76634

Keywords: triboelectric nanogenerator, angular displacement sensor, self-powered sensor, time-grating, robotics, unmanned aerial vehicles, PTFE, FPGA, phase modulation, motion control, encoders, energy harvesting

ML-KEM, standardized in NIST’s FIPS 203 and derived from the CRYSTALS-Kyber scheme, is the flagship lattice-based key-encapsulation mechanism intended to replace vulnerable key-exchange methods in the quantum era. Its mathematical security rests on the hardness of the Module Learning With Errors problem, a lattice problem believed to resist attacks even from large-scale quantum computers. But mathematical security is only as strong as the hardware that implements it. Side-channel analysis exploits physical observables, such as power consumption, electromagnetic emissions, or timing variations, to extract secret information without ever attacking the underlying mathematics directly.

The Tsinghua team, led by Munkhbaatar Chinbat with Liji Wu, Xiangmin Zhang, and Munkhnar Khulan, targeted the Number Theoretic Transform, or NTT, the arithmetic engine at the heart of ML-KEM. The NTT is a fast polynomial multiplication technique that converts secret coefficients into a transformed domain where multiplication becomes efficient. During decryption key generation, the secret vector is sampled from a centered binomial distribution and immediately transformed into the NTT domain before being stored. That transformation, the researchers realized, is a rich source of exploitable leakage because it processes every secret coefficient through well-defined, repetitive butterfly operations.

The structure of the first NTT round is what makes the attack possible. The transform operates on 256 coefficients arranged into 128 pairs, and in the first round every pair is processed with the same public twiddle factor. This means the power signature of each butterfly operation depends almost entirely on the secret input values, not on public data that could mask the leakage. Because the team’s accelerator processes coefficient pairs sequentially, the leakage from each pair occupies a distinct, predictable window in time, allowing an attacker to cleanly separate the fingerprints of all 128 pairs from a single recording.

To build their experimental platform, the researchers implemented a deliberately naive NTT accelerator on a Xilinx Artix-7 FPGA hosted on a CW305 board, using a ChipWhisperer-Lite for power trace acquisition. The design uses a single butterfly unit, a finite state machine controller, shared memory, and standard Montgomery and Barrett reduction techniques for modular arithmetic, mirroring the reference implementation of Kyber. The accelerator runs at 8.5 megahertz while the ADC samples power at roughly 105 million samples per second, with each trace capturing 20,000 sample points covering the entire first NTT stage. The minimalist design required only 743 lookup tables, 403 registers, one DSP block, and one block RAM, trading speed for simplicity and analyzability.

The attack methodology unfolds in two phases. In the profiling phase, the attacker trains on a clone device with known inputs. The team collected 100,000 power traces, using 80,000 for building statistical templates and 20,000 for the attack itself. Before any modeling, they applied the Test Vector Leakage Assessment, a statistical t-test comparing fixed versus random inputs, to pinpoint the exact time samples where secret-dependent information leaks. Any sample where the t-statistic exceeded 4.5 in absolute value, corresponding to a confidence level of 99.999 percent, was flagged as a point of interest. For each of the 128 coefficient pairs, these points were then compressed using principal component analysis, reducing thousands of raw samples to a handful of informative features.

Classification then proceeds via Mahalanobis distance, a statistical measure that accounts for the covariance structure of the leakage data. For every possible coefficient value pair, the profiling phase stores a mean vector and covariance matrix describing what its power signature typically looks like. During the attack, an unknown trace is compared against all templates, and the closest match reveals the secret coefficients. The results were striking: classification accuracy ranged from 96.93 to 97.97 percent across all 128 coefficient pairs, with an average near 97.4 percent. Notably, this classical statistical approach outperformed the team’s earlier deep-learning experiments with multilayer perceptrons, convolutional networks, and recurrent networks, which topped out at 96.64 percent accuracy.

Single traces, however, were not always sufficient. The team’s overlap analysis showed that only a small fraction of individual traces classified all 128 pairs correctly in one shot, since certain coefficient combinations, such as symmetric pairs like (1, -1) and (-1, 1), produce nearly identical power signatures. The solution is likelihood aggregation: by accumulating classification evidence across multiple decapsulation operations, the correct values emerge statistically. The guessing entropy analysis, which measures the expected rank of the correct answer among all candidates, dropped from 11.15 with 150 traces to just 1.09 with 10,000 traces, confirming that the templates converge rapidly toward certainty. Across 734 successful recovery trials, the number of traces needed for full polynomial recovery ranged from 7 to 92, with a mean of 27.3 and a median of 23.

The findings place ML-KEM hardware in a sobering context. Previous research had already demonstrated that software implementations on Cortex-M4 processors leak enough information for full key extraction with as few as 8 to 960 traces, and that masked and shuffled implementations can be broken with single traces when fault injection is combined with side-channel analysis. The new work extends this vulnerability picture to lightweight FPGA accelerators, showing that even a minimal, sequential NTT design without any countermeasures is effectively defenseless against a well-resourced profiling attacker. Because ML-KEM’s secret key consists of multiple polynomials, three for ML-KEM-768 and four for ML-KEM-1024, full key recovery simply requires repeating the polynomial-level attack for each component.

The researchers emphasize that their attack targets an unprotected design, and that more sophisticated architectures using parallelism or pipelining may present a smaller attack surface by blurring the temporal correlation of leakage. Still, the message for the post-quantum transition is clear: theoretical quantum resistance means nothing if the hardware leaks. The team proposes countermeasures including physically unclonable function-based address shuffling and higher-order masking, and points toward hybrid attacks that would feed template-attack likelihoods into belief-propagation frameworks such as Soft Analytical Side-Channel Attacks to reduce the trace requirements even further. As ML-KEM deployment accelerates across browsers, banks, and national infrastructure, the study serves as a warning that securing the mathematics is only half the battle; the silicon running it must be hardened against the whispers of its own power supply.

Subject of Research: A template-based side-channel attack recovering ML-KEM decryption keys from power leakage of an FPGA NTT accelerator

Article Title: A Template attack for decryption key recovery on the NTT accelerator of PQC ML-KEM

Article References: Chinbat, M., Wu, L., Zhang, X., & Khulan, M. (2026). A Template attack for decryption key recovery on the NTT accelerator of PQC ML-KEM. Cybersecurity, 9(1), Article 226. https://doi.org/10.1186/s42400-026-00675-3

Image Credits: AI Generated

DOI: 10.1186/s42400-026-00675-3

Keywords: ML-KEM, post-quantum cryptography, side-channel attack, template attack, Number Theoretic Transform, FPGA, power analysis, TVLA, principal component analysis, CRYSTALS-Kyber, decryption key recovery, NIST FIPS 203

The filter at the heart of the study is an extended Kalman filter, or EKF, the workhorse algorithm engineers use to estimate the state of a dynamic system from noisy measurements. The EKF works by linearizing the system’s motion model around the current estimate, predicting where the target should be, and then correcting that prediction with each new seeker measurement. For tracking problems with mild, well-behaved Gaussian noise, this recipe is remarkably effective. But real seeker data is rarely so cooperative. Glint effects, countermeasures, clutter, and abrupt target maneuvers all inject outliers—measurements that are wildly inconsistent with the statistical assumptions the filter relies on. A standard EKF treats every measurement as trustworthy, so a handful of bad readings can drag the state estimate far off course at precisely the moment accuracy matters most.

The researchers’ answer is to replace the filter’s least-squares cost function with the Huber cost function, a classic tool from robust statistics. The Huber function behaves like a quadratic for small residuals, where ordinary least squares is optimal, but switches to a linear penalty for large residuals. The practical consequence is that outlier measurements still influence the estimate, but their influence is capped rather than allowed to dominate. The resulting Huber-based extended Kalman filter, or HEKF, has been studied before in applications ranging from GPS navigation to spacecraft attitude estimation, and it consistently delivers more reliable estimates under non-Gaussian noise. The catch is computational: instead of a single closed-form update, the Huber formulation requires an iterative optimization loop that must converge on every filter cycle, multiplying the arithmetic workload by an order that embedded flight computers cannot easily absorb.

That bottleneck is what drove the team—Nayeon Kim, SeongJin Yoon, Heoncheol Lee of Kumoh National Institute of Technology, and Ikchan Lim, Changyeol Lee, and Jangseong Park of defense contractor LIGNEX1—toward hardware acceleration. Their target platform was an FPGA, a reconfigurable silicon chip whose logic fabric can be wired into custom digital circuits. Unlike a CPU, which executes instructions sequentially on a handful of cores, an FPGA can instantiate hundreds of arithmetic units that all operate in parallel, each one dedicated to a specific piece of the algorithm. For an iterative filter that must complete its entire predict-and-correct cycle within the tight timing budget of a seeker’s sampling rate, that architectural difference is decisive.

The centerpiece of the implementation is a custom intellectual property block, or IP core, built specifically to evaluate the Huber function and the iterative minimization it drives. Rather than letting a general-purpose processor grind through the optimization in software, the designers encoded the Huber computation directly into hardware datapaths, pipelined so that successive iterations and matrix operations overlap in time. The result is high-throughput, low-latency execution of the very step that makes the HEKF so expensive. In their evaluation, the Huber IP alone ran 6.79 times faster than the same computation on the processing system—the ARM-class CPU portion of the system-on-chip—while the complete HEKF, with the Huber core integrated into the filter pipeline, achieved an overall 3.71-fold acceleration.

Speed means little if accuracy collapses, so the team benchmarked the hardware implementation against the software version on denoising performance and estimation accuracy. The two proved comparable: the FPGA version preserved the robust filter’s ability to suppress measurement noise and track the line-of-sight rate through the nonlinear, outlier-ridden conditions that motivated the design in the first place. In other words, the researchers did not trade estimation quality for throughput; they simply removed the computational excuse for not using the more robust algorithm in real time. For guidance engineers, that is the crucial result, because it means the theoretically superior filter can finally be flown, not just simulated.

The work fits into a broader and rapidly accelerating trend of moving onboard aerospace algorithms from processors into reconfigurable hardware. Previous studies from overlapping research groups have parallelized particle filters and particle swarm optimization on FPGAs for ballistic target tracking, and accelerated convolutional neural network inference for routing in low-Earth-orbit satellite networks. GPU acceleration has been explored for related problems, including model predictive control in integrated missile guidance systems, but FPGAs hold particular appeal for flight hardware because they combine deterministic timing with low power consumption and resistance to the software overheads that plague general-purpose platforms. Comparisons of FPGA, CPU, GPU, and ASIC acceleration for neural network workloads have repeatedly highlighted the FPGA’s sweet spot: customizable parallelism without the fabrication cost of a fixed application-specific chip.

What makes the new study technically interesting is the marriage of robust estimation theory with register-transfer-level design. Kalman filtering on FPGAs is not new in itself—researchers have built hardware accelerators for EKF-based simultaneous localization and mapping, battery state estimation, and other applications—but the Huber variant introduces an iterative inner loop that resists naive parallelization. Each iteration depends on the previous one, so the designers must pipeline carefully, reusing hardware for matrix operations while keeping the convergence loop tight. The custom Huber IP solves this by treating the optimization as a dedicated hardware subroutine, effectively giving the filter a silicon-fast engine for the one part of the algorithm that software cannot execute quickly enough. The approach builds on the team’s earlier 2025 work on parallelized Huber-based EKF implementations, refining it into the present system-level evaluation.

The practical implications extend beyond missiles. Any platform that must estimate the state of a fast, maneuvering, poorly characterized target from noisy sensors faces the same trade-off between robustness and compute budget: drones tracking ground vehicles, radar systems following debris, autonomous vehicles fusing lidar returns, and spacecraft determining attitude in the presence of faulty star tracker readings. A hardware recipe that makes robust filtering affordable in real time is a template that transfers across those domains. The Korean work was funded by the Defense Acquisition Program Administration through the Korea Research Institute for Defense Technology Planning and Advancement, under a program developing design technology for an integrated guidance and control simulator incorporating weapon datalink and seeker systems—signaling that the intended path from laboratory FPGA board to operational guidance hardware is already mapped.

There remain, of course, the usual caveats of early hardware research. The reported speedups were measured against the processing system of the development platform, and further gains will depend on floating-point precision choices, clock rates, and how much of the remaining filter arithmetic migrates into custom logic. Certification of reconfigurable hardware for safety-critical flight systems carries its own regulatory burden. But the direction of travel is unmistakable. As seekers grow more capable and targets grow faster, the algorithms that keep interceptors on course are becoming too computationally demanding for conventional processors alone. By proving that a robust, outlier-resistant Kalman filter can run in hardware at full seeker speed—3.71 times faster than before, with accuracy intact—this study offers a concrete glimpse of where real-time guidance computing is headed: away from software loops and into the fabric of the chip itself.

Subject of Research: FPGA hardware acceleration of a Huber-based extended Kalman filter for robust real-time line-of-sight target tracking

Article Title: FPGA Implementation of Huber-Based Extended Kalman Filter for Real-Time High-Speed Target Tracking

Article References: Kim, N., Yoon, S., Lee, H., Lim, I., Lee, C., & Park, J. (2026). FPGA Implementation of Huber-Based Extended Kalman Filter for Real-Time High-Speed Target Tracking. International Journal of Aeronautical and Space Sciences. https://doi.org/10.1007/s42405-026-01216-5

Image Credits: AI Generated

DOI: 10.1007/s42405-026-01216-5

Keywords: FPGA, extended Kalman filter, Huber function, target tracking, missile guidance, line-of-sight rate, hardware acceleration, robust estimation, embedded systems, parallelization, seeker, real-time computing