Modern artificial intelligence systems are extraordinarily powerful, but much of their energy and time can be consumed moving data rather than performing calculations. In conventional computing architectures, sensory inputs and intermediate results must travel repeatedly between processors and external memory. This separation is especially costly for neural networks, which perform large numbers of mathematical operations on streams of data and often need to preserve information about what happened moments or even minutes earlier. The human brain takes a different approach. Neurons both process signals and maintain internal states, allowing computation and memory to coexist across densely interconnected networks. FLARE, short for a fully in-memory photonic computing architecture, is designed around a similar principle: sensing, processing and memory are integrated into the same computing fabric rather than treated as isolated stages.

The system combines photonic and electronic mechanisms to create what the researchers describe as reconfigurable photonic neurons. Photonic computing uses light to carry and manipulate information, an approach that can exploit the speed and parallelism of optical signals. Electronic components, meanwhile, can provide storage, control and nonlinear behavior that are difficult to implement efficiently with light alone. In FLARE, these mechanisms are coupled so that the artificial neurons can respond to incoming signals, transform them through a deep nonlinear neural network and preserve aspects of their previous activity. That memory is not a single, uniform function. The architecture supports both long-term and short-term dynamics, allowing it to retain learned or accumulated information while continuing to react quickly to new inputs.

This distinction between memory timescales is central to systems that must operate in changing environments. Short-term dynamics can help a machine interpret rapidly evolving signals, such as motion, acceleration or changing visual information. Long-term retention can preserve a more persistent internal state, allowing the system to use information gathered earlier rather than treating every new signal as an isolated event. The FLARE chip reportedly maintained long-term memory for 7.45 seconds while preserving short-term behavior in the gigahertz range. A gigahertz corresponds to a billion cycles per second, so the result represents a combination of sustained memory and extremely rapid signal dynamics. Rather than forcing a system to choose between storing information and processing it quickly, the architecture is intended to make both behaviors available within the same neural substrate.

At the physical level, the promise of photonic computing comes from the way light can propagate and interact across many channels at once. Optical signals can encode information in properties such as intensity, and integrated photonic circuits can perform transformations as light travels through carefully engineered structures. In a neural network, these transformations can represent the weighted combinations of inputs that form the basis of artificial-neuron computation. The critical challenge is that useful intelligence requires more than fast linear operations. Neural systems must also incorporate nonlinear responses, memory and adaptation. FLARE addresses those demands by combining optical processing with electronic mechanisms, creating neurons whose responses can be reconfigured and whose internal state can evolve over time. The result is not simply an optical accelerator attached to a conventional processor, but an attempt to merge the roles of memory, computation and sensing.

Scale is another important feature of the reported demonstration. The researchers built a monolithic multicore chip with 7,378 neurons, then arranged ten cores into a multilayer FLARE system for the autonomous-navigation experiment. A monolithic design places the relevant elements within a unified chip architecture, a step intended to reduce the bottlenecks that arise when separate components must exchange data. Multiple cores and layers allow the network to expand beyond a small laboratory proof of concept and to process information through a deeper neural structure. The architecture’s reconfigurability is also significant: a system designed to operate in the physical world must adjust to different inputs and tasks rather than relying on a fixed, one-purpose circuit. By integrating memory directly into the neural elements, FLARE is designed to keep intermediate activations close to where they are generated, limiting the costly movement of data through external digital memory.

The researchers tested the architecture in a setting that demands continuous interaction between perception and action: autonomous racing-drone navigation. A racing drone must interpret sensory information, explore its environment and adapt its behavior while moving rapidly through space. Conventional systems often divide these tasks among sensors, processors, memory and control units, creating delays and energy costs as information is repeatedly converted, transferred and processed. In the FLARE demonstration, the multilayer photonic system handled sensing, exploration and adaptation as parts of an integrated neural process. Its reported energy cost of 61.87 attojoules per operation illustrates the potential efficiency of performing computation in place. An attojoule is 10^-18 joules, an extraordinarily small unit of energy. The figure is reported at the system level, making it relevant to the complete demonstrated architecture rather than only to an isolated optical operation.

The most striking implication is that FLARE could help shift artificial intelligence away from the traditional sequence of “sense, store, compute and act.” In embodied systems such as drones, robots and autonomous vehicles, intelligence is inseparable from the physical world. Sensors generate continuous streams of data, and useful decisions depend on temporal context: what the machine detected earlier, how the environment is changing and whether a previous action produced the expected result. A network with integrated memory can preserve this context as part of its ongoing activity. A network that also processes signals photonicly could, in principle, handle high data rates without sending every intermediate result to a distant electronic memory. The combination may be particularly valuable where size, energy consumption and response time are tightly constrained.

The work nevertheless represents a pathway rather than a finished replacement for conventional artificial intelligence hardware. The reported results establish the architecture’s neuron count, memory retention, high-speed dynamics and autonomous-navigation demonstration, but practical deployment will depend on how such systems perform across a broader range of tasks and operating conditions. Photonic and electronic components must remain precisely coordinated, and large integrated neural systems must be manufactured, programmed and calibrated reliably. Memory that lasts several seconds may be useful for navigation, but different applications could require other timescales. Likewise, energy per operation is only one part of a system’s total cost; sensing, communication, control and training procedures also matter. These are engineering questions that will shape whether fully in-memory photonic systems can move from specialized demonstrations into everyday machines.

FLARE’s significance lies in the way it brings several long-standing ambitions together on one platform. It uses light for fast, parallel signal processing, electronics for memory and control, neural-network organization for nonlinear computation, and integrated architecture for direct interaction with sensory inputs. The resulting chip does not merely imitate the brain’s appearance; it targets a functional property that makes biological intelligence efficient: memory and computation are deeply intertwined. With thousands of photonic neurons, seconds-long retention, gigahertz-scale short-term dynamics and a low reported energy cost in drone navigation, the system offers a glimpse of machines that compute less by moving data and more by transforming information where it already exists. If the approach continues to scale, future autonomous devices could become faster, more adaptive and substantially more energy-efficient without relying on the memory bottlenecks that define much of today’s AI hardware.

As artificial intelligence systems become more powerful, the movement of data between processors and memory is emerging as one of the largest obstacles to performance. Modern AI workloads require enormous volumes of information to be transferred rapidly, yet conventional memory technologies struggle to keep up without consuming substantial energy. A research team at the Korea Advanced Institute of Science and Technology, or KAIST, has now developed a device structure designed to address one of the most persistent problems in three-dimensional memory: instability in vertically stacked semiconductor channels. By controlling the movement of oxygen at the nanoscale, the researchers have created an “oxygen-tunnel” architecture that could improve the speed, endurance and power efficiency of future AI chips.

The work focuses on oxide vertical channel transistors, or VCTs, a promising technology for increasing memory density beyond the limits of conventional planar designs. In a vertical channel device, electrical current flows through a semiconductor channel oriented vertically rather than horizontally. This architecture allows memory cells and transistors to be stacked in multiple layers, creating a three-dimensional structure that can hold more computing and storage elements within a smaller footprint. Such designs are particularly attractive for compute-in-memory systems, which perform calculations directly where data are stored instead of repeatedly moving information between separate memory and processor units.

The central challenge lies in the behavior of oxygen inside oxide semiconductors. These materials can contain oxygen vacancies, which are sites where oxygen atoms are missing from the crystal or amorphous structure. Although these vacancies may be useful in carefully controlled amounts, excessive or unstable concentrations can create unwanted electronic states, alter the transistor’s threshold voltage and increase leakage or variability. Over time, such defects can cause the electrical properties of the channel to drift, undermining the reliability required for memory and AI hardware. Supplying additional oxygen can compensate for these vacancies, but the solution creates another problem: oxygen may continue migrating beyond the channel and oxidize the nearby metal electrode.

That oxidation at the electrode interface can increase contact resistance, making it more difficult for current to enter and leave the transistor. The result is a fundamental materials trade-off. The semiconductor channel needs a controlled supply of oxygen to remain electrically stable, while the electrode must be shielded from the same oxygen to preserve a low-resistance connection. Conventional interlayer dielectric materials do not provide sufficient directional control, allowing oxygen to diffuse through regions where it can damage the device. KAIST researchers therefore designed a multilayer structure intended to guide oxygen toward the channel and block its movement toward the electrode.

The new structure consists of alternating layers of silicon nitride, silicon dioxide and silicon nitride, abbreviated as SiN/SiO₂/SiN. Rather than acting as a simple insulating barrier, this stack functions as a selective oxygen pathway. The researchers engineered the layers so that oxygen released from the interlayer dielectric could reach the oxide semiconductor, where it helps compensate oxygen vacancies, while its diffusion toward the metal contact was suppressed. The concept resembles a microscopic tunnel with a preferred direction of travel. By regulating the local chemical environment around the channel, the oxygen-tunnel architecture improves semiconductor stability without sacrificing the electrical quality of the electrode interface.

The researchers fabricated indium tin oxide vertical channel transistors incorporating the new structure and examined them using cross-sectional transmission electron microscopy. The imaging confirmed the formation of the intended SiN/SiO₂/SiN stack and showed a well-defined hole profile in the fabricated device. This structural evidence was important because the performance of vertically integrated transistors depends heavily on the precision of nanoscale layers and interfaces. Even small defects, irregularities or unintended diffusion paths can cause large changes in resistance, switching behavior and long-term reliability when thousands or millions of devices are combined in a memory array.

According to KAIST, the oxygen-tunnel transistors achieved high current density while also demonstrating strong data-retention characteristics. The devices maintained their performance during more than ten million cycles of severe electrical stress testing, with the threshold voltage shift remaining below 50 millivolts. Threshold voltage is the gate voltage required to switch a transistor into conduction, and changes in this value can cause a memory cell to be misread or an analog computation to become inaccurate. Limiting the shift to such a small value after repeated operation indicates that the new structure can withstand demanding workloads without the rapid electrical drift that has hindered oxide-based vertical devices.

The potential significance extends beyond memory density. In compute-in-memory hardware, transistors can be used not only to store information but also to perform operations such as multiplication and accumulation, which are fundamental to neural-network processing. These systems can reduce the energy lost when data travel back and forth between memory and a separate processor. The KAIST team evaluated the technology in combination with conventional silicon complementary metal-oxide-semiconductor circuitry and reported results suggesting that the oxide platform could improve the performance of monolithic three-dimensional compute-in-memory systems. Such integration could allow high-density memory layers to be placed directly above logic circuits, shortening interconnects and increasing the number of operations performed per unit of area.

The research was led by Hyeonho Gu, with Yongwoo Lee, Haksoon Jung and Jimin Kwon serving as corresponding authors, in collaboration with scientists from UNIST, Yonsei University, the Korea Research Institute of Chemical Technology, Seoul National University and other Korean institutions. Published in Advanced Functional Materials, the study presents oxygen migration control as a new route to solving reliability problems in vertically stacked oxide electronics. The paper, titled “Oxygen-Tunnel Indium Tin Oxide Vertical Channel Transistors with Enhanced Current Density and Reliability for Monolithic 3D Compute-In-Memory Systems,” was also selected as a Front Cover article. If the approach can be scaled to large arrays and integrated into manufacturing processes, it could help advance the ultra-low-power AI memory systems needed for increasingly data-intensive applications.

Subject of Research: Oxygen-tunnel indium tin oxide vertical channel transistors for reliable, high-density memory and monolithic 3D compute-in-memory systems.

Article Title: Oxygen-Tunnel Indium Tin Oxide Vertical Channel Transistors with Enhanced Current Density and Reliability for Monolithic 3D Compute-In-Memory Systems

Web References: https://doi.org/10.1002/adfm.202531989

References: Advanced Functional Materials, DOI: 10.1002/adfm.202531989

Image Credits: KAIST

Keywords

AI chips, three-dimensional memory, compute-in-memory, oxide semiconductors, vertical channel transistors, indium tin oxide, oxygen vacancies, oxygen migration, silicon nitride, silicon dioxide, semiconductor reliability, low-power computing

Modern AI systems rely on enormous numbers of calculations, often performed simultaneously across processors, memory components, and specialized accelerator chips. Traditionally, these components have been connected using packaging technologies that depend on microscopic metal bumps. Although micro-bumps have enabled major advances in chip integration, they occupy valuable space and limit how many electrical connections can be placed in a given area. As chiplets and three-dimensional architectures become more common, the physical distance between components must shrink while the number of communication channels rises. This creates a difficult engineering balance: designers need shorter pathways for faster data transfer, but they must also preserve signal quality, manufacturing accuracy, and reliable heat removal. The Science Tokyo team’s platform seeks to overcome these constraints by treating packaging, interconnection, and thermal behavior as parts of one integrated design problem.

The research was led by Specially Appointed Project Professor Norio Chujo of the WOW Alliance Heterogeneous and Functional Integration Research Unit at the Institute of Integrated Research, Institute of Science Tokyo, together with Researcher Hideki Kitada and Specially Appointed Project Professor Takayuki Oba. In presentations associated with the 2026 IEEE 76th Electronic Components and Technology Conference in Florida and the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits in Hawaii, the researchers described three technologies supporting the BBCube™ concept. These are a proprietary high-density chip-on-wafer process, a bumpless chip-interconnection method, and a thermal-analysis technique capable of examining heat behavior across a large chip at extremely fine resolution. The goal is not simply to stack more silicon, but to make the resulting system behave as a tightly coordinated computational platform.

One of the platform’s key elements is high-density chip-on-wafer integration. In this approach, individual chips are placed face down onto a wafer with high positional accuracy. According to the researchers, the process can reduce the spacing between adjacent chips to approximately 10 micrometers. That distance is comparable to the scale of many advanced semiconductor features, and achieving such placement accuracy is essential when thousands or millions of connections must align across chip boundaries. A smaller gap allows the interconnection region to be used more efficiently, reducing the physical separation that data signals must cross. For AI hardware, where processors may continuously exchange information with memory or neighboring chiplets, this type of close integration could help reduce communication delays and the energy required to move data through the package.

The second technology eliminates the conventional metal bumps used to connect chips. In the BBCube™ process, the researchers use via-last through-silicon vias, or TSVs. These are tiny vertical pathways that pass through silicon and are formed after the chips have been positioned. Instead of relying on arrays of solder or metallic bumps between components, the TSV-based structure creates direct vertical routes for electrical signals. Removing the bumps frees space for a much denser arrangement of connections and can simplify the geometric constraints imposed by traditional packaging. The resulting bumpless architecture is particularly relevant to heterogeneous three-dimensional systems, in which chips made with different processes or designed for different functions must operate together. It also provides a route toward increasing bandwidth without proportionally increasing the package footprint.

Analysis by the team indicates that combining the fine-pitch interconnections with highly accurate chip placement could deliver as much as 16 times greater aggregate signal bandwidth within the same interconnection area. The researchers report that this improvement can be achieved while maintaining signal quality comparable to conventional micro-bump-based designs. Signal quality is critical in high-speed systems because electrical interference, reflections, and losses can corrupt data as it travels between components. A denser connection layout is useful only if the signals remain reliable at the operating frequencies required by modern processors. By shortening the chip-to-chip distance and increasing the number of available pathways, the BBCube™ architecture is intended to move more data in parallel while avoiding the communication bottlenecks that can limit the performance of densely integrated AI hardware.

Greater density, however, brings a second major challenge: heat. Every switching transistor consumes energy, and much of that energy eventually becomes heat. When components are packed closely together, hot spots can form and thermal energy may struggle to escape. Excessive temperatures can reduce performance, increase power consumption, accelerate material degradation, and force processors to operate below their maximum capability. To address this problem, the researchers examined a waffle wafer structure designed to improve thermal behavior. Their simulations indicated that the structure could reduce thermal resistance by approximately 52 percent. Lower thermal resistance means that heat can travel more easily away from active regions, helping prevent localized temperature increases. For AI accelerators, which may run intensive workloads continuously, improved heat flow could be as important as faster electrical communication.

The team also developed a multiscale thermal-analysis method that can calculate heat distribution across an entire chip at a resolution of 1 micrometer. The analysis uses 100 million points, allowing researchers to examine thermal behavior from broad package-level patterns down to small local regions where hot spots may emerge. Conventional thermal simulations often require compromises between the size of the area studied and the detail that can be resolved. A model covering a complete chip may overlook microscopic variations, while an extremely detailed model may be too computationally expensive to use at system scale. The reported method is designed to bridge those levels, giving engineers a more complete picture of how heat moves through complex three-dimensional semiconductor structures. This could help identify weaknesses before a design reaches manufacturing.

The significance of BBCube™ lies in the combination of its three strategies rather than in any single packaging feature. Precise face-down chip placement establishes the geometric foundation, bumpless TSV interconnects provide dense vertical communication, and thermal analysis helps determine whether the integrated structure can operate safely under demanding workloads. The platform therefore targets three linked problems in advanced semiconductor engineering: how to place components closer together, how to exchange data rapidly across their boundaries, and how to prevent the resulting system from overheating. If the approach can be translated into scalable manufacturing, it could support smaller packages with greater communication capacity and more effective cooling. Such systems may become increasingly important as AI models grow larger and computing architectures become more heterogeneous.

The researchers emphasize that the work represents a platform for next-generation 2.5D and 3D integration, rather than a finished commercial processor. Its reported performance figures are based on the team’s analyses and demonstrations, and further development will be needed to evaluate manufacturing yield, long-term reliability, power consumption, and compatibility with different chip materials and production processes. Even so, the BBCube™ concept reflects a broader shift in semiconductor design: future gains may depend less on making a single chip larger and more on assembling specialized components into tightly coordinated systems. By bringing chips closer, increasing the density of their connections, and modeling heat at unprecedented detail, the Institute of Science Tokyo team has outlined a route toward compact AI accelerators and high-performance computers capable of handling more data without requiring correspondingly larger or less efficient hardware.

Subject of Research: Semiconductor packaging and heterogeneous 2.5D and 3D chip integration

Article Title: High-Density Chiplet Integration using Face-Down COW Processes with Bumpless Interconnects for Heterogeneous 3D Systems

News Publication Date: 3-Jul-2026

Web References: https://doi.org/10.1109/VLSITchnologyandCir65830.2026.11577472

References: IEEE/JSAP Symposium on VLSI Technology and Circuits, DOI: 10.1109/VLSITchnologyandCir65830.2026.11577472

Image Credits: Institute of Science Tokyo

Keywords

Artificial intelligence, AI accelerators, semiconductor packaging, chiplets, BBCube™, 3D integration, 2.5D integration, through-silicon vias, bumpless interconnects, thermal management, high-performance computing, electronics, semiconductor engineering

Six USC-linked projects were chosen for Genesis Mission funding this week, including three led directly by USC researchers. Collectively, the teams target major bottlenecks across energy, aviation, manufacturing, and computing: reducing energy usage in computation, improving access to critical materials, and enabling AI tools to solve problems that traditional modeling struggles to address at scale.

In one project, USC Viterbi electrical and computer engineering professor Massoud Pedram is pursuing Fast Phase Logic, a superconducting computing approach aimed at delivering higher performance with dramatically lower power demands. Instead of relying on bulky wiring structures used in earlier superconducting designs, Fast Phase Logic replaces those elements with compact, engineered components. The tighter integration allows more circuit elements to fit within the same chip area and lowers the operating current—steps that improve practicality and scalability.

Superconducting systems require extreme cooling to achieve near-zero electrical resistance. Yet designing such chips is difficult because the physics is complex and trial-and-error cycles can take years. Pedram’s team uses AI to predict component behavior and automates chip layout decisions, compressing design timelines while exploring architectures that could benefit edge computing, data-stream processing, and future quantum-control systems.

Another USC-led effort focuses on critical minerals. Karen Lloyd of USC Dornsife is developing AI models to infer where and how critical minerals become concentrated deep underground. The research integrates geological signals, underground fluid chemistry, naturally occurring gases, and microbial genomics—combining datasets in ways that can reveal patterns difficult to detect using conventional methods alone.

By merging geophysical imaging with subsurface modeling and AI, the project aims to improve estimates of mineral occurrence in geothermal systems and clarify the conditions that shape mineral distributions. The work brings together expertise from USC and partner institutions including Woods Hole Oceanographic Institution, the University of North Carolina at Chapel Hill, Oak Ridge National Laboratory, the University of Tennessee, Knoxville, and Georgia Tech.

A third project, led by USC Viterbi aerospace and mechanical engineering associate professor Iván Bermejo-Moreno, seeks to teach AI to predict turbulence using physical laws rather than relying solely on traditional mathematical turbulence models. Working with the University of Michigan and Argonne National Laboratory, the team trains AI models to recognize recurring flow structures—enabling faster and more accurate simulations of airflow and other complex physical processes.

If successful, the approach could support better design of aircraft, wind turbines, and engines, while broadening the use of physics-informed AI across science and engineering workflows.

Additional USC participation extends the Genesis Mission footprint through subaward and partner roles in three more projects, ranging from AI-ready excited-state materials datasets to multi-agent discovery frameworks for selective recovery from battery waste, and from hardware-speed decoding methods to accelerated scientific modeling pipelines.

Subject of Research: AI for scientific discovery (superconducting chips, turbulence prediction, critical mineral sourcing)
Article Title: USC Selected for DOE Genesis Mission AI Research Funding
News Publication Date:
Web References: https://today.usc.edu/usc-leads-national-ai-research-project-to-accelerate-scientific-discovery/ ; https://genesis.energy.gov/
References:
Image Credits:

Keywords: AI, superconducting computing, Fast Phase Logic, turbulence prediction, physics-informed machine learning, critical minerals, geothermal systems, geophysical imaging, multi-agent AI, DOE Genesis Mission

Traditional artificial intelligence hardware architectures typically bifurcate these essential functions—detection, memory retention, and processing—forcing data to shuttle between distinct components. This separation not only introduces latency but significantly amplifies energy consumption. The novel phototransistor developed by the OSU team disrupts this paradigm by embedding memory capabilities precisely where sensory inputs occur, vastly improving computational efficiency and speed.

Central to this device’s innovation is its ability to mimic the neurochemical processes governing memory strength and decay in the human brain. Rather than storing information with fixed permanence, the phototransistor utilizes trapped electrical charges generated by incident light to represent memories, which can then be pharmacologically tuned—via electrical gate voltages—to either reinforce or weaken these stored traces over time. This dynamic modulation reproduces the adaptive nature of biological synapses and opens unprecedented avenues for creating AI systems that can ‘forget’ as well as ‘remember,’ essential for real-time learning and adaptation.

Structurally, the device marries an oxide semiconductor acting as the electronic transistor channel with an organic photosensitive layer responsible for absorbing photons and generating charge carriers. The organic layer traps a subset of these carriers, creating a persistent local electric field even after illumination ceases. This trapped charge influences electron flow through the semiconductor channel, effectively encoding a memory of prior light exposure.

A key technical breakthrough lies in the device’s gate-tunable interface: by adjusting the voltage applied to the transistor’s gate terminal, researchers can manipulate the spatial positioning of trapped charges relative to the conduction channel at a nanoscopic level. This precise control modulates the strength of electrical interaction, allowing for programmable decay times of the optoelectronic memory—ranging from seconds to considerably longer durations. Such flexibility is vital for neuromorphic systems requiring adjustable time constants for processing temporal patterns.

The implications of this technology extend beyond simple visual sensing. By localizing both sensing and adaptive memory functions, the phototransistor can serve as a foundational building block for advanced vision systems capable of real-time data processing with exceptional energy efficiency. This novel hardware approach offers substantial improvements over conventional sensors, which often offload processing to centralized units, incurring latency and energy penalties.

Neuromorphic computing, a field striving to emulate the architecture and operational principles of the brain, stands to gain significantly from this development. The device’s capacity to embody synapse-like plasticity within a phototransistor embodies a leap toward systems that do not merely compute but adapt, learn, and optimize autonomously. Furthermore, the integration of these functionalities at the hardware level paves the way for compact, scalable AI platforms potentially transformative for robotics, autonomous vehicles, and sensory-rich IoT devices.

The research team acknowledges that the trapped charges’ mobility within the device’s photosensitive layer marks a fundamental departure from fixed-charge memory devices. By enabling charge repositioning in response to externally applied voltages, the phototransistor achieves an unprecedented degree of control over memory retention timescales—a property rarely realized in optoelectronic components designed for AI applications.

From an energy perspective, co-localizing sensing and computation reduces data transfer bottlenecks traditionally plaguing AI processors. This attribute directly addresses pressing challenges in AI hardware, where escalating computational demands often collide with limitations in battery life and thermal management. As a result, the novel phototransistor aligns with broader efforts to develop sustainable, high-performance AI technologies.

Conceived through a multidisciplinary collaboration spanning electrical engineering and physical sciences at Oregon State University, the device’s development also underscores the growing convergence of materials science with computational intelligence. By synergizing metal oxide semiconductors with organic tetracene compounds, the team harnessed complementary material properties—robust electron transport with efficient light absorption—to realize the device’s multifunctional capabilities.

The National Science Foundation’s support, alongside the efforts of researchers including Larry Cheng, Ahasan Ullah, Tasnim Sarker, Xueqiao Zhang, Andrew Ensinger, Lizhong Chen, Roshell Lamug, and Oksana Ostroverkhova, culminated in the publication of their findings in the esteemed journal Advanced Functional Materials. The study not only charts new territory in optoelectronics but also sets the stage for transformative innovation in neuromorphic computing hardware.

As artificial intelligence increasingly demands systems capable of real-world adaptability and resource efficiency, innovations like this gate-tunable neuro-phototransistor epitomize the direction forward. By drawing directly from the brain’s principles of memory modulation and energy-efficient computation, the OSU team’s technology heralds a new era where AI devices can perceive, process, and remember in ways that approximate human cognition more closely than ever before.

Subject of Research: Not applicable

Article Title: Neuromodulator-Inspired Gate-Tunable Tetracene–Metal Oxide Phototransistor for Adaptive Optoelectronic Memory and Neuromorphic Computing

News Publication Date: 19-May-2026

Web References: http://dx.doi.org/10.1002/adfm.75942

References: Published in Advanced Functional Materials

Image Credits: Oregon State University

Keywords

Neuromorphic computing, phototransistor, adaptive memory, optoelectronics, brain-inspired AI, gate-tunable memory, oxide semiconductor, organic photosensitive material, energy-efficient AI, in-sensor computing, tetracene, neuromodulation

A team of researchers has introduced a groundbreaking synaptic device fully controlled and modulated by photons, diverging fundamentally from prior designs that hinge on electric signal transduction stages. This novel optical synapse harnesses a rare-earth-doped long-afterglow crystal, whose persistent luminescence properties enable information storage and processing purely through photonic pathways. This evasion of electrical intermediaries is not merely a conceptual novelty — it can substantially curtail noise levels, slash energy requirements, and accelerate operations, particularly in tasks grounded in visual data processing that naturally involve photons at inception.

The core material at the heart of this device is a doped crystalline matrix exhibiting both immediate photon emission and delayed luminescent afterglow, mediated by trapped charge carriers. When illuminated, some carriers relax promptly to emit photons, while others become temporarily ensnared within defect-induced traps, releasing their energy over extended periods. Crucially, the population dynamics of these traps depend intricately on the device’s illumination history, effectively encoding temporal patterns of input signals. This history-dependent modulation mirrors the synaptic plasticity observed in neural networks, where synaptic strength adapts dynamically based on prior activity, forging a physical instantiation of short-term memory.

To accurately characterize and predict the photophysical behavior of this device, the team formulated a comprehensive kinetic model. This framework accounts for the generation, capture, storage, and release of photoexcited carriers, integrating the competing pathways that determine the balance between instantaneous and persistent luminescence. The model reveals that prior light exposure alters the availability of traps, thereby modulating subsequent emission efficiency. Such nonlinear temporal dependencies provide an elegant mechanistic basis for bidirectional synaptic plasticity—all achieved without recourse to any electrical stimulation or control circuitry.

Experimental validation of the device’s synaptic functionalities was performed using dual-wavelength optical stimulation protocols. Under ultraviolet excitation, the device exhibited paired-pulse facilitation: a second light pulse closely following the first produced an enhanced luminescent response. This enhancement arises because initial excitation partially saturates trap states, thereby biasing subsequent carriers towards faster, direct recombination pathways. Conversely, near-infrared stimulation induced paired-pulse depression. Here, the initial pulse emptied previously trapped carriers, causing a diminished response to the following pulse. The coexistence of these opposing plasticity modes—excitatory and inhibitory—imbues the device with the versatility necessary for emulating complex neural processing.

Moreover, the experimental results corresponded impeccably with the theoretical model’s predictions, underscoring a robust understanding of the underlying physical processes. The research team demonstrated fine-tuned control over device response via modulation of key parameters such as light intensity, pulse duration, and inter-pulse timing. Importantly, they confirmed that the synaptic behaviors observed stemmed authentically from trap dynamics rather than simply residual luminescence, reinforcing the physical legitimacy and repeatability of their design.

Pushing the boundaries towards practical application, the researchers integrated the photon-modulated synaptic crystal atop a commercial silicon imaging sensor, creating a prototype neuromorphic vision system. In this hybrid device, the photonic synapse layer processes incoming images in situ, effectively performing early-stage data interpretation. Notably, strong optical signals persist longer in the crystal’s afterglow, while weak or noisy signals decay rapidly. This intrinsic temporal filtering acts as a form of in-sensor contrast enhancement and noise suppression, circumventing the need for conventional post-processing steps and streamlining the entire image acquisition pipeline.

Leveraging this innovative sensor, the team evaluated performance on image recognition tasks, particularly handwritten digit classification. A simulated neural network employing the measured synaptic device responses achieved an impressive 95.99% accuracy following noise reduction—a stark improvement over approximately 78% accuracy without integrated optical denoising. This milestone not only validates the concept of merging sensing, memory, and processing but also showcases the potential for enhanced computational efficacy and reduced complexity in real-world AI systems.

While current operational speeds of the device range across milliseconds to seconds, slower than typical electronic components, they align closely with biological timescales relevant to visual processing. This temporal congruence suggests the potential for biologically inspired computational timing regimes, rather than simply faster hardware clocks. The authors envisage that scaling the device dimensions and refining the doped crystalline material properties could yield significant increments in speed and energy efficiency, opening pathways to broader applicability.

This research exemplifies a visionary stride toward fully optical neuromorphic computing platforms. By combining optical sensing, information storage, and processing within a single crystal device, it bypasses longstanding bottlenecks inherent in electronic systems. Such all-photonic architectures hold promise for diverse sectors such as robotic vision, autonomous vehicles, wearable electronics, and edge computing, where limited power budgets and rapid data interpretation are paramount.

Further developments may include integrating arrays of these photon-modulated synapses to form complex optical neural networks and exploring materials with even longer-lived trap states or tunable spectral responses. The ability to engineer synaptic plasticity through tailored photonic stimuli provides a rich toolbox for crafting adaptive, intelligent machines that operate closer to the efficiency and sophistication of biological brains.

Overall, this pioneering work sets a new benchmark for neuromorphic device design, suggesting a future where light itself not only conveys information but also processes and remembers it—ushering in a new era of energy-frugal, high-speed, and biologically plausible artificial intelligence.

Subject of Research:
Not applicable

Article Title:
Fully photon-modulated synaptic devices with bidirectional plasticity for neuromorphic vision and recognition

News Publication Date:
25-May-2026

Web References:
https://www.spiedigitallibrary.org/journals/advanced-photonics/volume-8/issue-04/046001/Fully-photon-modulated-synaptic-devices-with-bidirectional-plasticity-for-neuromorphic/10.1117/1.AP.8.4.046001.full

References:
Y. Yan et al., “Fully photon-modulated synaptic devices with bidirectional plasticity for neuromorphic vision and recognition,” Adv. Photon., vol. 8, no. 4, p. 046001, 2026. doi: 10.1117/1.AP.8.4.046001

Image Credits:
Y. Yan et al.

The hallmark of this advancement lies in the seamless amalgamation of a 0.5-micrometer industrial fabrication process with a back-end-of-line (BEOL) integrated academic laboratory technique. This fusion has produced a fully functional MoS2 computer with an impressive transistor count of 1,433, ingeniously interconnected with four metal layers within a remarkably compact footprint. The resulting integration density pushes the boundaries to approximately 9,336 transistors per square millimeter—placing this fabrication at the forefront of 2D semiconductor technology. Such a scale is particularly significant, as it overcomes one of the most persistent bottlenecks for 2D materials: the scaling hurdle from isolated devices to complex, densely packed circuits.

Functionally, this MoS2-based computer isn’t merely a technical curiosity but a genuine computational engine capable of on-chip data storage within registers and the execution of arithmetic operations on multiple-bit data in parallel. Operating at a clock frequency of 1 kHz, the device demonstrates that 2D semiconductors can transition from niche experimental components to devices that handle substantive computational loads. This bit-parallel architecture is a testament to the system’s sophisticated design, reflecting a deliberate emphasis on optimizing data throughput and operational integrity despite the innate challenges posed by the material’s nanoscopic nature.

Crucial to this success is the introduction of a multi-level co-optimization methodology—an integrated design approach that harmonizes optimization efforts across all stages of the computational stack. From transistor engineering through to standard cell libraries, logic synthesis, and interconnect design, this methodology systematically addresses variations and defects at every level, rather than treating each layer in isolation. This holistic co-optimization paves the way for mitigating parasitic effects and variability-induced performance degradation, ensuring reliable and high-yield integration in large-scale 2D semiconductor circuits.

The transistor level improvements are particularly noteworthy. MoS2, as a layered transition metal dichalcogenide, exhibits excellent electrical characteristics such as high carrier mobility and a sizeable bandgap, which are imperative for digital switching. At the transistor scale, the device engineers optimized channel length and contact resistance, mitigating common pitfalls like short-channel effects and Schottky barriers that can cripple device performance in sub-micrometer regimes. This foundation is what permits the higher-level circuit elements to function reliably.

Beyond individual transistor tuning, the design team advanced the development of a standard cell library specifically adapted to the idiosyncrasies of MoS2 devices. By tailoring cell topologies and transistor arrangements to optimize both speed and energy efficiency, they facilitated the construction of complex logic circuits that reconcile the unique electrical properties of MoS2 with practical design constraints. The result is a standard cell library that integrates seamlessly into existing logic synthesis tools while delivering robust performance metrics.

Logic synthesis itself was subjected to rigorous co-optimization, ensuring that the conversion of high-level design specifications into gate-level architectures accounted for inter-device variability and the constraints of the 2D material platform. This adaptive synthesis framework intelligently balances gate duplication, routing complexity, and timing closure, crucially maintaining computational correctness amidst the potential instability introduced by material imperfections.

Interconnect design, often an overlooked but critical component, was innovatively addressed by employing four metal layers in the back-end-of-line. This multi-layer interconnection scheme reduces parasitic capacitances and resistance while providing the routing flexibility necessary for densely packed, large-scale integration without sacrificing signal integrity. Their approach ensures that the physical layout supports the logical design’s complexity, effectively bridging the gap between nanoscale devices and macro-scale circuits.

Additionally, the integration of industry-standard fabrication techniques with academic laboratory innovation provides a blueprint for future work. The industrial 0.5-micrometer node ensures reliable baseline fabrication throughput and device consistency, while the back-end integrated academic processes allow for novel experiments and rapid iteration, such as precision doping and contact engineering. This symbiotic fabrication paradigm is key for transitioning lab-scale breakthroughs into scalable manufacturing pipelines.

The impact of this MoS2 computer extends far beyond the immediate technical achievements. By demonstrating that 2D semiconductors can be fabricated into reliable, densely integrated computational systems capable of storing and processing multi-bit data in parallel, this research reinvigorates hopes for ultralow-power electronics that can dramatically reduce the environmental footprint of AI and data centers. As AI computations continue to surge in demand, such energy efficiency will be critical for sustainable technology development.

Moreover, the system’s unique bit-parallel structure challenges traditional serial data processing paradigms, optimizing computational throughput and providing a tangible pathway for incorporating 2D materials into existing digital architectures. This could catalyze a transformation in how future digital circuits are conceived, prioritizing parallelism not just at the algorithmic level but deeply rooted in the physical hardware design.

The researchers’ work also highlights the importance of considering variations inherent in emerging materials from the outset. By recognizing and designing against the challenges that defects and non-uniformities introduce—rather than treating them as afterthoughts—the team sets a new standard for material-aware circuit design. This philosophy may become seminal as the semiconductor industry increasingly integrates novel materials to surpass silicon’s physical limitations.

While the MoS2 computer operates at 1 kHz, a frequency modest compared to state-of-the-art silicon-based processors, the trade-offs are justified by the significantly reduced power consumption and the demonstration of system-level functionality in an emerging material system. Future efforts aimed at scaling the clock frequency and further integrating advanced processing units could revamp the landscape of low-power, high-density electronics for AI and beyond.

In conclusion, this pioneering MoS2 computer embodies a comprehensive, multi-scale approach to solving the longstanding challenges of 2D semiconductor integration. By aligning advances in fabrication, transistor physics, circuit design, and system architecture, the researchers have established a new frontier for sustainable, energy-efficient computing technologies. Their work not only propagates academic knowledge but also lays a practical foundation for the industrial realization of 2D electronics in mainstream technology sectors. As the semiconductor industry confronts the limits of traditional silicon scaling, innovations like this could well be the blueprint for the next technological revolution.

Subject of Research: Sustainable computing technology using two-dimensional molybdenum disulfide semiconductor for large-scale digital electronics.

Article Title: A bit-parallel molybdenum disulfide computer built through multi-level co-optimization.

Article References:
Fan, D., Mao, Y., Qiu, H. et al. A bit-parallel molybdenum disulfide computer built through multi-level co-optimization. Nat Electron (2026). https://doi.org/10.1038/s41928-026-01641-0

DOI: https://doi.org/10.1038/s41928-026-01641-0

Artificial intelligence computations today are largely dependent on traditional computer architectures that separate memory storage from processing units. This classical von Neumann model necessitates constant data exchange between units, a mechanism responsible for significant energy losses and bottlenecks. As AI proliferates across sectors—from healthcare and autonomous systems to financial markets—the demand for data processing at greater scale and speed simultaneously increases global energy consumption. Consequently, the call for energy-efficient computing solutions is more urgent than ever.

This urgency has driven interest in neuromorphic computing—a paradigm inspired by the human brain’s architecture where memory and computation coexist within the same physical units, enabling energy savings and adaptive processing. The Cambridge team’s development stands out by leveraging the memristor concept, an electronic component capable of storing information by changing its resistance. Unlike conventional memristors that rely on the unpredictable growth and dissolution of conductive filaments inside metal oxides, the new device employs a fundamentally different mechanism that drastically enhances performance uniformity and energy efficiency.

Their approach utilizes a specially engineered hafnium oxide thin film, doped with elements such as strontium and titanium, and synthesized via a novel two-step deposition technique. This process produces a series of precisely formed p-n heterojunctions—interfaces between positively and negatively charged semiconductor regions—that serve as ultra-stable electronic gates. Instead of switching states through filament formation or rupture, the device modulates the energy barrier these junctions create. This subtle, interface-based switching mechanism results in a highly controllable resistance change, which is both smooth and repeatable from cycle to cycle.

This breakthrough addresses a persistent limitation in memristive technologies: variability and randomness in switching caused by filamentary conduction paths. Such variability undermines device reliability, making scaling and integration difficult. By shifting to a switching method that pivots on p-n junction physics, the Cambridge team achieved remarkable device uniformity and stability. Their memristors operate at currents roughly a million times lower than some existing oxide-based devices, a staggering reduction that directly correlates with vast energy savings in AI computations.

Another critical performance metric for these memristors is their ability to support a multitude of stable, distinct conductance states. This multi-level functionality parallels the analog nature of biological synapses and is essential for advanced ‘in-memory’ computing systems capable of complex learning and adaptation. Laboratory evaluations revealed that these hafnium oxide devices could consistently endure tens of thousands of switching cycles while retaining their programmed resistance states for approximately 24 hours—a testament to their practical durability and potential for real-world applications.

Beyond static storage, the devices demonstrated dynamic plasticity reminiscent of neuronal learning processes, specifically spike-timing dependent plasticity (STDP). STDP is a biological mechanism whereby the timing of neural spikes strengthens or weakens synaptic connections, enabling learning and memory formation. The memristor’s ability to replicate such behavior hints at its suitability for implementing hardware-based learning algorithms, making AI systems more adaptive and efficient, moving away from data shuttling toward localized intelligent processing.

Despite these promising results, challenges remain before the technology can be fully commercialized. Notably, the current fabrication process requires temperatures around 700 degrees Celsius—significantly higher than standard CMOS (complementary metal-oxide-semiconductor) manufacturing protocols allow. This poses integration hurdles, as semiconductor fabrication lines operate under stringent thermal constraints to maintain device integrity and compatibility. The Cambridge researchers acknowledge this limitation and are actively investigating methods to reduce processing temperatures, aiming for seamless integration with industry-standard chip fabrication techniques.

Lead researcher Dr. Babak Bakhit, a materials physicist affiliated with Cambridge’s Departments of Materials Science and Engineering, highlighted the significance of this hurdle but remains optimistic. “Lowering the fabrication temperature is our immediate goal,” he stated. “Once achieved, integrating these memristors onto chip-scale systems would mark a pivotal advancement, potentially transforming AI hardware by combining monumental energy reductions with impressive device performance.”

The journey to this breakthrough was far from straightforward. Dr. Bakhit recounted nearly three years of iterative experiments marked by numerous unsuccessful attempts before a crucial modification in the deposition process yielded success late last year. Specifically, introducing oxygen only after the initial film layer grew helped establish the desired p-n heterojunctions critical for stable operation. This perseverance underscores the intricate balance of materials science, device physics, and engineering necessary to develop next-generation computing components.

Support for this research came from prestigious institutions including the Swedish Research Council, the Royal Academy of Engineering, the Royal Society, and UK Research and Innovation (UKRI). The University of Cambridge’s innovation arm, Cambridge Enterprise, has also filed a patent application to protect the intellectual property encompassing this technological leap. Such institutional backing highlights the groundbreaking nature and high potential impact of this work on the AI hardware landscape.

As AI continues its rapid expansion across society, innovations like these hafnium oxide-based memristors offer a glimpse into a future where intelligent machines operate with the brain’s energy efficiency and adaptability. By successfully mimicking key features of neural computation—uniform switching, multi-level states, and synaptic plasticity—within a silicon-compatible material framework, this research paves the way toward scalable, energy-efficient, neuromorphic chips. Such chips could dramatically lower the environmental and economic costs of AI while enabling more powerful, responsive systems.

In conclusion, the University of Cambridge’s research represents a transformative step in neuromorphic hardware development. By harnessing novel materials chemistry, refined fabrication methods, and in-depth understanding of memristive physics, they have created a memristor that not only reduces power consumption by orders of magnitude but also preserves functional characteristics essential for cognitive computing. While further engineering challenges remain, this innovation holds enormous promise to shift the trajectory of AI from energy-intensive computation toward sustainable, brain-like efficiency.

Subject of Research: Neuromorphic hardware and energy-efficient memristive devices

Article Title: HfO2-based Memristive Synapses with Asymmetrically Extended p-n Heterointerfaces for Highly Energy-efficient Neuromorphic Hardware

News Publication Date: 20-Mar-2026

Web References: DOI: 10.1126/sciadv.aec2324

Image Credits: Babak Bakhit, University of Cambridge

Keywords

Neuromorphic computing, memristors, hafnium oxide, p-n heterojunctions, energy-efficient AI hardware, spike-timing dependent plasticity (STDP), materials science, nanoelectronics, artificial intelligence, semiconductor fabrication, brain-inspired computing, in-memory computing

Traditional photonic spiking neural systems, though promising for their high-speed, low-energy operation via optical pulses, have long been hindered by their inability to fully exploit nonlinear processing in photonics. These nonlinear mechanisms are critical for enabling learning and decision-making functions intrinsic to artificial intelligence. Until now, these essential nonlinear computations required conversion back into electronic signals, negating many benefits of photonics by introducing additional delays and power consumption. The newly developed system ingeniously bypasses this bottleneck, leveraging a dual-chip design that supports all-optical processing, which could drastically accelerate applications ranging from autonomous driving to real-time robotic cognition.

The core architecture comprises a 16-channel photonic neuromorphic chip equipped with 272 trainable parameters, working in concert with a complementary chip featuring a state-of-the-art distributed feedback laser array integrated with saturable absorbers. This hardware combination enables the system to handle multiple streams of optical data simultaneously while dynamically adjusting synaptic weights through optical learning processes. The sophisticated use of Mach-Zehnder interferometer meshes within the chips allows precise manipulation of spiking signals, closely mimicking the functionality of biological neural networks but at unprecedented speeds measured in picoseconds.

To validate the system, the researchers implemented a comprehensive hardware-software collaborative training framework. Initial global training occurred via conventional software algorithms, after which the neural models were transferred onto the photonic chips for further refinement. This hybrid strategy allowed compensation for any manufacturing variances and ensured the photonic neural network’s operational fidelity matched the software’s performance with remarkable accuracy. The capacity for on-chip learning and inference is a breakthrough that substantially reduces latency and power consumption compared to purely electronic solutions.

Demonstrating the practical capability of the new neuromorphic system, the team successfully deployed the photonic chips in classic reinforcement learning scenarios such as the CartPole and Pendulum tasks. These benchmark problems require fast, adaptive decision-making to stabilize a balancing pole or swing a pendulum upright. Impressively, the photonic hardware’s decision accuracy was only marginally lower than purely software-based implementations, with a mere 1.5% and 2% reduction in performance respectively. This equivalency underscores the system’s proficiency in replicating complex neural behaviors in real time using light alone.

Beyond task execution, the system boasts extraordinary energy efficiency, delivering 1.39 tera operations per second per watt (TOPS/W) for linear photonic computations, comfortably competing with current GPU technology. Nonlinear processing metrics are equally impressive, achieving close to 988 giga operations per second per watt (GOPS/W), marking a significant leap in operational density and energy economy in neuromorphic photonics. Fabrication innovations, including optimized low-threshold nonlinear spiking components, contribute to these superior performance metrics.

On top of energy efficiency, the photonic neuromorphic chip impresses with its compute density, estimated at 0.13 TOPS per square millimeter for linear operations and 533.33 GOPS per square millimeter for nonlinear tasks, placing it squarely within the performance envelope of top-tier GPUs and application-specific integrated circuits. Its ultra-low latency—only 320 picoseconds for on-chip computation—further cements its potential as a game-changing technology for applications requiring ultra-fast, real-time processing capabilities at the hardware edge.

Looking forward, the research team envisions scaling their design to a 128-channel fully integrated photonic spiking neural network chip. Such an advancement would empower the hardware to tackle even more complex, dynamic reinforcement learning problems such as neuromorphic autonomous navigation, which demands rapid sensorimotor coordination and adaptation. Achieving this level of integration and complexity will require overcoming engineering challenges related to hybrid photonic integration, fabrication yield, and system-level optimization.

This research heralds a new era of neuromorphic computing hardware, where energy-efficient, ultra-fast, and fully programmable photonic processors offer a viable alternative to conventional electronic neural networks. By demonstrating the feasibility of large-scale photonic spiking neurons with hardware-in-the-loop training and inference, this work opens horizons for next-generation AI that can learn directly from environmental interactions with minimal energy footprint and unprecedented speed.

The potential applications of these photonic neuromorphic chips extend far beyond autonomous vehicles and robotics. High-speed optical neural networks could impact data centers, telecommunications, sensor networks, and edge computing devices, accelerating processing while significantly reducing cooling and power requirements. The integration of nonlinear photonic components also suggests future possibilities for on-chip optical memory and real-time cognitive processing in compact, robust form factors.

In summary, this breakthrough in photonic spiking reinforcement learning signifies a monumental step toward neuromorphic hardware that leverages the unmatched properties of optics for artificial intelligence. The synthesis of advanced laser arrays, interferometric meshes, and saturable absorbers into a coherent, scalable architecture exemplifies the fusion of photonics and machine learning. Such technology promises to reshape the landscape of computing with systems that learn fast, operate efficiently, and respond instantaneously—all within the realm of light.

Subject of Research: Photonic Neuromorphic Computing and Reinforcement Learning
Article Title: Nonlinear Photonic Neuromorphic Chips for Spiking Reinforcement Learning
Web References: https://opg.optica.org/optica/abstract.cfm?doi=10.1364/OPTICA.578687
References: S. Xiang, Y. Chen, H. Zhao, S. Shi, X. Zeng, Y. Zhang, X. Guo, Y. Han, Y. Shi, Y. Hao, “Nonlinear Photonic Neuromorphic Chips for Spiking Reinforcement Learning” 13, (2025).
Image Credits: Shuiying Xiang, Xidian University

Keywords

Neural networks, Autonomous vehicles, Robots, Photonics, Applied optics

Traditional electronic neural networks face inherent limitations in speed, heat dissipation, and bandwidth, particularly as model sizes continue to balloon and real-time performance becomes indispensably critical. Optical computing, long theorized as a potential path forward, offers unmatched advantages due to the ultrafast speed of photons and the prospect of parallelism through multiplexed channels. However, translating these theoretical advantages into practical, scalable, and reliable architectures has remained highly challenging. The recent breakthrough by Feng, Li, Zhang, and colleagues addresses these challenges head-on by exploiting the untapped dimensions of spatiotemporal mode multiplexing to implement fully optical neural processing.

The core principle revolves around manipulating optical signals encoded with information distributed across distinct spatial locations and temporal intervals. By multiplexing these modes, the researchers effectively expand the data-carrying capacity of the optical system without necessitating larger or more complex physical components. This mode multiplexing strategy dramatically enhances the expressivity and throughput of the optical neural network, enabling it to process vast amounts of information simultaneously. The result is an all-optical neural network capable of computation speeds far exceeding those achievable with current electronic or hybrid optoelectronic systems.

To bring their vision to life, the team designed a sophisticated photonic architecture integrating multimode waveguides, dynamic modulators, and nonlinear optical elements. These components orchestrate the generation, propagation, and interaction of multiplexed optical modes with remarkable precision. The spatial modes are organized through carefully engineered waveguide geometries that support distinct transverse light patterns, while temporal modes are controlled via ultrafast modulators and delay lines. This dual manipulation enables the seamless embedding and processing of neural information streams, all within the photonic domain.

Equally important are the nonlinear mechanisms embedded within the system to emulate neural network functions such as activation and weighting. These nonlinearities, implemented via materials exhibiting intensity-dependent refractive indices or saturable absorption, facilitate the essential computational transformations in a purely optical manner. The result is the realization of critical neural network units—neurons and synapses—without resorting to electronic conversions, thereby eliminating latency bottlenecks that plague electronic systems.

Extensive simulations and experimental validations underscore the extraordinary potential of this approach. The researchers demonstrated high-fidelity signal processing with low error rates, even as the number of spatiotemporal modes multiplied significantly. Notably, the system achieves operational speeds on the order of tens of gigahertz, a breakthrough magnitude when compared to conventional electronic accelerators that typically operate within megahertz to low gigahertz regimes. Such speeds unlock new applications where real-time, high-throughput inference is a decisive advantage.

The implications of this advance ripple across numerous domains. Real-time video processing, autonomous vehicle navigation, rapid signal classification, and even real-time genomics analysis stand to benefit from the unprecedented computing rates enabled by spatiotemporal mode multiplexed optical neural networks. Additionally, the inherently lower energy consumption of photonic circuits promises eco-friendly computation solutions amid growing environmental concerns associated with large-scale data centers.

Furthermore, the scalable nature of the mode multiplexing paradigm offers a promising roadmap for future expansions. By exploiting additional degrees of freedom such as polarization multiplexing or frequency division multiplexing, the system’s capacity could be extended even further, pushing the envelope of optical neural network complexity and size. The modular design principles also facilitate integration with existing photonic and quantum technologies, potentially fostering a holistic photonic information processing ecosystem.

One of the most exciting prospects is the alleviation of electronic interconnect bottlenecks that currently restrict the scaling of AI hardware. By performing all operations in the optical domain, data transfer delays inherent to electrical conversions are eliminated. This intrinsic speed-up translates into significantly shorter inference times and opens avenues for novel architectures where AI can function directly at the speed of light, essentially matching the ultimate physical limits of information processing.

Achieving practical deployment, however, requires overcoming challenges related to fabrication precision, mode crosstalk mitigation, and material stability under high optical intensities. The researchers address these obstacles through a combination of precise nanofabrication techniques and advanced error-correction algorithms embedded within the network’s training procedures. Such innovations ensure robust operation in realistic environments, thereby moving beyond laboratory prototypes toward viable commercial systems.

In terms of algorithmic compatibility, the all-optical neural network supports a wide spectrum of architectures, including convolutional neural networks and recurrent networks, by tailoring the spatial and temporal mode design to specific computational graphs. This adaptability is crucial for widespread adoption, as it means that the same underlying hardware can be programmed to serve diverse AI workloads without extensive redesigning.

Moreover, the system’s ability to process information in a brain-inspired, parallel manner introduces fresh opportunities for neuromorphic computing paradigms. Unlike serial electronic processing, the spatiotemporal multiplexing model inherently resembles how biological neurons convey and integrate information across spatially distributed and temporally sequenced signals. Hence, this work not only boosts speed but also deepens functional parallels between artificial and natural intelligence systems.

The authors conclude with a forward-looking vision where fully integrated photonic chips embed these optical neural networks alongside light sources, detectors, and control electronics into compact packages suitable for deployment in edge devices, data centers, and even airborne platforms. Such integration could revolutionize the portfolio of AI-enabled technologies, ushering in unprecedented levels of responsiveness and efficiency.

In summary, the development of high-speed all-optical neural networks empowered by spatiotemporal mode multiplexing represents a paradigmatic shift in artificial intelligence hardware. This novel approach combines the unmatched speed of light with the versatility of multiplexed optical modes to deliver unparalleled computational throughput and energy efficiency. As the field burgeons, this pioneering work stands as a beacon for the future of AI and photonics convergence, transforming theoretical promise into practical reality at last.

Subject of Research:
High-speed all-optical neural network architectures based on spatiotemporal mode multiplexing and photonic computing.

Article Title:
High-speed all-optical neural networks empowered spatiotemporal mode multiplexing.

Article References:
Feng, F., Li, X., Zhang, Z. et al. High-speed all-optical neural networks empowered spatiotemporal mode multiplexing. Light Sci Appl 14, 342 (2025). https://doi.org/10.1038/s41377-025-02007-5

Image Credits: AI Generated

DOI: https://doi.org/10.1038/s41377-025-02007-5