The researchers built a single hardware-aware neural architecture search framework and used it as a level playing field for three competing multi-objective optimizers: NSGA-II, a classic evolutionary algorithm; Multi-Objective Simulated Annealing, or MOSA, which borrows its logic from the physics of cooling metals; and Multi-Objective Bayesian Optimization, or MOBO, which builds a statistical model of the search space to guess where the best designs lie. Each optimizer was tasked with tuning three popular neural architectures for keyword spotting: a plain convolutional neural network, a convolutional recurrent hybrid known as CRNN, and a depthwise separable convolutional network called DS-CNN, which is prized for delivering strong accuracy at a fraction of the parameter count.

What makes the search genuinely difficult is that the two objectives pull in opposite directions. Maximizing accuracy generally means adding layers, channels, and parameters, which inflates the serialized model size. Shrinking the model saves memory but usually costs recognition performance. Rather than collapsing these goals into a single weighted score, the team kept the search bi-objective, allowing the optimizers to map out a Pareto front: the set of designs where no model can be made more accurate without becoming larger, and no model can be made smaller without losing accuracy. This Pareto framing gives designers a menu of defensible choices rather than a single answer that silently encodes someone’s assumptions about what matters most.

To keep the comparison statistically honest, the authors ran every optimization five times and subjected the results to non-parametric significance testing, including the Kruskal-Wallis and Mann-Whitney procedures with Holm correction for multiple comparisons. This is a methodological discipline that many architecture search papers skip, and it matters, because multi-objective optimizers are stochastic: a single lucky run can make a weak algorithm look brilliant. The headline result of the study is that MOSA delivered the most reliable convergence across all three architectures, achieving the lowest mean generational distance, a metric that measures how close the found solutions are to the true optimal front. Differences in hypervolume and spread, two other standard quality indicators, were not statistically significant at this sample size, a finding the authors report with appropriate caution.

The best model produced by the framework reached 97.41 percent accuracy, a figure that would have seemed unattainable for on-device keyword spotting only a few years ago. But accuracy alone does not guarantee a deployable model, and this is where the study’s second major contribution comes in. After the search completed, the team evaluated the selected candidates on real hardware, measuring peak SRAM usage, Flash storage requirements, and on-device inference latency. These measurements fed into a Hardware-in-the-Loop Deployability Index, a screening score that separates models that merely look good on paper from models that actually fit and run fast on a target microcontroller. Crucially, the HIL evaluation screens candidates after the search rather than steering it, which keeps the expensive physical measurements from slowing down the optimization loop itself.

The hardware results carry practical weight for anyone shipping embedded voice products. On the STM32F401, one of the tightest boards in the study, the DS-CNN selected by MOBO retained the most resource headroom among the DS-CNN candidates, leaving valuable SRAM and Flash margin for the rest of an application’s firmware. In the embedded world, that headroom is not a luxury; it determines whether a product team can add a second sensor pipeline, a firmware update mechanism, or a more sophisticated wake-word vocabulary later. A model that consumes 95 percent of available memory may benchmark beautifully and still be unshippable, which is precisely the failure mode the Deployability Index is designed to catch.

The final stage of the pipeline addresses a subtler question: given a Pareto front full of trade-off candidates, which one should a designer actually pick? The authors applied a Tchebycheff scalarization step, a technique from multi-objective decision theory that ranks the models according to a stated preference between accuracy and size. Instead of pretending there is one objectively best model, the method makes the designer’s priorities explicit and then identifies the candidate that best honors them. This separation of concerns, generating the trade-off frontier first and applying preferences second, reflects a maturing view of how automated design tools should serve human engineers rather than replace their judgment.

Underlying the whole effort is a quiet revolution in how neural networks are quantized and compressed. The study notes that moving from 32-bit floating point to 8-bit integer weights reduces model size roughly fourfold, which is what makes microcontroller deployment feasible at all. The search framework operates with these deployment realities in view, evaluating serialized model size rather than raw parameter counts, so the numbers the optimizers chase correspond to what will actually be written into Flash memory. The training data came from publicly available corpora, including Google Speech Commands v2 and the Multilingual Spoken Words Corpus, which supports reproducibility and opens the door for other groups to replicate the comparison.

The broader significance of the work lies in its insistence on fair comparison and real-hardware validation, two things the neural architecture search literature has often lacked. Many published NAS pipelines are evaluated on proxy tasks or simulated latency models, and the resulting architectures sometimes disappoint when they meet silicon. By grounding the evaluation in measured SRAM, Flash, and latency figures on actual boards, and by repeating every experiment with proper statistical controls, Garai and Samui have produced something rarer than a new record: a reproducible methodology for asking which optimizer serves TinyML designers best. Their answer, that MOSA converges most reliably while MOBO’s selections leave the most hardware headroom, is nuanced rather than triumphant, and that nuance is exactly what practitioners need.

As always-on voice interfaces spread into battery-powered sensors, hearing aids, industrial monitors, and smart home devices, the demand for tiny models that are simultaneously accurate, small, and fast will only intensify. This study offers a template for meeting that demand systematically: define the objectives honestly, compare optimizers under identical conditions with statistical rigor, verify the winners on real hardware, and only then apply human preferences to choose among the finalists. For the growing TinyML community, the message is that the path from a research prototype to a product that ships inside a two-dollar microcontroller is no longer a matter of trial and error. It can be searched, measured, and ranked, one carefully optimized neural network at a time.

Subject of Research: Multi-objective neural architecture search for hardware-efficient TinyML keyword spotting on microcontrollers

Article Title: Multi-objective neural architecture search for TinyML keyword spotting: a comparative study of metaheuristic and bayesian optimization with hardware-in-the-loop evaluation

Article References: Garai, S., & Samui, S. (2026). Multi-objective neural architecture search for TinyML keyword spotting: a comparative study of metaheuristic and bayesian optimization with hardware-in-the-loop evaluation. Neural Computing and Applications, 38(19), Article 784. https://doi.org/10.1007/s00521-026-12484-3

Image Credits: AI Generated

DOI: 10.1007/s00521-026-12484-3

Keywords: TinyML, keyword spotting, neural architecture search, multi-objective optimization, Bayesian optimization, NSGA-II, simulated annealing, microcontrollers, hardware-in-the-loop, Pareto optimality, DS-CNN, embedded systems

The filter at the heart of the study is an extended Kalman filter, or EKF, the workhorse algorithm engineers use to estimate the state of a dynamic system from noisy measurements. The EKF works by linearizing the system’s motion model around the current estimate, predicting where the target should be, and then correcting that prediction with each new seeker measurement. For tracking problems with mild, well-behaved Gaussian noise, this recipe is remarkably effective. But real seeker data is rarely so cooperative. Glint effects, countermeasures, clutter, and abrupt target maneuvers all inject outliers—measurements that are wildly inconsistent with the statistical assumptions the filter relies on. A standard EKF treats every measurement as trustworthy, so a handful of bad readings can drag the state estimate far off course at precisely the moment accuracy matters most.

The researchers’ answer is to replace the filter’s least-squares cost function with the Huber cost function, a classic tool from robust statistics. The Huber function behaves like a quadratic for small residuals, where ordinary least squares is optimal, but switches to a linear penalty for large residuals. The practical consequence is that outlier measurements still influence the estimate, but their influence is capped rather than allowed to dominate. The resulting Huber-based extended Kalman filter, or HEKF, has been studied before in applications ranging from GPS navigation to spacecraft attitude estimation, and it consistently delivers more reliable estimates under non-Gaussian noise. The catch is computational: instead of a single closed-form update, the Huber formulation requires an iterative optimization loop that must converge on every filter cycle, multiplying the arithmetic workload by an order that embedded flight computers cannot easily absorb.

That bottleneck is what drove the team—Nayeon Kim, SeongJin Yoon, Heoncheol Lee of Kumoh National Institute of Technology, and Ikchan Lim, Changyeol Lee, and Jangseong Park of defense contractor LIGNEX1—toward hardware acceleration. Their target platform was an FPGA, a reconfigurable silicon chip whose logic fabric can be wired into custom digital circuits. Unlike a CPU, which executes instructions sequentially on a handful of cores, an FPGA can instantiate hundreds of arithmetic units that all operate in parallel, each one dedicated to a specific piece of the algorithm. For an iterative filter that must complete its entire predict-and-correct cycle within the tight timing budget of a seeker’s sampling rate, that architectural difference is decisive.

The centerpiece of the implementation is a custom intellectual property block, or IP core, built specifically to evaluate the Huber function and the iterative minimization it drives. Rather than letting a general-purpose processor grind through the optimization in software, the designers encoded the Huber computation directly into hardware datapaths, pipelined so that successive iterations and matrix operations overlap in time. The result is high-throughput, low-latency execution of the very step that makes the HEKF so expensive. In their evaluation, the Huber IP alone ran 6.79 times faster than the same computation on the processing system—the ARM-class CPU portion of the system-on-chip—while the complete HEKF, with the Huber core integrated into the filter pipeline, achieved an overall 3.71-fold acceleration.

Speed means little if accuracy collapses, so the team benchmarked the hardware implementation against the software version on denoising performance and estimation accuracy. The two proved comparable: the FPGA version preserved the robust filter’s ability to suppress measurement noise and track the line-of-sight rate through the nonlinear, outlier-ridden conditions that motivated the design in the first place. In other words, the researchers did not trade estimation quality for throughput; they simply removed the computational excuse for not using the more robust algorithm in real time. For guidance engineers, that is the crucial result, because it means the theoretically superior filter can finally be flown, not just simulated.

The work fits into a broader and rapidly accelerating trend of moving onboard aerospace algorithms from processors into reconfigurable hardware. Previous studies from overlapping research groups have parallelized particle filters and particle swarm optimization on FPGAs for ballistic target tracking, and accelerated convolutional neural network inference for routing in low-Earth-orbit satellite networks. GPU acceleration has been explored for related problems, including model predictive control in integrated missile guidance systems, but FPGAs hold particular appeal for flight hardware because they combine deterministic timing with low power consumption and resistance to the software overheads that plague general-purpose platforms. Comparisons of FPGA, CPU, GPU, and ASIC acceleration for neural network workloads have repeatedly highlighted the FPGA’s sweet spot: customizable parallelism without the fabrication cost of a fixed application-specific chip.

What makes the new study technically interesting is the marriage of robust estimation theory with register-transfer-level design. Kalman filtering on FPGAs is not new in itself—researchers have built hardware accelerators for EKF-based simultaneous localization and mapping, battery state estimation, and other applications—but the Huber variant introduces an iterative inner loop that resists naive parallelization. Each iteration depends on the previous one, so the designers must pipeline carefully, reusing hardware for matrix operations while keeping the convergence loop tight. The custom Huber IP solves this by treating the optimization as a dedicated hardware subroutine, effectively giving the filter a silicon-fast engine for the one part of the algorithm that software cannot execute quickly enough. The approach builds on the team’s earlier 2025 work on parallelized Huber-based EKF implementations, refining it into the present system-level evaluation.

The practical implications extend beyond missiles. Any platform that must estimate the state of a fast, maneuvering, poorly characterized target from noisy sensors faces the same trade-off between robustness and compute budget: drones tracking ground vehicles, radar systems following debris, autonomous vehicles fusing lidar returns, and spacecraft determining attitude in the presence of faulty star tracker readings. A hardware recipe that makes robust filtering affordable in real time is a template that transfers across those domains. The Korean work was funded by the Defense Acquisition Program Administration through the Korea Research Institute for Defense Technology Planning and Advancement, under a program developing design technology for an integrated guidance and control simulator incorporating weapon datalink and seeker systems—signaling that the intended path from laboratory FPGA board to operational guidance hardware is already mapped.

There remain, of course, the usual caveats of early hardware research. The reported speedups were measured against the processing system of the development platform, and further gains will depend on floating-point precision choices, clock rates, and how much of the remaining filter arithmetic migrates into custom logic. Certification of reconfigurable hardware for safety-critical flight systems carries its own regulatory burden. But the direction of travel is unmistakable. As seekers grow more capable and targets grow faster, the algorithms that keep interceptors on course are becoming too computationally demanding for conventional processors alone. By proving that a robust, outlier-resistant Kalman filter can run in hardware at full seeker speed—3.71 times faster than before, with accuracy intact—this study offers a concrete glimpse of where real-time guidance computing is headed: away from software loops and into the fabric of the chip itself.

Subject of Research: FPGA hardware acceleration of a Huber-based extended Kalman filter for robust real-time line-of-sight target tracking

Article Title: FPGA Implementation of Huber-Based Extended Kalman Filter for Real-Time High-Speed Target Tracking

Article References: Kim, N., Yoon, S., Lee, H., Lim, I., Lee, C., & Park, J. (2026). FPGA Implementation of Huber-Based Extended Kalman Filter for Real-Time High-Speed Target Tracking. International Journal of Aeronautical and Space Sciences. https://doi.org/10.1007/s42405-026-01216-5

Image Credits: AI Generated

DOI: 10.1007/s42405-026-01216-5

Keywords: FPGA, extended Kalman filter, Huber function, target tracking, missile guidance, line-of-sight rate, hardware acceleration, robust estimation, embedded systems, parallelization, seeker, real-time computing

The core of the approach, called the Hybrid Compression Framework (HCF), deliberately avoids relying on any single compression technique. Instead, it coordinates three strategies that operate in concert: knowledge distillation, in which a large teacher network supervises a compact student model to preserve semantic fidelity; quantization-aware training, which controls memory footprint by simulating low-precision arithmetic during training; and dynamic inference, which routes each incoming sentence to either a lightweight or a standard computational path depending on its estimated complexity. The author emphasizes that this is not a naive concatenation of existing methods. Neural architecture search is treated as a hardware-aware structure finder, and the architectures it discovers are forced to preserve the parameter subspace that the distillation teacher relies on most heavily—a search-then-distill synergy the paper identifies as the key distinction from prior ensembles.

Two novel modules anchor the framework. The first, a Cognitive Oriented Sparse Constraint (COSC), uses a pre-trained English dependency parser to compute how sensitive each model parameter is to key syntactic nodes such as core predicates and subordinating conjunctions. Parameters with high sensitivity are marked as a protected cognitive core and subjected to stronger regularization during pruning and quantization, forcing them to retain lower sparsity. According to the study, this grammar-aware protection improves the coherence score of long English text by 15.6 percent over conventional pruning at the same compression rate, addressing the familiar failure mode in which aggressively compressed models collapse on complex clauses and slang.

The second module, an Incremental Semantic Calibration Mechanism (ISCM), tackles a quieter problem: semantic drift during continuous learning. Embedded terminals encounter shifting data distributions as learners progress, and models updated on the fly tend to forget earlier capabilities. ISCM maintains a small memory replay set and combines it with elastic weight consolidation, a technique that estimates each parameter’s importance to previous tasks. The measured drift between old and new tasks is converted into a regularization term added directly to the loss function, keeping degradation within a controllable range without requiring cloud retraining.

Dynamic inference works through a lightweight classifier that decides, before any heavy computation begins, which path a sentence should take. The decision is based on three cheaply extracted features: the sentence’s length in tokens, its syntactic complexity measured as the depth of its dependency parse tree, and its lexical difficulty scored through a TF-IDF-based rarity metric. A sigmoid function over these features yields the probability of choosing the high-precision path, with the classifier’s weights trained against oracle-tested optimal paths on the target hardware. A sentence-pattern cache adds a second layer of efficiency: utterances are hashed by their dependency-parse skeleton and content-word sequence, and repeated patterns reuse cached outputs. When the cache hit ratio falls below 0.6, stale entries are evicted to match the current session’s usage.

The system implementation follows a micro-service design, decoupling speech recognition, semantic understanding, and response generation into independent units that communicate asynchronously through message queues. An event-driven scheduler allocates computing resources by priority, and a heterogeneous computing aware runtime compiler (HCARC) provides a unified intermediate layer across different embedded processors. The paper reports that this abstraction slashes model migration cost across hardware platforms by 72 percent—a practical concern given that prior approaches often required regenerating the inference engine for each new terminal. Quantization is applied differentially: attention mechanisms retain 16-bit precision, common fully connected layers are compressed to 8 bits, and the speech feature extraction network uses a specialized 4-bit scheme.

Reinforcement learning refines response quality through a composite reward combining fluency, relevance, and engagement scores, with weights that shift by audience. For children’s learning scenarios, fluency is weighted higher to prioritize grammatical correctness; for adult business English, relevance dominates. Fluency and relevance are computed with BERT-based similarity against reference sets, while engagement is proxied by response length diversity and the presence of follow-up questions. A comprehensive service-quality score multiplies four dimensions—latency, semantic accuracy, memory stability, and output diversity—with weights updated every 100 inference requests to compensate for router drift during long sessions.

The experimental evaluation used the Stanford Sentiment Treebank, supplemented with 120,000 real recorded texts spanning daily dialogue, academic discussion, and scene practice, plus 18,652 hours of speech from Mozilla’s Common Voice dataset. Data was split 70:15:15 for training, validation, and testing with scenario proportions preserved. Against competing methods including hierarchical knowledge distillation, dynamic sparse training, hardware-aware neural architecture search, self-supervised quantization-aware distillation, and cross-modal distillation with semantic alignment, the proposed framework achieved the fastest average response time at 187 milliseconds, a 25 percent reduction in scene response time, 30 percent better memory efficiency, and 23 percent lower energy consumption. Memory usage stayed within 156 megabytes, and simulated availability reached 99.2 percent over 24 hours of continuous operation.

An ablation study isolated each component’s contribution. Removing knowledge distillation dropped semantic accuracy by 4.2 percentage points, from 92.3 to 88.1 percent, confirming its supervisory role. Replacing quantization-aware training with post-training quantization inflated peak memory by roughly 28.8 percent, from 156 to 201 megabytes. Disabling dynamic inference pushed response time up by about 49 percent to 278 milliseconds in exchange for a marginal 0.8 percent accuracy gain—a trade-off the author deems unacceptable for real-time interaction. Cross-scenario testing showed the model holding top performance across basic conversation (0.912), academic discussion (0.885), business communication (0.896), and situational practice (0.924), supporting claims of strong generalization from its multi-source training strategy.

The implications reach beyond the laboratory. Offline-capable, low-power English tutoring could matter enormously in classrooms without reliable connectivity, where cloud offloading fails on latency and unstable links. The author notes limitations candidly: real-time response capability needs further optimization, and long-term verification in actual educational settings remains to be done. Future work includes cross-lingual transfer learning and integrating federated learning to protect user privacy during on-device updates. A product roadmap outlined in the paper plans hardware adaptation to additional chip platforms starting in early 2026. If the reported numbers hold outside simulation, the study suggests the long-standing trade-off between semantic depth and computational efficiency on edge devices may finally be loosening—bringing genuinely conversational AI tutors within reach of inexpensive, battery-powered hardware.

Subject of Research: Lightweight large language model compression for embedded English learning terminals

Article Title: Lightweight large language english interaction model based on embedded learning terminal

Article References: Wang, X. (2026). Lightweight large language english interaction model based on embedded learning terminal. Discover Artificial Intelligence, 6(1), Article 1287. https://doi.org/10.1007/s44163-026-02269-x

Image Credits: AI Generated

DOI: 10.1007/s44163-026-02269-x

Keywords: large language models, knowledge distillation, quantization-aware training, dynamic inference, embedded systems, edge computing, neural architecture search, model compression, semantic accuracy, educational technology, low-power AI, natural language processing

The core idea is deceptively simple: instead of asking patients how much it hurts, listen to their bodies. Pain triggers well-documented physiological responses across the autonomic nervous system. Heart rate and pulse change, breathing patterns shift, skin conductance rises as sweat gland activity increases, and body temperature can fluctuate. The Spanish team combined four low-cost sensors into a single wearable setup: a pulse sensor, a respiratory rate sensor, a body temperature sensor and a galvanic skin response sensor, which measures the electrical conductance of the skin. Each of these signals has previously been linked to pain in the clinical literature, but the Sevilla group’s contribution lies in fusing them together on hardware that costs a fraction of what conventional clinical monitoring equipment does.

The choice of hardware is central to the project’s ambition. Rather than streaming data to a cloud server or a powerful workstation, the researchers deployed their machine learning models directly onto a low-cost microcontroller, an approach known as EdgeAI. This matters for several reasons. First, running inference at the edge means the system can deliver pain predictions in real time without depending on network connectivity, which is essential in busy hospital wards and rehabilitation gyms. Second, keeping physiological data on the device rather than shipping it to remote servers reduces privacy risks, an increasingly important consideration for sensitive health information. Third, microcontrollers are cheap and power-efficient, meaning a finished system could plausibly be scaled to many patients without prohibitive cost.

To make the EdgeAI approach work, the team turned to shallow machine learning algorithms rather than the deep neural networks that dominate headlines. Deep models are powerful but computationally hungry; they generally cannot fit within the memory and processing constraints of a small microcontroller. The researchers instead trained and compared several classic algorithms: artificial neural networks with modest architectures, J48 decision trees, instance-based k-nearest-neighbors classifiers, and random forests. Each model was tasked with the same job: taking the physiological readings from the four sensors and classifying the patient’s state into one of three categories: mild, moderate or severe pain.

A crucial part of the effort was the dataset itself. No off-the-shelf repository of sensor readings matched to pain labels existed for this exact configuration, so the team collected data specifically for the study, annotating recordings with pain levels. This is where the inherent difficulty of the problem becomes visible. Pain perception varies enormously between individuals and is influenced by culture, sex, psychological state and context, factors that the authors themselves acknowledge complicate data collection, annotation and inference. The labels attached to any physiological recording are therefore approximations, filtered through the same subjective reporting the system is trying to supplement. Despite this noise, the models found meaningful structure in the signals.

The results are encouraging for such a constrained platform. The random forest architecture emerged as the clear winner, achieving an accuracy of 83.60 percent in distinguishing between mild, moderate and severe pain. All tested approaches exceeded 65 percent accuracy, well above the roughly 33 percent that random guessing across three classes would achieve. Beyond raw accuracy, the team reported a battery of complementary metrics that paint a fuller picture of performance. The Kappa statistic, which measures agreement above chance, reached 0.7306, generally considered substantial. The area under the ROC curve, a measure of the model’s ability to discriminate between classes across all thresholds, hit 0.9440, a strong result. Error measures were correspondingly modest: mean absolute error of 0.1590, root mean square error of 0.2815, relative absolute error of 0.3942 and relative squared error of 0.6268.

Those numbers should be read with appropriate caution, as the authors are careful to note. An 83.60 percent accuracy in a three-class problem with subjective labels is promising but not clinical perfection, and the system is proposed as a decision-support tool rather than a replacement for clinical judgment. Still, the fact that such performance is achievable with shallow models on a microcontroller is the real headline. It suggests that the physiological signature of pain, however noisy, is strong enough to be captured by cheap hardware and simple algorithms, democratizing a capability that previously required expensive laboratory equipment or complex multimodal setups involving brain imaging or facial video analysis.

The potential applications are broad. The researchers highlight rehabilitation sessions, where physiotherapists need continuous, objective feedback about how much pain a patient is experiencing during exercises, information that patients themselves may minimize or exaggerate. The system could also be useful during surgeries and postoperative monitoring, where anesthetized or sedated patients cannot report pain at all. Perhaps most strikingly, it could serve patients with speech disorders, who currently have no reliable way to communicate their pain level to caregivers. In all these scenarios, a continuous, wearable, automatic monitor could catch pain spikes that periodic verbal check-ins miss, leading to faster interventions and better pain management strategies.

The work also fits into a rapidly growing research landscape. Machine learning approaches to pain assessment have accelerated in recent years, with studies using electrodermal activity, facial video analysis, electroencephalography and multimodal neuroimaging to predict clinical pain. Many of these efforts rely on heavy computational resources, cloud processing or specialized sensors. The Sevilla system’s distinctive contribution is its radical pragmatism: four commodity sensors, one microcontroller, four classic algorithms and a mobile application that presents the predicted pain level to the user or clinician. The mobile app completes the loop, turning raw sensor streams into an interpretable evaluation that can inform care in real time.

Challenges remain before such a system reaches routine clinical use. The subjectivity of pain perception affects every stage of the pipeline, from how training data is labeled to how well a model generalizes to new patients whose baseline physiology differs from those in the training set. Larger and more diverse datasets, longitudinal validation in real hospitals, and regulatory scrutiny will all be necessary. Yet the direction of travel is clear. As edge computing hardware grows more capable and biosensors cheaper, objective, continuous pain monitoring is moving from the research lab toward the clinic. The Spanish team’s study, supported by the Andalusian DAFNE project and the Spanish Ministry of Science’s NEKOR project, offers a concrete demonstration that meaningful pain assessment does not need a supercomputer, just well-chosen signals, well-trained models and a chip small enough to wear.

Subject of Research: Automatic pain assessment using EdgeAI machine learning and low-cost physiological sensors

Article Title: Automatic pain assessment system based on EdgeAI and low-cost sensors

Article References: García Flores, J., Cabello Arango, C. A., Duran-Lopez, L., Cerezuela-Escudero, E., & Dominguez-Morales, J. P. (2026). Automatic pain assessment system based on EdgeAI and low-cost sensors. Neural Computing and Applications, 38(18), Article 740. https://doi.org/10.1007/s00521-026-12474-5

Image Credits: AI Generated

DOI: 10.1007/s00521-026-12474-5

Keywords: pain assessment, EdgeAI, machine learning, biosensors, microcontroller, random forest, galvanic skin response, rehabilitation, wearable sensors, embedded systems, neural networks, pain management

The motivation behind the study is straightforward: intelligence gathered after the fact is of limited use to security operators and urban planners who need answers as events unfold. Earlier crowd counting approaches generally fall into three camps. Detection-based methods scan video frames for individual people, but they falter badly in dense crowds where bodies and heads occlude one another. Regression-based approaches instead learn global image cues such as texture and gradient statistics to estimate numbers, yet they often miss fine local detail that precision counting demands. The dominant modern paradigm, density map estimation, trains a convolutional network to predict a continuous map in which each head contributes a small blob, and summing the map yields the total count. Pioneering models such as the Multi-column Convolutional Neural Network showed the promise of this idea, but their deep, parameter-heavy architectures demand server-class GPUs and large memory footprints that embedded surveillance hardware simply cannot provide.

Some researchers have chased efficiency with deliberately slimmed-down networks. PCC-Net-light reduced parameters for single-image counting, MobileCount introduced an efficient encoder-decoder framework, and structured knowledge transfer distilled large models into smaller ones. Generic lightweight backbones such as SqueezeNet, MobileNet, and ShuffleNet demonstrated that careful architectural choices, including depthwise separable convolutions, group convolutions, and channel shuffling, could slash computational cost without catastrophic accuracy loss. The new work builds on this lineage but targets a stricter bar the authors call super real-time performance. Previous lightweight counters, they note, cut parameters yet still failed to deliver the fastest possible inference, leaving a gap for applications such as intelligent surveillance, public safety management, urban planning, and intelligent transportation where every millisecond counts.

The proposed architecture follows a stem-encoder-decoder blueprint. The stem network performs early down-sampling that compresses spatially redundant pixel data to one quarter of the original resolution, then applies unusually large convolution kernels of sizes 9, 7, and 5. Large kernels enlarge the network’s receptive field, allowing it to capture detailed head features that small kernels miss, a choice the authors validated in ablation experiments. Because the model trains from scratch without pretrained weights, expanding the receptive field at the front end proves especially valuable. The stem also incorporates ShuffleNetV2-style shuffle blocks, which split channels into two branches, process them with convolutions, and re-mix information through concatenation and channel shuffling to keep the representation expressive at minimal cost.

The encoder, where much of the speed gain originates, organizes features into multi-scale branches at one quarter, one eighth, and one sixteenth of the input resolution, with channel counts of 36, 64, and 96 respectively. Each of its two stages stacks components containing two Conditional Channel Weighting blocks and one Multi-branch Local Fusion block. Conditional Channel Weighting, first introduced in Lite-HRNet and adapted here for crowd counting for the first time, replaces ordinary convolutions with element-wise weighting operations governed by cross-resolution and spatial weight functions, adaptively selecting which feature channels matter at each resolution. The Multi-branch Local Fusion block, a new design from this team, merges multi-scale features exclusively through down-sampling and summation, keeping feature scales small during fusion and thereby holding computational consumption down.

To compensate for the inevitable incompleteness of purely local fusion, the decoder borrows Feature Pyramid Networks, a proven mechanism from object detection. The lowest-resolution encoder output is up-sampled, fused with lateral feature maps produced by one-by-one convolutions, and refined with three-by-three convolutions that smooth the aliasing artifacts of up-sampling; this iterative process repeats until a final density map emerges. Two one-by-one convolution layers then regress the combined features down to a single-channel prediction map. The entire decoder adds only about 0.085 megabytes of parameters. Training uses a straightforward mean squared error loss between predicted and ground-truth density maps, with the Adam optimizer, a cosine-annealed learning rate schedule starting at one times ten to the minus four, 300 epochs, and standard augmentation including random cropping and horizontal flipping.

The numbers are remarkable for a model this size: the whole network weighs just 0.15 megabytes and requires roughly 1.32 gigafloating-point operations per image. Across three standard benchmarks, the small-scale ShanghaiTech dataset with its SHHA and SHHB subsets, the diverse and challenging UCF-QNRF collection of 1,535 dense crowd images, and NWPU-Crowd, currently the largest benchmark with 5,109 images and more than 2.1 million annotated heads spanning densities from zero to 20,033 people per image, the network delivers competitive accuracy, including a mean absolute error near 65 on the SHHA test split while running at roughly 380 frames per second. Runtime tests across four hardware platforms, the GTX 1080Ti, RTX 3090, Jetson TX1, and Jetson Xavier, show per-image inference never exceeding 15 milliseconds at a resolution of 576 by 768 pixels, comfortably inside real-time territory even on low-power modules.

The study also confronts the elephant in the modern research room: large language models and vision-language systems. Although models such as BLIP-2 and LLaVA excel at few-shot and zero-shot vision tasks, the authors quantify why they are hopeless fits for embedded counting today. BLIP-2, with 11 billion parameters, and LLaVA, with 7 billion, demand 15 to 22 gigabytes of GPU memory and take 1.0 to 1.3 seconds per 224 by 224 image even on an NVIDIA A100. On a Jetson TX1, these models cannot complete a single forward pass in under 10 to 12 seconds and effectively exhaust available memory, and even a compact MiniGPT-4-tiny variant exceeds 500 milliseconds per frame, far beyond the 33-millisecond budget that 30 frames-per-second operation requires. The team’s own tests found that no evaluated language-model-based approach exceeded 0.1 frames per second on the TX1, versus more than 70 frames per second for their lightweight convolutional network on the same chip.

Ablation studies reinforce each design decision. Large kernels of 9, 7, and 5 outperformed both stacks of small three-by-three kernels and dilated kernels, with the authors speculating that dilated convolutions ignore very small head information in dense scenes and introduce gridding artifacts. Neither Conditional Channel Weighting nor Multi-branch Local Fusion alone matches the accuracy-and-efficiency combination of the pair working together, and the stem, encoder, and decoder each prove indispensable. The team further introduces an Accuracy-Efficiency Score that jointly weighs mean square error, parameter count, and frame rate, and their model tops this metric across benchmarks, trading roughly 2 to 3 mean absolute error points for a five-to-tenfold speedup compared with heavier competitors whose hundreds of millions of parameters confine them below 50 frames per second.

The researchers acknowledge limits and point the way forward. The model occasionally underestimates counts in extremely dense regions where head boundaries overlap severely, and future work may pair the lightweight architecture with density-aware loss functions or replace the Feature Pyramid Network decoder with something even leaner to reach more marginalized devices. For now, the paper demonstrates a crucial principle for practical artificial intelligence: raw accuracy on a leaderboard tells only part of the story, and a deliberately balanced design can put genuinely useful, super-real-time crowd analytics within reach of the inexpensive embedded hardware that actually keeps watch over the world’s crowds.

Subject of Research: A lightweight deep learning architecture for real-time crowd counting on embedded systems

Article Title: Real-time crowd counting for embedded systems with lightweight architecture

Article References: Zhao, Z., Wen, Y., Yang, S., Ning, L., Liu, Y., & Gao, J. (2025). Real-time crowd counting for embedded systems with lightweight architecture. Vicinagearth, 2(1), Article 13. https://doi.org/10.1007/s44336-025-00025-w

Image Credits: AI Generated

DOI: 10.1007/s44336-025-00025-w

Keywords: crowd counting, embedded systems, lightweight neural network, computer vision, density map estimation, real-time inference, NVIDIA Jetson, convolutional neural network, intelligent surveillance, public safety, Feature Pyramid Networks, efficiency

The starting point is the so-called W-shaped development process, proposed by the European Union Aviation Safety Agency together with the company Daedalean in their Concepts of Design Assurance for Neural Networks reports. The classic V-model, which underpins standards such as DO-178C in avionics, ISO 26262 in automotive engineering, and the ECSS framework in aerospace, arranges development as two arms: requirements are refined into code on one side, and hierarchical testing verifies them on the other. The W-shaped process extends this with a second V dedicated to what EASA calls learning assurance—verifying that a learned model generalizes to unseen operational data and behaves robustly within its Operational Design Domain, the envelope of conditions in which it is meant to operate. For supervised learning, where datasets with labels exist before training begins, the process works. But reinforcement learning is different, and that difference matters.

In reinforcement learning, an agent learns by interacting with its environment: it observes a state, takes an action, and receives a reward that reflects how good the action was for achieving its goal. There are no ground-truth labels to check outputs against, and—crucially—there is no dataset before training. Training data is generated by the very interactions that produce learning. The researchers, led by Ángel-Grover Pérez-Muñoz of Universidad Politécnica de Madrid and colleagues, found that this single characteristic fractures the W-shaped process at its foundation. The process assumes data management precedes learning; in reinforcement learning the two are inseparable. EASA itself has deferred guidance on reinforcement learning to 2028, which makes an empirical test of the framework both timely and rare.

To probe the limits, the team designed a use case that is as much a safety exercise as an AI challenge. A defender drone, controlled entirely by a neural-network reinforcement learning agent, must follow a predefined sequence of waypoints through a simulated urban landscape built in Microsoft’s AirSim simulator, while an adversary drone tries to ram it. Three attacker strategies escalate in difficulty: a deterministic pursuer that simply chases the defender’s last known position; a predictive pursuer that estimates the defender’s position one second ahead with random scaling to mimic sensor error; and a still harder variant that randomizes its prediction horizon between one and two seconds. The defender must reach each waypoint within three meters, maintain at least 1.25 meters of separation from the attacker, and repeat this under waypoint altitudes it never saw during training.

The technical machinery underneath is careful and deliberate. The agent’s state is a twelve-dimensional vector built entirely from relative quantities—distance to the attacker, distance to the next waypoint, relative velocity, and the defender’s own velocity—so that the learned policy is invariant to where the drone happens to be in the world. Actions are continuous velocity commands on three axes, bounded at seven meters per second. The reward function stacks a cubic distance penalty, large bonuses for reaching waypoints and completing the course, and steep penalties for collisions, proximity violations, and wasted time. Training used the Soft Actor-Critic algorithm with four-layer actor and critic networks of 512 neurons each; notably, the team found SAC outperformed Proximal Policy Optimization because it prioritized minimizing penalties over chasing rewards—an intuitive fit for a system whose primary duty is not crashing.

The results carry a cautionary lesson about overtraining. An agent trained for 400,000 steps against the simple deterministic attacker achieved success rates between roughly 75 and 81 percent against all three attackers, including strategies it had never encountered, evaluated over 1,100 episodes across eleven random seeds. Its sibling trained for a full million steps on the same attacker fared dramatically worse, dropping as low as 27 percent against the predictive pursuers—a statistically significant collapse, confirmed with bootstrap tests of ten million resamples. Extended training, it appears, caused the agent to overspecialize on the deterministic chase pattern. Agents trained directly against the harder attackers did no better, with one achieving near-zero success. The lesson for safety engineers is stark: more compute and more training do not guarantee more general, more trustworthy behavior, and the certification process must be able to catch this.

What elevates the study beyond a simulation exercise is what happened next. The actor network—the part of the agent that turns observations into actions—was automatically translated from Python into C code compliant with MISRA-C, the conservative subset of C used in safety-critical software, which forbids dynamic memory allocation and thereby eliminates memory leaks, heap fragmentation, and unpredictable timing. The code was deployed on a Zynq UltraScale+ MPSoC board under the XtratuM hypervisor, which partitions the hardware in both space and time so that a fault in the AI component cannot propagate to other subsystems. Because the deployed agent must never learn in operation, only the frozen policy flies; the critic networks stay behind.

The embedded system passed its examinations. Running at a required control period of 200 milliseconds with a 100-millisecond deadline, static worst-case execution time analysis using the OTAWA tool bounded a single inference at 38 milliseconds, while 1,500 measured inferences averaged 23.62 milliseconds with a maximum of 71.18 milliseconds—comfortably inside the deadline even with interference from other tasks. Numerical comparison between the Python original and the C implementation, necessarily reduced from 64-bit to 32-bit floating point, showed errors on the order of one hundred-thousandth of a meter per second, negligible against an action range of fourteen meters per second. Success rates on the hardware—79.1, 81.4, and 79.6 percent against the three attackers—fell within the confidence intervals of the original model, demonstrating that the certified translation did not silently degrade the learned behavior.

The broader significance lies in the mapping the researchers drew between reinforcement learning’s needs and the W-shaped process’s stages. They found that the entire development-assurance half of the process—implementation, integration, and verification on real hardware—is agnostic to the learning technique and applied cleanly. The learning-assurance half required reinvention: instead of predefined datasets, the team defined scenarios derived from the Operational Design Domain to govern data generation; data quality requirements such as representativeness and completeness, which normally apply to whole datasets, were reinterpreted as properties of those scenarios; and a new step was inserted to define the agent-environment interface—the states, actions, and reward function—before training could begin.

This is, by the authors’ account, the first application of EASA’s W-shaped process to a reinforcement learning system, and it arrives as EUROCAE and SAE finalize the ARP6983/ED-324 standard for aeronautical AI. The work suggests a realistic path forward: certification frameworks built for supervised learning can stretch to accommodate learning agents that discover their own strategies, provided the emphasis shifts from curating data to curating the scenarios that generate it. The researchers caution that their results live in simulation, and closing the sim-to-real gap—sensor noise, communication delays, environmental perturbations—remains future work, as does confronting learning-based attackers. But for a field waiting on regulators until 2028, the demonstration that a reinforcement learning drone can be trained, certified, and embedded within real-time safety constraints is a milestone worth more than its 71-millisecond inference time might suggest.

Subject of Research: Applying the EASA W-shaped development process to reinforcement learning for safe drone navigation and collision avoidance

Article Title: Application of the W-shaped process for a Reinforcement Learning use case on drone navigation

Article References: Pérez-Muñoz, Á.-G., García-Quijano, H., López-García, G., Alonso, A., & Pérez, M. S. (2026). Application of the W-shaped process for a Reinforcement Learning use case on drone navigation. Machine Learning with Applications, 26, Article 101009. https://doi.org/10.1016/j.mlwa.2026.101009

Image Credits: AI Generated

DOI: 10.1016/j.mlwa.2026.101009

Keywords: reinforcement learning, drone navigation, aviation safety, EASA, W-shaped process, machine learning certification, neural networks, embedded systems, collision avoidance, Soft Actor-Critic, operational design domain, safety-critical systems

Researchers Hamed Alqahtani of King Khalid University in Saudi Arabia and Gulshan Kumar of Shaheed Bhagat Singh State University in India have unveiled FTL-IDS, a Federated Temporal-Aware Lightweight Intrusion Detection System. The framework is a deliberate co-design of four technologies that are usually pursued separately: multi-domain feature extraction from CAN traffic, a hybrid LSTM-Transformer temporal encoder, 8-bit quantization-aware training, and federated learning. According to the authors, existing intrusion detection systems tend to trade temporal modeling capability, privacy, or embedded efficiency against one another; the goal of FTL-IDS is to balance all three at once.

The feature engineering stage is where raw CAN traffic becomes machine-learnable. Rather than feeding raw frames into a neural network, the system organizes temporal, entropy, spectral, and payload-statistical features into fixed-length windows. Entropy features capture the randomness of message identifiers and payloads, which spikes during fuzzing or injection attacks. Spectral features expose periodic patterns that replay or denial-of-service attacks disrupt. Payload statistics reveal when a message’s data content deviates from what a given ECU normally transmits. This multi-domain representation gives the downstream model a rich but compact view of network behavior.

At the heart of the detector sits a hybrid deep learning architecture that splits the temporal modeling problem in two. A long short-term memory network, or LSTM, captures the local dynamics of CAN traffic, the short-range dependencies between consecutive frames that define normal in-vehicle behavior. A Transformer component then models longer-range dependencies across the window, using attention mechanisms to spot subtle patterns that unfold over longer horizons. This division of labor mirrors a broader trend in sequence modeling, where recurrent architectures handle fine-grained local structure while attention mechanisms excel at global context.

Deploying such a model inside a car, however, demands more than accuracy. Automotive ECUs have strict memory, compute, and latency budgets, so the researchers applied 8-bit quantization-aware training, a technique in which the neural network is trained with the constraints of low-precision arithmetic baked in from the start. The resulting quantized model occupies just 1.4 megabytes and achieves a forward-pass latency of 0.13 milliseconds per precomputed window on a Raspberry Pi 4B, a stand-in for resource-constrained embedded hardware. That footprint makes the approach realistic for integration alongside existing ECU software rather than requiring dedicated high-performance hardware.

Privacy is addressed through federated learning, a distributed training paradigm in which the model is trained across multiple clients, such as vehicles or fleet segments, without centralizing raw CAN traffic. Each client trains locally on its own data and shares only model updates, so sensitive driving behavior never leaves the vehicle. The federated version of FTL-IDS retains 99.10, 97.81, and 96.40 percent accuracy on the three evaluation datasets respectively, showing that distributed training costs only a modest amount of detection performance compared with centralized training.

The evaluation spanned three widely used benchmarks of increasing realism: the HCRL Car Hacking dataset, the ROAD dataset, and CAN-MIRGU. On these, FTL-IDS achieved accuracies of 99.71, 98.94, and 97.12 percent, with macro-F1 scores of 0.9978, 0.9817, and 0.9653. The authors also stress-tested the model against adversarial examples, carefully crafted inputs designed to fool machine learning classifiers. Under a fixed perturbation level of epsilon equal to 0.1, accuracies held at 95.2, 93.1, and 91.8 percent against the Fast Gradient Sign Method, and 92.8, 90.0, and 89.7 percent against the more aggressive Projected Gradient Descent attack. The system also incorporates explainability through SHAP and LIME analyses, aligning with a growing demand for interpretable security decisions in safety-critical domains.

The authors are candid about the limits of the work. The robustness study covers only FGSM and PGD attacks; the federated experiments use five simulated clients rather than a real fleet; and the reported latency excludes raw-log preprocessing and the computation of SHAP and LIME explanations. Validation on production-grade ECUs, along with broader adaptive, black-box, and certified robustness testing, remains necessary before the framework can be considered deployment-ready. Standards contexts such as AUTOSAR and ISO 26262, which govern automotive software architecture and functional safety, will ultimately shape how such detectors are certified.

Even with those caveats, the study offers a deployment-oriented baseline for CAN intrusion detection research, demonstrating that temporal representation, privacy-preserving training, and compact inference can be engineered to coexist. As vehicles become more connected and attack surfaces widen, frameworks like FTL-IDS suggest a path toward protecting in-vehicle networks without sacrificing either driver privacy or the real-time performance that automotive systems demand. The datasets used in the study are publicly available, allowing other researchers to build on and independently verify the results.

Subject of Research: A hybrid federated deep learning framework for lightweight, privacy-preserving intrusion detection in CAN-based in-vehicle networks.

Article Title: Federated temporal-aware lightweight intrusion detection system for CAN-based in-vehicle networks: A hybrid deep learning and privacy-preserving framework

Article References: Alqahtani, H., & Kumar, G. (2026). Federated temporal-aware lightweight intrusion detection system for CAN-based in-vehicle networks: A hybrid deep learning and privacy-preserving framework. Multimedia Tools and Applications, 85(10), Article 766. https://doi.org/10.1007/s11042-026-21937-9

Image Credits: AI Generated

DOI: 10.1007/s11042-026-21937-9

Keywords: automotive cybersecurity, intrusion detection system, CAN bus, federated learning, LSTM-Transformer, quantization-aware training, adversarial robustness, in-vehicle networks, controller area network, deep learning, embedded systems, privacy-preserving training