The pairing of the two themes is deliberate rather than coincidental. Modern chip development has become one of the most computationally and intellectually demanding tasks in engineering, and AI is rapidly changing how circuits are conceived, verified, and optimized. At the same time, the explosive growth of machine learning has created enormous demand for hardware that can execute neural networks efficiently, particularly outside the data center, where power budgets are tight and latency matters. Fraunhofer IAF’s new initiatives in Heilbronn address both sides of this equation, while its III-V activities address a third, equally strategic concern: ensuring that Europe retains sovereign, resilient manufacturing capacity for the specialized semiconductor technologies that underpin communications, mobility, and security.

The first of the new initiatives is the state-funded project FRAUKE—short for Fraunhofer AI Design—carried out at the Innovation Park Artificial Intelligence (IPAI) in Heilbronn. In FRAUKE, Fraunhofer IAF is working together with the University of Stuttgart and IMS CHIPS to research CMOS circuit design for and through artificial intelligence. The phrase captures a double ambition. On one side, the project aims to accelerate the design process itself, using AI methods to support and speed up the creation of CMOS circuits. On the other, it aims to develop CMOS-based hardware components for AI applications, with target domains that include edge computing and image processing—areas where intelligent processing must happen directly on the device rather than in a distant cloud. The project is funded by the Ministry of Economic Affairs, Skilled Craft and Tourism of Baden-Württemberg, anchoring it firmly in the state’s growing semiconductor strategy.

Running in parallel is a second, longer-term undertaking at the same Heilbronn location. Fraunhofer IAF and the Fraunhofer Institute for Integrated Circuits IIS, together with the Research and Innovation Center FIZ Chip AI, are building a durable infrastructure for AI chip design within the Fraunhofer Heilbronn Research and Innovation Centers, known as HNFIZ. This effort is funded by the Dieter Schwarz Foundation and is intended to establish a platform for what the institute describes as AI Hardware Made in Germany. The scope stretches from AI-supported CMOS design processes all the way to neuromorphic processors and spiking neural networks, a class of brain-inspired computing architectures valued for their potential to deliver energy-efficient edge AI. By building this infrastructure in Heilbronn, the partners are creating a permanent home for research that connects algorithmic intelligence with physical silicon.

Visitors to the Fraunhofer IAF booth in Stuttgart will be able to engage with these themes directly. The institute will present an interactive exhibit on AI tools for chip design and on chip design for AI applications, translating the abstract ambitions of the FRAUKE and FIZ Chip AI initiatives into a hands-on experience. The exhibit is designed to show how closely AI and microelectronics already interact today, a point emphasized by the institute’s leadership. Prof. Rüdiger Quay, Director of Fraunhofer IAF, notes that the presence at EFX demonstrates the interaction between intelligent chip design and powerful hardware for AI applications, while also underscoring the institute’s role in transferring these technologies into industrial practice in Germany and Europe through its III-V pilot lines and its position within the Research Fab Microelectronics Germany.

That second pillar—III-V semiconductor manufacturing—may be less fashionable than artificial intelligence, but it is arguably more foundational. III-V compound semiconductors, materials formed from elements in the third and fifth groups of the periodic table, include gallium nitride (GaN) and indium gallium arsenide (InGaAs). These materials offer electronic and optical properties that silicon cannot match in certain regimes: GaN excels in high-power, high-frequency operation, while InGaAs is prized for high-speed and optoelectronic applications. The result is a technology base that is indispensable for 5G and future 6G networks, autonomous driving, satellite communication, and modern defense systems. Fraunhofer IAF argues pointedly that Europe must not become dependent on non-European supply chains in these areas, a concern that has moved to the center of industrial policy across the continent.

What the institute brings to this challenge is a complete chain of expertise housed in its specialized cleanroom in Freiburg. The capabilities span epitaxy—the crystal-growth process by which the layered semiconductor structures are deposited—through process development, design, and characterization, and extend to modules and advanced prototyping based on III-V compound semiconductors. At EFX, the exhibits presented by Fraunhofer IAF are intended to exemplify this end-to-end capability. The strategic idea is to make specialized III-V chip technologies accessible to industry through pilot lines: shared manufacturing and development pathways that allow companies, particularly small and medium-sized enterprises and start-ups, to test, mature, and prototype advanced technologies without having to invest in their own specialized fabrication facilities.

This pilot-line philosophy scales up through Fraunhofer IAF’s role as a cooperating institute of the Research Fab Microelectronics Germany (FMD), a consortium of thirteen Fraunhofer Institutes together with the Leibniz Institutes FBH and IHP. Within this national research infrastructure, Fraunhofer IAF contributes the III-V expertise for high-frequency, power, and optoelectronics. The consortium model is designed to give research and industry a single point of access to the full breadth of microelectronics technologies, and the institute frames its participation as a direct contribution to resilient, European manufacturing capacities in electronics manufacturing. The stated goal is to create the foundation for mastering critical high technologies independently—from the laboratory to industrial production—a formulation that speaks directly to current debates about technological sovereignty.

The venue for all of this is itself part of the story. EFX—Expo for Electronics Manufacturing is a new event, and Messe Stuttgart is positioning it as a platform for innovative, digital, and resilient electronics manufacturing. The choice of Baden-Württemberg as the host region is no accident: the state has been investing heavily in its semiconductor ecosystem, and the Chip Connect BW network, in which Fraunhofer IAF is an active partner, exists precisely to present local expertise along the semiconductor value chain and in technology transfer. By exhibiting together with other network partners, the institute is presenting not an isolated laboratory but a connected regional ecosystem capable of carrying research results into production.

For the audiences the fair is meant to attract—companies, start-ups, scientists, and trade visitors—the invitation is explicitly practical. Fraunhofer IAF will be reachable at booth 9B26B in the Chip Connect BW joint area from October 6 to 8, 2026, with experts available to discuss AI chip design, chip manufacturing, and III-V pilot lines, and to initiate concrete collaborations. Behind the trade-fair presentation lies a broader argument about how the next decade of electronics will be built: that the tools used to design chips will increasingly be intelligent themselves, that the hardware running AI will need to be radically more efficient at the edge, and that the specialized materials enabling high-frequency and power electronics must be manufacturable on European soil. Fraunhofer IAF’s Stuttgart presence is, in essence, a demonstration of all three propositions under one roof, backed by a research institution whose work covers the entire value chain from materials research and design through processing to modules, systems, and demonstrators—including electronic circuits for innovative communication and mobility solutions, laser systems for real-time spectroscopy, novel hardware components for quantum computing, and quantum sensors for industrial applications.

Subject of Research: AI-supported chip design and III-V semiconductor pilot lines for European electronics manufacturing

Article Title: AI chip design and III-V pilot lines for electronics manufacturing

Article References: AI chip design and III-V pilot lines for electronics manufacturing. (n.d.). Original publication

Image Credits: AI Generated

DOI: Not provided

Keywords: Fraunhofer IAF, chip design, artificial intelligence, III-V semiconductors, gallium nitride, CMOS, neuromorphic computing, pilot lines, electronics manufacturing, edge AI, Research Fab Microelectronics Germany, EFX 2026

The Electrical Testing Board, described in the open-access journal HardwareX by a research team led by Geu M. Puentes-Conde of the Universidad Autónoma de Ciudad Juárez, is a four-layer FR-4 board measuring 187 by 160 millimeters, complete with an integrated carrying handle and an 88-pin gold-finger edge connector designed for backplane integration. Rather than attempting to replace a full-scale industrial test station, the platform is positioned as a compact, reproducible alternative for circuit prototyping, academic instruction and small-scale manufacturing, where the economics of full in-circuit testing infrastructure remain prohibitive. The hardware is released under the CERN Open Hardware License v2.0, its firmware under the GNU General Public License v3.0, and its documentation under Creative Commons Attribution 4.0.

In-circuit testing verifies the values and structural integrity of individual components soldered onto a board, while functional testing validates the overall operational behavior of the finished device. Both methodologies are indispensable in industry because defects can arise from many sources: improper material handling, components that fall outside parametric tolerances, failures in surface-mount assembly equipment, or simple human error. Commercial systems from vendors such as Keysight Technologies, Teradyne and SPEA apply voltage or current stimuli through test nodes, route the resulting signals through multiplexers and conditioning stages involving amplification, filtering and linearization, and finally digitize the analog result to yield electrical parameters such as resistance, capacitance, inductance, voltage, current and short- or open-circuit status. The new board follows this same architectural logic, but in a radically miniaturized and democratized form.

At the heart of the design is a three-board modular stack. A main PCB houses the functional test modules, a relay PCB carries the switching matrices, and a pluggable MCU PCB hosts the primary controller, a Microchip PIC32MX795F512L running at 80 megahertz. Because the core module is a daughterboard, a failed microcontroller can be swapped in seconds without any desoldering. Two slave PIC18F4620 microcontrollers, managed over the I2C bus, drive the relay matrices and handle auxiliary input and output tasks. Sixteen test nodes connect the device under test to four relay-based switching buses, labeled V+, M+, M− and G−, which route signals among the programmable power supplies, the digital multimeter subsystem, comparators, programmable pull-up and pull-down networks, and protection circuitry. The reed relays at the center of these matrices, Coto 9012-12-11 units, actuate in roughly 0.35 milliseconds, allowing a complete in-circuit or functional measurement cycle of 10 to 50 milliseconds per device.

The measurement capabilities are broad. The onboard digital multimeter offers voltmeter ranges of 0 to 10 volts and 0 to 100 volts through a 16-bit successive-approximation ADC paired with a low-drift 10-volt precision reference, ammeter ranges from 1 microampere to 1 milliampere across three calibrated gain stages built around a transimpedance amplifier, resistance measurements from 0.5 ohms to 1 megohm using a ratiometric voltage-divider method, and capacitance measurements from 10 nanofarads to 220 microfarads. Rather than replicating the expensive AC voltammetry and synchronous phase-detection approach used in commercial systems, the designers adopted a direct interface circuit technique: the unknown capacitor is charged and then discharged through a known reference resistor while an embedded timer measures the interval until a comparator threshold is crossed, from which capacitance follows from simple logarithmic relations. The method trades some accuracy at the low end of the range for dramatic reductions in circuit complexity and cost.

Validation against reference instrumentation suggests the trade-offs are manageable for its intended audience. Benchmarked against an HP 34401A six-and-a-half-digit multimeter, the voltmeter stayed within 0.14 percent relative error at low-voltage test points of 1, 3.3 and 5 volts, with error and variance growing at higher voltages, reaching about 0.91 percent at 90 volts, a divergence the authors attribute to attenuation networks and parasitic loading in the high-voltage path. The ammeter achieved sub-percent errors at points such as 5 microamperes and 150 microamperes, though deviations grew near the top of each subrange. Resistance measurements remained below 1 percent relative error across 1 kilohm to 1 megohm, while the lowest point, 0.5 ohms, showed an 11.31 percent error driven by relay contact resistance, a systematic offset the firmware can compensate through tare calibration. Capacitance accuracy was weakest at 10 nanofarads, with errors above 30 percent, but settled to roughly 8 to 10 percent for bulk values of 100 and 220 microfarads.

Beyond raw metrology, the platform is designed for integration into automated test equipment environments. It communicates with a host computer or programmable logic controller over RS-232, opto-isolated UART buses, or Ethernet through a Microchip LAN8720 physical layer transceiver, using a checksum-protected packet protocol in which command bytes select tasks such as automated testing, limit transmission and data retrieval. Up to 12 boards can be daisy-chained under a single host controller, each addressed by a dedicated digital selection line and monitored through a busy-status output. In a demonstration implementation, eight boards ran parallel end-of-line tests across a multi-cavity fixture pallet, performing power-up sequencing, firmware register extraction over UART, harness continuity checks, battery voltage profiling, quiescent current measurement, pneumatic actuation of buttons via high-current relay outputs, busbar presence verification and even acoustic pattern validation through the onboard audio conditioning circuit, a capability absent from the commercial systems the authors compared against.

The team is candid about the limits of the platform. It supports a single device under test per board, offers 16 test nodes compared with up to 2,592 on a two-module Keysight i3070 system, and its practical analog bandwidth is deliberately limited to DC to 10 kilohertz by the relay switching network. It cannot measure inductance, does not support IEEE 1149.1 JTAG boundary-scan testing, and is not certified for industrial deployment, restricting its scope to controlled laboratory, prototyping and small-production settings operated by qualified engineering personnel. Long-term relay endurance, thermal drift, fault injection robustness and full metrological characterization were also left as explicit future work. Power consumption, however, is modest: roughly 2.5 watts at idle and between 3.1 and 6 watts during typical testing routines.

The economic argument is nevertheless compelling. Where a complete commercial system with instrument cards, chassis and enclosure can run into six figures, the proposed assembly costs about $790 to fabricate, or an estimated $3,500 for a full system including host controller, enclosure, cables and test probes, still roughly an order of magnitude below the entry point of industrial hardware, which typically demands $25,000 to $250,000. All design files, schematics, firmware, bill of materials and even a debugging enclosure are openly available through a public repository, enabling any competent electronics laboratory to replicate or adapt the platform.

The implications extend beyond manufacturing quality control. The authors envision materials scientists using the programmable switching matrices and multimeter to map resistance and capacitance across novel conductive polymers or biological tissue samples, applied physics laboratories replacing bulky benchtop instruments in automated experiments, environmental researchers deploying the opto-isolated inputs and Ethernet interface as a ruggedized sensor node layer, and embedded acoustics teams exploiting the audio conditioning chain for voice and frequency pattern work. Future development will focus on integrating machine learning directly into the firmware layer to shorten test cycles and enable predictive fault isolation, along with expanding the physical node architecture to widen signal routing capacity and test coverage. For a field in which the cost of entry has quietly determined who can afford rigorous electrical verification, an open, sub-$1,000 testing platform may prove to be one of the more quietly disruptive hardware releases of the year.

Subject of Research: A low-cost modular open-hardware PCB assembly for in-circuit and functional testing of electronic devices

Article Title: A low-cost modular PCB assembly for functional and in-circuit testing

Article References: Puentes-Conde, G. M., Sifuentes, E., Molina, J., Enríquez-Aguilera, F., Bravo, G., & Ávila, A. H. (2026). A low-cost modular PCB assembly for functional and in-circuit testing. HardwareX, 28, Article e00844. https://doi.org/10.1016/j.ohx.2026.e00844

Image Credits: AI Generated

DOI: 10.1016/j.ohx.2026.e00844

Keywords: in-circuit testing, functional testing, open-source hardware, printed circuit board, automated test equipment, digital multimeter, relay switching matrix, electronics manufacturing, small and medium enterprises, microcontroller, capacitance measurement, HardwareX