Very long baseline interferometry is one of the most demanding techniques in all of astronomy. By combining signals from radio dishes spread across continents, astronomers can achieve angular resolution equivalent to a single telescope as wide as the entire baseline, revealing fine structure in quasars, masers, and even the shadow of a black hole. The catch is data volume: each telescope digitizes incoming radio waves into streams of baseband data at enormous rates, and these streams must later be compared with microsecond-level precision at a central correlator. Traditionally, this has meant recording data on disks, shipping or transferring them, and playing them back hours or days later. The e-VLBI approach collapses that timeline to zero, improving observational efficiency, reducing the risk that a technical failure ruins an entire session, and dramatically shortening the distance between observation and scientific result. Real-time operation also enables time-critical science, from rapid follow-up of gamma-ray bursts to geodetic monitoring of Earth’s rotation.

At the heart of the new design is the VLBI Data Interchange Format, or VDIF, a universal standard adopted by major observatories worldwide, including Japan’s OCTAVE-Family systems, MIT Haystack’s RDBE, the Event Horizon Telescope’s R2DBE, the European DBBC series, and the DiFX and SFXC software correlators. The author, Wei Yu, who conducted the work at the Shanghai Astronomical Observatory and is now at the University of Tübingen, built the system with the Chinese VLBI Network and the East Asia VLBI Network in mind, though the design is applicable to other arrays such as the European VLBI Network. In the architecture, the VDIF formatter and network transmission interface live inside each telescope’s digital backend, while the VDIF deformatter and network receiving interface are embedded in the hardware correlator at the correlation center, linking components that in conventional systems operate as loosely coupled, independent units.

The formatter’s job begins with a subtle problem. The digital baseband converter produces data from up to 16 baseband channels at 2 bits per channel, but after channel selection, only a subset of bits in each 32-bit word may be valid, and that number must be a power of two: 1, 2, 4, 8, 16, or 32. The Fanout module solves this by accumulating the valid bits into a fully packed 32-bit stream using configurable accumulation sub-modules and multiplexers selected by a bit-stream mask number. For example, when only 8 bits are valid, the module fills four successive bytes before declaring a new word complete. Once a full frame’s worth of data has accumulated, a pulse signals that a new frame is ready. A FIFO buffer bridges the clock domains between this module and the downstream frame generator, keeping the pipeline orderly despite differing clock frequencies.

The Frame_Generator module then does what its name suggests: it inserts standard VDIF headers into the continuous data stream at regular intervals, producing frames consisting of eight 32-bit header words followed by a payload of baseband data ranging from 64 bytes to 9000 bytes. Timing is everything here. A pulse-per-second signal from a hydrogen maser synchronizes the formatter to absolute time, and an internal counter loads a 30-bit VDIF timestamp that increments every second, stored in the header along with a frame number that advances with each new frame. Because headers are irreplaceable, this module runs at a higher clock frequency than its neighbors, and a pulse generator sub-module reshapes timing signals to match. When the formatter starts, the multiplexer outputs the eight cached header words in sequence and then reads payload data from a FIFO, producing a seamless stream of standard VDIF frames ready for the network.

The network interfaces represent perhaps the most significant engineering achievement of the paper. Rather than running a software network stack on an embedded processor, the author implemented a fully hardware-based UDP/IP stack directly in FPGA logic, using on-chip RAM for buffering to avoid the bottlenecks of external memory. In the transmission direction, a finite state machine drives a Tri-mode Ethernet Media Access Controller, prepending 14 bytes of Ethernet header, 20 bytes of IP header, and 8 bytes of UDP header to each payload chunk. With the maximum transmission unit set to 1500 bytes, each packet carries a fixed 1472-byte payload, cached in a RAM of precisely calculated depth. Notably, the UDP checksum is skipped and set to zero, a deliberate latency-saving choice made safe by the Ethernet frame checksum and by receiving software that captures raw packets in promiscuous mode using the libpcap library.

On the receiving side, the hardware correlator faces a different challenge: it must wait for data from all playback servers before processing, but its FPGA buffer is too small to idle indefinitely without overflowing. The solution is an improved UDP protocol with an acknowledgment mechanism. After every group of 20 packets, the playback server starts a timer and waits for an acknowledgment from the correlator; if the ACK arrives in time, transmission continues with the next group, and if not, the same group is retransmitted. The receiving state machine validates destination MAC and IP addresses, strips the protocol headers into a compact 42-byte RAM table, pushes payload data into a FIFO, and replies with a pre-constructed ACK packet whose addressing fields borrow the source addresses of the incoming data. This mechanism trades some raw throughput for reliability, a sensible bargain for a correlator with finite logic resources.

The VDIF deformatter reverses the formatting process at the correlator. Its Header_Stripper module reassembles incoming 8-bit network data into 32-bit words, detects the synchronization word that marks each VDIF header, and cross-checks the frame timestamp against an externally initialized synchronization time. Frames whose extracted frame numbers do not match an internal counter are dropped and replaced with zero-filled data, ensuring that timing errors propagate visibly rather than silently corrupting correlations. The Fanin module then decomposes each packed 32-bit word back into multiple output words using shift registers, restoring the original channel structure with valid low bits and zero-padded high bits, exactly mirroring the Fanout module’s earlier compression. A functional test confirmed end-to-end correctness: a sinusoidal signal fed into the formatter emerged intact from the deformatter after network transit, scaled down by the configured decimation factor of 16.

The performance numbers are striking. Implemented on a board carrying five Xilinx Virtex-4 FPGAs, the formatter and transmission interface consume just 8 percent of available slices and 5 percent of on-chip RAM, while the receiving chain uses only 7 percent and 5 percent respectively. Throughput testing showed the transmission interface reaching approximately 790 megabits per second, or 79 percent of gigabit Ethernet efficiency, a nearly threefold improvement over the roughly 260 megabits per second achieved by the previous solution that ran the Treck TCP/IP stack on an embedded CPU. The receiving interface, throttled by the acknowledgment mechanism, sustained about 420 megabits per second in the actual CVN hardware correlator, comfortably above the 302 to 467 megabits per second recorded in a recent intercontinental e-VLBI transmission between University Malaya and the Shanghai Astronomical Observatory using the Jive5ab-UDT protocol.

Perhaps most importantly, the system works under real observing conditions. In an actual observation of the radio source 1741-038 with four telescopes of the Chinese VLBI Network operating in single polarization with 2-bit quantization and sixteen 2-megahertz baseband channels, the hardware correlator produced clean autocorrelation amplitude spectra for all four stations and clear fringe patterns across all six baselines, confirming successful detection of the correlated signal. The four components, formatter, deformatter, and both network interfaces, are designed as independent intellectual property cores that can be dropped into other radio astronomical instruments, and the transmission interface has already been adopted by a continuous spectrum backend. As e-VLBI becomes the norm for international arrays, designs like this one, which squeeze gigabit performance out of modest FPGA resources while speaking the universal language of VDIF, will form the invisible plumbing of a globally synchronized observing machine.