The motivation behind the work is the growing mismatch between the relentless growth of global data and the physical limits of electronic memory. Conventional silicon-based architectures, despite decades of refinement, are approaching hard boundaries in scalability, speed, and power density. All-optical memories, which encode, store, and retrieve information entirely within the optical domain, promise high transfer rates, low latency, and favorable energy efficiency. Yet each competing approach carries drawbacks: silicon-on-insulator platforms suffer from high losses, localized surface plasmon resonance structures are limited by ohmic losses and fabrication complexity, photonic crystals demand extreme fabrication precision, and Kerr nonlinear materials require high optical intensities and are sensitive to noise. Phase-change materials stand apart because they retain data even after the light source is removed, thanks to their non-volatile nature and high optical contrast between structural states.

The heart of the new device is a dumbbell-shaped resonator: a rectangular cavity flanked by two semi-disk resonators, coupled to MIM input and output waveguides carved in silver with air serving as the dielectric. Surface plasmon polaritons, hybrid waves of light and collective electron oscillations, are confined to the metal-dielectric interfaces and squeezed into regions far smaller than the wavelength of light. The team modeled the optical response of silver with the Drude formalism and validated the design using two-dimensional finite-difference time-domain (FDTD) simulations with a 3-nanometer mesh and perfectly matched layer boundaries. As a passive filter, the structure exhibits a Gaussian transmission peak at 1210 nanometers with a peak transmittance of 91 percent, a full width at half maximum of 56 nanometers, and a quality factor of about 21.

Geometry proved to be the decisive lever in tuning performance. Through systematic parametric sweep simulations, the researchers found that the radius of the semi-disk resonators dominates the resonance wavelength, shifting it by 2.22 nanometers for every nanometer of radius change, while the width of the rectangular cavity induces a blueshift at a sensitivity of minus 0.69 nanometers per nanometer, and the cavity length contributes a modest redshift of 0.3 nanometers per nanometer. The coupling gap between the waveguides and the resonator, varied from 0 to 18 nanometers, showed that transmission degrades progressively as the gap widens, because the evanescent field that transfers energy between the waveguide and the cavity decays exponentially with distance. Notably, the optimal configuration is a zero-gap, monolithic design, which sidesteps the notoriously difficult requirement of maintaining sub-10-nanometer alignment during fabrication.

Transforming this filter into memory required integrating a strip of GST, measuring 500 by 190 nanometers, into the central resonator and introducing a second optical pathway. A control signal, delivered from above the chip by a laser, programs the memory: a SET pulse of 50 milliwatts lasting 150 nanoseconds, roughly 7.5 nanojoules, gently heats the material above its crystallization temperature of about 450 kelvin, converting it from the amorphous to the crystalline state. A RESET pulse of 110 milliwatts for 20 nanoseconds, about 2.2 nanojoules, melts the material at roughly 880 kelvin before it rapidly quenches back into the amorphous phase. Crucially, this programming is spatially and functionally decoupled from the readout, which uses a low-power probe signal sent through the MIM waveguide, too weak to disturb the stored phase state.

The readout mechanism exploits the dramatic optical difference between the two phases of GST. In the amorphous state, the refractive index is 3.94 with low absorption, and the device transmits a resonance peak at 1912 nanometers with 95 percent transmittance, corresponding to logic state 1. In the crystalline state, both the real and imaginary refractive indices rise sharply to 6.11 plus 0.83i, absorption soars, and transmission drops to essentially zero, registering logic state 0. The contrast between the states reaches 95 percent, the extinction ratio reaches 25 decibels, and the insertion loss is a remarkably low 0.19 decibels in the amorphous state versus 25.2 decibels in the crystalline state. Because the phase persists without power, the bit is genuinely non-volatile, classifying the device within the PRAM and NVRAM families of memory.

The team went beyond static spectra and performed transient femtosecond-scale analysis using a square excitation pulse. In the amorphous state, the output rises to 95 percent of the input within about 200 femtoseconds after a 7-femtosecond propagation delay, with rise and fall times of 82 and 84 femtoseconds respectively, before ohmic losses drain the signal by roughly 1100 femtoseconds. In the crystalline state, the output settles at only about 4 percent, an OFF regime with minimal leakage. A reference simulation without the GST-loaded resonator confirmed that the MIM waveguides themselves preserve signal integrity with negligible distortion, meaning any temporal modification originates from the light-matter interaction inside the resonator. The researchers note that while these read dynamics reflect the electromagnetic impulse response rather than the slower phase-change kinetics, existing experimental literature supports GST switching frequencies between 1 and 10 megahertz with endurance up to one million cycles.

Perhaps the most forward-looking aspect of the design is its neuromorphic potential. The optical transmittance of the resonator is governed by the complex refractive index of the GST layer, and GST is well documented to undergo fractional crystallization, passing through intermediate states between fully amorphous and fully crystalline. Each intermediate state yields a distinct transmission level, which can be mapped onto an analog synaptic weight. The high-transmission amorphous state corresponds to a potentiated synapse, while the low-transmission crystalline state represents a depressed one. The authors frame the device as a scalable building block for all-optical neuromorphic synapses, potentially enabling spike-timing-dependent plasticity through tailored pulse-programming sequences in future circuits, thereby merging logic and memory on a single photonic platform in a departure from conventional von Neumann architectures.

Practical integration also received attention. The device is compatible with back-end-of-line CMOS processes, relying on standard techniques such as electron-beam evaporation, sputtering, electron-beam lithography, and reactive ion etching. The monolithic zero-gap resonant cavity can be patterned as a single continuous unit, eliminating fragile alignment steps, and sensitivity analysis confirms that performance peaks precisely at this configuration. Ultra-thin passivation layers of silicon dioxide or aluminum oxide can shield the silver from oxidation without compromising plasmonic confinement, while the high thermal conductivity of the silver substrate acts as a passive heat sink that, combined with nanosecond control pulses, suppresses thermal crosstalk. The authors acknowledge that the design deliberately prioritizes high transmission over an ultra-high quality factor, because the active GST layer introduces losses during switching and a strong baseline signal is essential for reliably distinguishing the two logic states. Compared against a broad field of plasmonic and photonic-crystal memories built on GST and Kerr materials, the proposed cell posts the highest transmission contrast in its class while remaining among the most compact, suggesting that light-written, power-free memory at the nanoscale may be moving from concept toward chip-ready reality.

Subject of Research: A non-volatile plasmonic memory based on an MIM waveguide and GST phase-change material for binary logic and neuromorphic computing

Article Title: Design of a non-volatile Plasmonic Memory Based on MIM waveguide and phase-change Materia for binary logic and neuromorphic integration

Article References: Kehtarmanesh, M., Keshavarzi, P., & Danaie, M. (2026). Design of a non-volatile Plasmonic Memory Based on MIM waveguide and phase-change Materia for binary logic and neuromorphic integration. Results in Optics, 25, Article 101141. https://doi.org/10.1016/j.rio.2026.101141

Image Credits: AI Generated

DOI: 10.1016/j.rio.2026.101141

Keywords: plasmonics, phase-change material, GST, non-volatile memory, MIM waveguide, optical memory, neuromorphic computing, photonic integrated circuits, FDTD simulation, optical contrast, synaptic weight, CMOS compatibility

Monolithic 3D integration differs from the chip-stacking approaches used in today’s advanced packaging. Instead of fabricating separate dies and bonding them together with relatively coarse interconnects, monolithic 3D integration builds successive device layers sequentially on the same wafer. Each new tier of transistors is grown and patterned directly on top of the interconnect stack of the tier below. This allows extremely dense vertical connections between logic and memory, dramatically shortening the distances data must travel and opening the door to computing architectures in which memory and processing are woven together in three dimensions. The obstacle has always been thermal budget: conventional silicon processing requires temperatures that would destroy the metal interconnects and devices already in place beneath a new layer, so any channel material added on top must be deposited and processed at low temperatures.

The Purdue team, led by Peide D. Ye of the Elmore Family School of Electrical and Computer Engineering, turned to indium oxide deposited by atomic layer deposition, a technique in which the semiconductor film grows one atomic layer at a time through self-limiting surface reactions. Atomic layer deposition offers exceptional thickness control and superb conformality across large substrates, and the resulting amorphous indium oxide films can be processed at temperatures well within the tolerance of back-end-of-line metallization. Because the films are amorphous rather than crystalline, they sidestep the grain-boundary and lattice-matching problems that plague many alternative low-temperature channel materials, including two-dimensional semiconductors that have attracted enormous attention for the same application.

The demonstration is remarkable for its breadth of device functionality. On the 200-millimeter wafers, the researchers fabricated three tiers of devices spanning ferroelectric field-effect transistors for non-volatile memory, as well as enhancement-mode and depletion-mode field-effect transistors for logic. Ferroelectric transistors hold their stored state without power, enhancement-mode devices switch off cleanly at zero gate voltage, and depletion-mode devices conduct by default, so together they form a complete transistor toolkit suitable for real circuit design. The electrical statistics across the wafers are equally notable. Threshold voltage standard deviations as low as 0.04 volts were achieved, a level of uniformity that rivals commercial silicon devices and indicates that the low-temperature process is genuinely manufacturable rather than a laboratory curiosity. Average electron mobilities reached up to 91.6 square centimeters per volt-second, high enough to support fast switching and strong drive currents in dense vertical layouts.

Uniformity at wafer scale is arguably the central achievement here. Research groups have previously shown promising oxide semiconductor transistors on small chip-scale samples, but moving to a 200-millimeter platform subjects every device to the same statistical scrutiny that foundry engineers apply to silicon. The team systematically characterized how processing variations, including annealing temperatures and capping steps, affected each device family. They found that a surface-capping layer followed by a 300-degree-Celsius anneal substantially improved bias stability, suppressing the threshold voltage drift that can undermine reliability during sustained operation. Statistical distributions of subthreshold swing, threshold voltage, and memory window remained tight across hundreds of measured devices per condition, with sample sizes running into the hundreds for each device type tested.

Thermal robustness was verified layer by layer. Because each tier of devices must survive the processing of the tiers fabricated above it, the researchers subjected finished transistors to the full thermal sequence and re-measured them. Mobility, threshold voltage, and subthreshold characteristics were preserved with negligible shift after the complete stack processing, confirming that indium oxide can endure the cumulative thermal exposure of a multi-tier build. The team also engineered the channel thickness to select device behavior: thinner films of about 1.5 nanometers yielded enhancement-mode operation, while thicker films near 3.0 nanometers produced depletion-mode devices, giving circuit designers the complementary options they need for power-efficient logic within the same material system.

With three functional tiers established, the researchers went beyond device statistics and demonstrated fully functional cross-tier circuits, in which signals travel vertically through inter-tier vias connecting transistors on different layers. This vertical wiring capability is what transforms stacked transistors from a density trick into a genuine architectural opportunity. Logic and memory separated by microns of horizontal wiring in a conventional planar chip can instead sit directly atop one another, connected by short vertical links. The team used a custom process design kit built around compact models of their indium oxide transistors, including a standard cell library of eleven logic gates verified through D flip-flop simulations, to bridge the gap between measured device behavior and large-scale circuit design.

The system-level payoff was quantified in the design of a four-tier 3D computing-in-memory accelerator targeting large-language-model workloads. Computing-in-memory architectures perform matrix operations directly inside memory arrays, sidestepping the energy cost of shuttling data between separate memory and processor units, a bottleneck that dominates the power budget of modern artificial intelligence systems. By vertically interleaving logic and memory tiers made from the same low-temperature oxide platform, the proposed accelerator exploits the short inter-tier connections that monolithic integration uniquely enables. Benchmark simulations showed speed-ups of 1.4 times to 2.9 times over comparable two-dimensional baselines, together with comparable improvements in energy-delay product, a metric that captures both how fast a workload completes and how much energy it consumes.

The significance for the semiconductor industry lies in the convergence of manufacturability and application pull. Data centers running large language models are straining power grids, and the energy cost of moving data between memory and logic has become the defining constraint of AI hardware. A low-temperature, wafer-scale, CMOS-compatible platform for stacking logic and memory in three dimensions offers a way to attack that constraint directly, without abandoning the existing silicon infrastructure. Because the entire integration happens on standard 200-millimeter wafers using back-end-of-line-compatible processing, the approach could in principle be adopted as an additional module within existing foundry flows rather than requiring a wholesale reinvention of the fabrication plant.

Challenges remain before such stacks reach commercial products. The accelerator results reported here come from design and simulation benchmarked against the measured device data rather than from a fully fabricated four-tier chip, and scaling the demonstrated three-tier integration to four or more tiers will demand continued control of yield and variability across the stack. Nevertheless, the demonstration answers the question that has lingered over monolithic 3D integration for years: whether any low-temperature channel material can deliver both the electrical performance and the wafer-scale uniformity that real manufacturing requires. With atomic-layer-deposited indium oxide now shown to do so on an industry-standard substrate, the vertical dimension of computing has moved from concept toward the fabrication line.

Subject of Research: Monolithic 3D integration of atomic-layer-deposited indium oxide semiconductor devices on 200-mm silicon wafers for vertically stacked logic and memory in AI hardware

Article Title: Monolithic 3D integration of atomic-layer-deposited oxide semiconductors on 200-mm silicon wafers

Article References: Niu, C., Long, L., Zheng, L., Du, S., Lin, J.-Y., Nam, K., Lin, Z., Liu, C., Lu, J., Wang, H., Li, H., & Ye, P. D. (2026). Monolithic 3D integration of atomic-layer-deposited oxide semiconductors on 200-mm silicon wafers. Nature Nanotechnology. https://doi.org/10.1038/s41565-026-02276-0

Image Credits: AI Generated

DOI: 10.1038/s41565-026-02276-0

Keywords: monolithic 3D integration, indium oxide semiconductor, atomic layer deposition, 200-mm wafer, back-end-of-line processing, ferroelectric field-effect transistor, computing-in-memory, AI accelerator, large language models, CMOS compatibility, threshold voltage uniformity, three-dimensional chip stacking

The review, authored by Nada Salem, Ahmed Shaker, Mahmoud Ossaimee, Ahmed Saeed, Mohamed Abouelatta, and El-Sayed M. El-Rabaie, takes an unusually integrated approach. Rather than treating device physics, manufacturing, and circuit applications as separate silos, the authors connect the atomic structure of carbon nanotubes directly to transistor behavior and ultimately to commercial viability. This matters because the performance of a CNTFET is not determined by the nanotube alone; contact resistance, tube alignment, density control, metallic-tube removal, and compatibility with existing CMOS manufacturing all shape whether carbon can genuinely replace silicon in a factory setting.

At the heart of the technology lies a deceptively simple material trick. A carbon nanotube is a sheet of graphene rolled into a cylinder roughly one nanometer in diameter, and the precise way it is rolled, defined by its chirality indices (n, m), determines whether it behaves as a metal or a semiconductor. Tubes in which the difference between the two indices is divisible by three are nominally metallic, while the rest are semiconducting. For semiconducting single-walled tubes, the bandgap scales approximately inversely with diameter, following the relation Eg of about 0.84 divided by the diameter in nanometers. That simple formula gives device engineers a powerful tuning knob: choosing the tube diameter effectively sets the threshold voltage, the leakage current, and the ON-state current of the resulting transistor.

The physics inside these devices is equally striking. Because carriers are confined to a one-dimensional channel, transport can approach the ballistic limit, where electrons traverse the channel without scattering. Clean carbon nanotube channels have demonstrated carrier mobilities of roughly 1,000 to 10,000 square centimeters per volt-second, an order of magnitude or more above scaled silicon, with characteristic carrier velocities of 2 to 5 times ten to the seventh centimeters per second against a theoretical Fermi velocity ceiling near 8 times ten to the seventh. Subthreshold swings can approach 60 to 80 millivolts per decade, and ON/OFF current ratios spanning 10^5 to 10^8 have been reported depending on diameter, contacts, and dielectric engineering. These numbers explain why researchers have chased carbon nanotubes since the first CNTFET was demonstrated in 1998.

Architecture has evolved considerably since those early proof-of-concept devices. Back-gated transistors, in which the silicon substrate itself acts as the gate, were simple to build but suffered from contact resistances of a megohm or more and weak electrostatic control. Top-gated designs introduced thin dielectrics deposited by atomic layer deposition, tightening gate coupling and enabling individual devices to be isolated on a single wafer. Wrap-around or gate-all-around structures, demonstrated in 2008, surround the nanotube entirely, suppressing leakage and short-channel effects most effectively. Suspended devices, in which the tube hangs free over a trench, minimize substrate scattering and reveal the intrinsic transport properties of the material, though mechanical instability and limited dielectric options keep them largely a laboratory tool.

Modeling this zoo of devices has produced a rich theoretical landscape. Ballistic models, built on the Landauer formalism, estimate the performance ceiling of ideal short-channel devices. Quasi-ballistic and non-ballistic models add phonon scattering through virtual-source and Landauer-Büttiker approaches, capturing the roughly 30 percent current reduction that dissipative transport imposes in realistic channels. Tunneling-based compact models account for band-to-band tunneling that dominates in small-bandgap tubes under bias, while full non-equilibrium Green’s function formulations solve quantum transport self-consistently with electrostatics, linking device behavior directly to the chiral index of the tube. For circuit designers, SPICE-compatible compact models such as the Stanford virtual-source CNFET model bridge the gap, embedding quantum capacitance, contact resistance, and ambipolar conduction into tools that can evaluate logic, memory, and radio-frequency circuits.

Fabrication remains the decisive battleground. Modern processes grow horizontally aligned nanotube arrays on quartz by chemical vapor deposition at densities near three tubes per micrometer, transfer them to oxidized silicon wafers, selectively remove metallic tubes, and deposit high-k gate stacks of titanium dioxide with titanium-platinum electrodes. The resulting devices show improved ON/OFF ratios and reduced device-to-device variability, and the low processing temperatures make the route compatible with CMOS thermal budgets. On a very different frontier, aerosol jet printing has been used to fabricate working CNTFETs on flexible Kapton substrates using silver ink electrodes and cross-linked polymer dielectrics, opening a path toward wearable and bendable electronics that rigid silicon cannot serve.

The application portfolio is expanding fast. CNTFET biosensors have detected the H1N1 virus, DNA modifications, prostate-specific antigen at concentrations from 5 to 5000 picograms per milliliter, and SARS-CoV-2 spike protein epitopes within minutes, exploiting the nanometer-scale match between tube and biomolecule. In memory research, devices using hafnium oxide gates have achieved write and erase operations with 100-nanosecond pulses, roughly 10,000 times faster than earlier carbon nanotube memory, with retention exceeding four hours and endurance past 18,000 cycles. Digital demonstrations include 1-kilobit six-transistor SRAM arrays built with carbon nanotube CMOS, ternary logic gates that combine CNTFETs with resistive memory, and approximate multipliers for energy-efficient image processing. Wafer-scale synaptic transistors exploit the sensitivity of nanotubes to charged defects, positioning carbon at the heart of neuromorphic computing architectures that dissolve the boundary between logic and memory.

Even with this momentum, the review is candid about the barriers. Chirality-controlled synthesis of high-purity semiconducting tubes at wafer scale remains unsolved, and even small diameter variations shift bandgaps enough to scatter threshold voltages across a chip. Residual metallic tubes create leakage paths, contact engineering at the metal-carbon interface still introduces Schottky barriers and variability, and self-heating in real devices, where nanotube-to-substrate thermal boundary resistance limits heat dissipation, threatens reliability despite the exceptional intrinsic thermal conductivity of individual tubes. Uniform high-k dielectric deposition on chemically inert nanotube surfaces, variation-aware compact modeling, and back-end-of-line integration with existing CMOS flows round out the challenge list.

What emerges from the full picture is a technology standing at a genuine inflection point. The intrinsic material advantages of carbon nanotubes, from near-ballistic transport and diameter-tunable bandgaps to mechanical flexibility and bioscale sensitivity, are no longer in dispute. The remaining work is industrial: scalable purification, wafer-level alignment, stable low-resistance contacts, and standardized benchmarking against silicon and emerging two-dimensional materials. If those pieces fall into place, the authors conclude, CNTFETs are strong contenders to deliver the high-performance, energy-efficient, and miniaturized electronics that the next generation of computing, sensing, and communication systems will demand.

Subject of Research: Carbon nanotube field-effect transistors as post-silicon electronic devices

Article Title: Structure, modeling, fabrication, and applications of carbon nanotube field-effect transistors: a comprehensive review

Article References: Salem, N., Shaker, A., Ossaimee, M., Saeed, A., Abouelatta, M., & El-Rabaie, E.-S. M. (2026). Structure, modeling, fabrication, and applications of carbon nanotube field-effect transistors: a comprehensive review. Results in Physics, 89, Article 108749. https://doi.org/10.1016/j.rinp.2026.108749

Image Credits: AI Generated

DOI: 10.1016/j.rinp.2026.108749

Keywords: carbon nanotubes, CNTFET, field-effect transistors, post-silicon electronics, Moore's law, bandgap engineering, neuromorphic computing, biosensors, SRAM, CMOS compatibility, quantum transport, flexible electronics