The work, published in Frontiers in Photonics, tackles the central weakness of photonic neural networks: nonlinearity. Optical interference is superb at performing linear operations, such as the matrix–vector multiplications that dominate neural network workloads, essentially at the speed of light. But without nonlinear elements, cascaded optical stages collapse into a single linear transformation, incapable of expressing the rich functions that make deep learning powerful. Many photonic implementations sidestep this by converting light to electrons, processing, and converting back—an optical–electrical–optical detour that erodes the very latency advantage photonics promises.

The Heidelberg team, led by Wolfram Pernice at the Kirchhoff-Institute for Physics together with Holger Fröning’s group at the Institute of Computer Engineering, chose a different path. Their nonlinear unit is a photodiode directly wired to a microring modulator, fabricated on a CMOS-compatible silicon photonics platform through the Applied Micro Foundry multi-project wafer service. When light hits the silicon–germanium photodiode, the generated photocurrent flows straight into the forward-biased PN junction of the microring resonator. No amplification, no signal conditioning, no electronic detour. The injected carriers shift the resonator’s refractive index through the plasma dispersion effect, moving its resonance wavelength and thereby reshaping how much light the ring transmits. The result is a genuinely optical nonlinearity with only two physical control knobs.

Those two knobs are what make the device trainable. The optical power in the resonator’s bus waveguide sets the amplitude of the output, while an integrated microheater thermally tunes the ring resonance—about 20 milliwatts of electrical power per π-phase shift—positioning the Lorentzian-shaped resonance relative to the fixed signal wavelength. Operating near the steepest slope of the resonance yields strong nonlinear behavior; operating further away approaches quasi-linear response. Because both the through and drop ports of the resonator are accessible, the unit even offers complementary nonlinear responses with opposite slopes, a flexibility that proves useful when cascading multiple units.

Characterization revealed the device’s speed limit and, crucially, confirmed it is fast enough to matter. The microring showed an insertion loss of just 0.6 dB at 1,550 nm, and the photodiodes a responsivity of roughly 0.9 A/W. Under pulsed optical excitation producing photocurrents near 3 mA, the transmitted signal followed the input envelope with a measured rise time of approximately 8 nanoseconds—a figure set by the carrier recombination dynamics of forward-biased silicon carrier-injection modulators. Just as importantly, when the team compared the peak amplitudes of dynamically transmitted pulses against predictions from their static model, the agreement was strong, validating that the device’s nonlinear transfer function holds up under high-speed operation.

From these measurements the researchers built a differentiable software model in PyTorch, calibrated against the experimental data, in which photocurrent and heater current jointly determine the ring’s phase shift through carrier-induced and thermo-optic effects. This physical grounding is what elevates the work beyond a device demonstration. The team then asked a pointed architectural question: instead of multilayer perceptrons, which demand large numbers of nonlinear elements, why not exploit Kolmogorov–Arnold networks? These architectures place learnable univariate nonlinear functions along network edges rather than at nodes, a formulation rooted in the Kolmogorov–Arnold representation theorem that achieves expressive function approximation with reduced structural redundancy. The Lorentzian response of the microring, with its two learnable parameters, replaces the B-spline basis functions of the original mathematical formulation.

The photonic implementation imposed honest constraints. Optical fan-out from a single resonator to multiple downstream nodes is not supported, since splitting would require amplification stages that add loss and complexity; instead, signals follow merge-only routing, where many upstream edges can feed one photodiode but each edge connects to only one destination. The photodiode’s finite linear operating range caps how many signals can be combined at a node, and practical limits on chip area, routing, and the peripheral circuitry each ring needs—heaters, resonance stabilization, feedback control—restrict networks to at most a few hundred nonlinear units. Inputs are distributed to the first layer in a round-robin pattern to encourage early mixing of variables, and every subsequent layer obeys the merge-only discipline.

Despite these constraints, the simulated photonic Kolmogorov–Arnold networks approximated a demanding portfolio of structured functions with networks of only a few hundred units. Benchmarks drawn from the original KAN literature included Bessel functions of the first and second kind, modified Bessel functions, Jacobi elliptic sine, incomplete elliptic integrals, associated Legendre functions, spherical harmonics, and functions spanning up to 100 input dimensions. Root-mean-square errors ranged from slightly above zero down to near-machine precision across the set, with unit counts between 110 and 322 microrings. Even the challenging spherical harmonic case, among the highest-error functions, kept its relative residual below 6 percent across the entire domain and considerably smaller over most of the input region.

The comparison with alternative photonic KAN approaches is instructive. Recent ring-assisted Mach–Zehnder interferometer designs offer richer edge functions with nine trainable controls per edge, suited to accelerator-scale architectures with dense connectivity. The PD-MRM unit offers only two trainable parameters per edge, so hardware-constrained networks need more edges—for instance, 243 edges to fit a modified Bessel function that a conventional digital KAN fits with three spline edges. But each of those edges maps directly onto experimentally accessible device controls, and the compact unit is far easier to manufacture at scale. The two approaches, the authors argue, are complementary rather than competing.

There are honest limitations. Because optical intensities are non-negative and combine additively, the architecture cannot directly implement signed edge weights or cancellation, restricting expressivity for functions that inherently require subtractive combinations—though normalization and output-domain shifting recover negative-valued targets. The current model also omits noise sources such as thermal crosstalk and fabrication variability, although prior work suggests training algorithms can harden parametrizations against such physical noise. Looking forward, the team sees clear paths: engineering carrier dynamics through junction design for faster switching, replacing power-hungry thermal tuning with nonvolatile phase-change-material tuning that consumes virtually no electrical energy, and adopting coherent photonic schemes that enable subtraction through controlled interference. Because light propagates continuously through the network—downstream units begin responding the moment signal reaches them rather than waiting for sequential layer execution—inference latency scales sublinearly with depth, anchored by that 8-nanosecond activation time. For applications where microseconds separate success from failure, that physics may prove decisive.

Subject of Research: Photonic Kolmogorov-Arnold networks built from photodiode-microring nonlinear units for ultrafast optical inference

Article Title: Enabling photonic Kolmogorov-Arnold networks for ultra-fast inference

Article References: Pradip, R., Janssen, R., Varri, A., Gründel, N., Ebert, F., Durán, R. G., Lee, T., McRae, L., Römer, J., Schmidt, P., Bankwitz, J. R., Brückerhoff-Plückelmann, F., Fröning, H., & Pernice, W. (2026). Enabling photonic Kolmogorov-Arnold networks for ultra-fast inference. Frontiers in Photonics, 7, Article 1860010. https://doi.org/10.3389/fphot.2026.1860010

Image Credits: AI Generated

DOI: 10.3389/fphot.2026.1860010

Keywords: photonic neural networks, Kolmogorov-Arnold networks, silicon photonics, microring modulator, photodiode, nonlinear optics, ultrafast inference, neuromorphic photonics, CMOS compatibility, carrier injection, analog computing, low-latency AI

The secret to DLC’s versatility lies in its structure. The term does not describe a single material but a broad family of metastable amorphous carbon coatings characterized by different ratios of sp2 and sp3 hybridized bonds, often containing hydrogen or additional dopants. Carbon atoms with sp3 hybridization form tetrahedral bonds similar to those in diamond, delivering high hardness, high elastic modulus, excellent wear resistance, and a wide electronic bandgap. In contrast, sp2 hybridization produces graphitic structures with delocalized pi electrons, leading to higher electrical conductivity at the expense of hardness. Because most DLC films contain mixtures of both bonding states, their functional properties can be tailored by controlling deposition parameters and film composition, allowing engineers to dial in hardness, friction coefficient, electrical conductivity, optical transparency, chemical inertness, and biocompatibility.

Hydrogen incorporation represents another fundamental lever. Hydrogenated DLC films generally exhibit lower residual stress, reduced friction coefficients, improved chemical stability, and smoother surfaces compared with hydrogen-free coatings, but excessive hydrogen may reduce hardness, thermal stability, and wear resistance. The article classifies DLC materials into hydrogen-free amorphous carbon, hydrogenated amorphous carbon, tetrahedral amorphous carbon, doped systems, and advanced engineered architectures such as nanocomposite, multilayer, and graded films. Silicon incorporation can improve oxidation resistance, thermal stability, and adhesion while reducing internal stress, nitrogen doping modifies electrical conductivity, fluorine reduces surface energy and enhances hydrophobicity, and metallic dopants including tungsten, titanium, chromium, and silver have been investigated to improve conductivity, tribological behavior, catalytic activity, or antibacterial performance.

Why does this matter now? The rapid evolution of microsystems is reshaping the requirements imposed on engineering materials. Wearable healthcare devices, autonomous sensors, implantable medical systems, intelligent manufacturing, space exploration, and distributed Internet of Things networks all demand materials capable of performing multiple functions beyond conventional structural support. At the microscale, where surface forces dominate over inertial forces, the low coefficient of friction exhibited by many DLC coatings plays a crucial role in minimizing stiction, reducing energy losses, and extending device lifetime in microelectromechanical systems. Equally important is the outstanding chemical stability of DLC, which provides effective protection against corrosion, oxidation, and surface degradation in biological fluids, high humidity, and extreme temperatures, ensuring stable operation over prolonged periods.

The article is careful to note that DLC should not be regarded as a universal replacement for other functional thin-film materials. Silicon carbide offers excellent thermal stability for harsh-environment MEMS, silicon nitride and alumina provide outstanding dielectric properties, titanium nitride is widely employed as a hard conductive coating, and graphene exhibits exceptional electrical conductivity and flexibility. Polymeric coatings such as parylene offer excellent conformality but lower hardness, while self-assembled monolayers provide molecular-scale functionalization but lack mechanical robustness. DLC occupies a unique position by simultaneously combining high hardness, low friction, chemical inertness, tunable electrical properties, optical transparency, and excellent biocompatibility within a single coating platform, although these advantages are often accompanied by challenges related to residual stress, adhesion, and process optimization.

On the manufacturing side, plasma-enhanced chemical vapor deposition remains the most widely adopted technique for DLC synthesis because of its relatively low processing temperature, good film uniformity, and compatibility with complex three-dimensional geometries. Physical vapor deposition methods, including magnetron sputtering and filtered cathodic vacuum arc, have also gained considerable attention, while high-power impulse magnetron sputtering offers enhanced plasma ionization and improved control over film density, adhesion, and microstructure. One of the most important challenges for future deposition technologies is achieving high-performance DLC coatings at temperatures compatible with complementary metal–oxide–semiconductor processing and flexible polymer substrates, which will be essential for integrating DLC with flexible electronics, wearable sensors, and heterogeneous microsystems without compromising existing electronic components.

Characterization is equally critical, since the properties of DLC are highly sensitive to bonding configuration, hydrogen content, residual stress, and defect density. Raman spectroscopy remains the most widely employed tool for evaluating structural organization, providing valuable information on disorder and sp2 clustering, but it alone cannot accurately quantify the sp3 fraction and should be interpreted together with other techniques. X-ray photoelectron spectroscopy enables investigation of surface chemistry and dopant incorporation, electron energy loss spectroscopy offers insights into carbon hybridization, Fourier transform infrared spectroscopy identifies hydrogen bonding configurations, and nanoindentation remains the standard technique for measuring hardness and elastic modulus. Depending on the intended application, additional methods such as scratch testing, ball-on-disk tribometry, and electrochemical impedance spectroscopy assess adhesion, tribological performance, and corrosion resistance.

The emerging applications are striking. In flexible and stretchable microsystems, careful control of deposition parameters, hydrogen content, film thickness, and doping enables DLC coatings with reduced residual stress and improved flexibility suitable for polymeric substrates, while structural engineering approaches such as island-bridge layouts, serpentine interconnects, and kirigami-inspired geometries accommodate large mechanical deformation. In BioMEMS and biomedical microdevices, properly engineered DLC surfaces can support cell adhesion while minimizing inflammatory responses, and surface functionalization enables highly selective biosensors capable of detecting biomarkers, pathogens, or metabolites. The article emphasizes that biological evaluation should rely on standardized testing protocols from the ISO 10993 series rather than isolated biocompatibility claims, since protein adsorption, hemocompatibility, and bacterial colonization depend strongly on surface chemistry, roughness, wettability, and elemental doping.

Looking further afield, DLC coatings could improve the durability and performance of microbatteries, microsupercapacitors, piezoelectric and triboelectric energy harvesters, and miniaturized power management devices. Hybrid structures combining DLC with two-dimensional materials or carbon nanostructures may lead to devices with enhanced sensing capabilities, improved charge transport, and superior mechanical performance, potentially enabling applications in photonic microsystems, quantum sensing, and high-performance environmental monitoring. Machine learning algorithms, high-throughput experimentation, and real-time process monitoring may accelerate the optimization of deposition parameters and material properties, and sustainability is likely to become an important driver, with low-temperature deposition processes and energy-efficient manufacturing routes reducing the environmental impact of thin-film fabrication.

Significant barriers remain before DLC’s full potential can be realized. Precise control of residual stress directly influences film adhesion, mechanical reliability, and long-term stability, and stress management continues to limit the deposition of thick, defect-free coatings and their integration with fragile microstructures. From an industrial perspective, reproducibility and scalability remain significant obstacles: achieving uniform coatings over large areas, ensuring consistent film properties across production batches, and establishing standardized characterization and qualification protocols are critical steps toward commercial implementation. The article outlines a phased outlook, with short-term efforts focused on deposition reproducibility and CMOS-compatible low-temperature processes, medium-term advances emphasizing multifunctional coatings and AI-assisted process optimization, and longer-term convergence with intelligent manufacturing and self-powered microsystems. The future impact of diamond-like carbon, the article concludes, will depend on the convergence of materials science, microfabrication, device engineering, and sustainable manufacturing, transforming DLC into a key enabling material for reliable, multifunctional, and highly integrated microsystems supporting advances in healthcare, environmental monitoring, smart manufacturing, and future microelectronic devices.

Subject of Research: Diamond-like carbon films as multifunctional platform materials for MEMS, flexible electronics, and biomedical microdevices

Article Title: Future directions for diamond-like carbon in microsystems and microdevices

Article References: Fraga, M. A. (2026). Future directions for diamond-like carbon in microsystems and microdevices. Frontiers in Carbon, 5, Article 1924248. https://doi.org/10.3389/frcrb.2026.1924248

Image Credits: AI Generated

DOI: 10.3389/frcrb.2026.1924248

Keywords: diamond-like carbon, DLC films, MEMS, microsystems, thin-film deposition, CMOS compatibility, biocompatibility, flexible electronics, residual stress, surface functionalization, tribology, BioMEMS

NY Creates, the Albany-based New York Center for Research, Economic Advancement, Technology, Engineering, and Science, has announced its participation in the newly funded Manufacturable and Resilient superconducting QUantum Information Systems, or MARQUIS, Quantum Leap Challenge Institute. The institute is a flagship program of the U.S. National Science Foundation and is led by Princeton University. According to the agency, MARQUIS is receiving $27.9 million in NSF funding over five years, and NY Creates will receive approximately $1.25 million of that total to support research, technology scaling, and workforce development activities aimed at advancing quantum computing technologies.

The central obstacle MARQUIS confronts is one that has shadowed superconducting quantum computing since its earliest days: the materials and fabrication techniques underpinning today’s qubits have barely evolved in decades. Nathalie de Leon, professor of electrical and computer engineering at Princeton University and director of the new institute, described the problem bluntly. “The whole community has been using essentially the same materials technology for about a quarter century,” she said. “That technology has worked well for experimental prototypes and small-scale systems. But to build quantum computers at a scientifically useful scale, the most basic elements must be reinvented.” She added that having a few key experts in the field who know what the right waypoints are and how to think about it is really crucial.

Understanding why this reinvention is necessary requires a brief look at how superconducting quantum computers work. At the heart of these machines are qubits, the quantum analogues of the bits in classical computing. Unlike ordinary bits, which must be either zero or one, qubits can exist in superpositions of both states simultaneously, and they can become entangled with one another in ways that allow certain calculations to be performed with dramatically fewer resources than classical machines would require. Superconducting qubits, the approach pursued by MARQUIS, rely on tiny electrical circuits cooled to temperatures near absolute zero, where resistance vanishes and quantum effects dominate. These circuits incorporate Josephson junctions, nanoscale sandwich structures of superconducting materials separated by insulating barriers, which act as the nonlinear elements that make quantum computation possible.

The trouble is that these junctions and the materials surrounding them are exquisitely sensitive. Microscopic defects, impurities, and inconsistencies introduced during fabrication can cause decoherence, the process by which fragile quantum states leak information to their environment and collapse into useless classical noise. As researchers scale from processors with dozens or hundreds of qubits to the thousands or millions needed for scientifically and commercially meaningful computation, the variability of fabrication becomes an increasingly punishing bottleneck. A process that works acceptably for a handful of devices in a university cleanroom may fail catastrophically when applied across an entire wafer of thousands of components.

This is precisely where NY Creates brings distinctive value to the consortium. The organization operates advanced 300-millimeter semiconductor research and development infrastructure, the wafer format that dominates industrial chip manufacturing worldwide. As part of MARQUIS, the NY Creates team, led by Dr. Satyavolu Papa Rao, Senior Director of Emerging Technologies and Research at the organization, will work with institute partners to test innovative materials and processes at the 300-millimeter wafer scale, targeting mid-scale superconducting quantum processors. Working at wafer scale means that new materials and fabrication recipes can be evaluated under conditions that closely resemble real industrial production, rather than the small-batch conditions typical of academic laboratories.

“Creates is uniquely positioned to help bridge the gap between breakthrough quantum research and scalable manufacturing,” Papa Rao said. “Through our advanced 300mm semiconductor R&D infrastructure and deep industry partnerships, we will work alongside MARQUIS collaborators to evaluate, translate, and scale promising quantum materials and processes, helping to accelerate the development of manufacturable quantum technologies while strengthening the nation’s quantum workforce and semiconductor innovation ecosystem.”

Beyond testing new materials, the NY Creates team will collaborate with MARQUIS researchers to identify critical data and process insights that could improve the scalability of materials and fabrication approaches for quantum devices within industry-standard CMOS-compatible manufacturing environments. CMOS, the complementary metal-oxide-semiconductor technology that underpins virtually all modern electronics, represents the gold standard for manufacturability. Ensuring that quantum device innovations remain compatible with CMOS-style processes is a strategic bet: it means that whatever succeeds in the laboratory has a plausible path into the enormous existing infrastructure of the semiconductor industry, rather than requiring an entirely new fabrication ecosystem to be built from scratch.

The institute’s ambitions extend well beyond fabrication alone. NY Creates will also support MARQUIS efforts to develop databases of materials, processes, and device structures that can help researchers better understand the factors influencing quantum device performance, decoherence, and process variability. Such databases could prove transformative for the field, which has historically relied on scattered, hard-to-compare experimental results. Systematic, shared data on how specific material combinations and processing steps affect qubit coherence times and yield would allow researchers to iterate far more quickly, applying the kind of data-driven optimization that revolutionized classical semiconductor development over past decades.

Workforce development forms a third pillar of NY Creates’ contribution, and it addresses a widely recognized vulnerability in the American quantum enterprise. The quantum industry is growing faster than the supply of people trained to work in it, and the specialized skills required, spanning quantum physics, cryogenic engineering, materials science, and precision fabrication, are scarce. Through MARQUIS, NY Creates will work with institute partners to expand opportunities for students and postdoctoral researchers to gain hands-on experience with advanced semiconductor manufacturing environments through periodic site visits and collaborative learning experiences. The goal is to cultivate a generation of scientists, engineers, and technologists who are equally comfortable with quantum theory and with the practical realities of high-volume chip fabrication.

The breadth of the consortium reflects the scale of the challenge. The Princeton-led MARQUIS institute brings together researchers from Princeton University, Cornell University, the Massachusetts Institute of Technology, the University of California at Santa Barbara, Stanford University, Dartmouth College, NY Creates, Michigan State University, and the University of Iowa. These institutions contribute expertise across materials science, quantum devices, and semiconductor processing, spanning two dozen laboratories in total. The initiative is further supported by an advisory board that includes representatives from Google Quantum AI, NVIDIA, Applied Materials, Oxford Instruments, Bluefors, KU Leuven/imec, and MIT Lincoln Laboratory, a lineup that spans the leading quantum computing companies, the dominant suppliers of semiconductor fabrication equipment, and the major providers of cryogenic systems essential to superconducting quantum hardware.

Dave Anderson, President and CEO of NY Creates, framed the award as a milestone for both the organization and the region. “This award reflects the growing importance of integrating world-class semiconductor manufacturing expertise with leading-edge quantum research,” Anderson said. “As a partner in this exceptional consortium of leading universities, industry partners, and research institutions, Creates will help advance technologies that are critical to the future of quantum computing and America’s scientific and economic competitiveness. The MARQUIS initiative also reinforces New York’s leadership in semiconductor innovation while creating valuable opportunities to educate and train the next generation of scientists, engineers, and technologists who will drive quantum-based economic growth.”

The stakes for the United States are considerable. Quantum computing is widely viewed as a strategic technology, one with potential implications for national security, pharmaceutical development, financial modeling, and materials design. Nations around the world, including China and members of the European Union, have committed billions of dollars to quantum research and development, and leadership in the field is increasingly seen as inseparable from broader economic and technological competitiveness. By pairing the fundamental scientific expertise of its leading universities with the manufacturing know-how embedded in organizations like NY Creates, the MARQUIS institute represents a deliberate attempt to ensure that American quantum discoveries do not stall at the prototype stage but instead flow into scalable, domestic production.

MARQUIS is one of several Quantum Leap Challenge Institutes established by the National Science Foundation as part of a broader federal push in quantum science, and it embodies a philosophy that is gaining traction across the field: the bottleneck to useful quantum computers is no longer only a matter of physics but also of engineering discipline, manufacturing rigor, and human capital. If the institute succeeds in reinventing the basic elements of superconducting qubits and embedding them in CMOS-compatible, wafer-scale processes, the consequences could ripple far beyond the laboratory. Quantum processors that can be fabricated reliably, in quantity, and with predictable performance would move the field decisively closer to the day when quantum machines tackle problems no classical computer ever could, and the groundwork for that transition is now being laid, one wafer at a time, in Albany and its partner institutions across the country.

Subject of Research: Manufacturable superconducting quantum computing hardware and fabrication

Article Title: NY Creates joins Princeton-led NSF Quantum Institute to advance next-generation quantum computing

Article References: NY Creates joins Princeton-led NSF Quantum Institute to advance next-generation quantum computing. (n.d.). Original publication

Image Credits: AI Generated

DOI: Not provided

Keywords: quantum computing, superconducting qubits, MARQUIS, National Science Foundation, Princeton University, NY Creates, semiconductor manufacturing, 300mm wafer, CMOS compatibility, decoherence, workforce development, Josephson junctions

The motivation behind the work is the growing mismatch between the relentless growth of global data and the physical limits of electronic memory. Conventional silicon-based architectures, despite decades of refinement, are approaching hard boundaries in scalability, speed, and power density. All-optical memories, which encode, store, and retrieve information entirely within the optical domain, promise high transfer rates, low latency, and favorable energy efficiency. Yet each competing approach carries drawbacks: silicon-on-insulator platforms suffer from high losses, localized surface plasmon resonance structures are limited by ohmic losses and fabrication complexity, photonic crystals demand extreme fabrication precision, and Kerr nonlinear materials require high optical intensities and are sensitive to noise. Phase-change materials stand apart because they retain data even after the light source is removed, thanks to their non-volatile nature and high optical contrast between structural states.

The heart of the new device is a dumbbell-shaped resonator: a rectangular cavity flanked by two semi-disk resonators, coupled to MIM input and output waveguides carved in silver with air serving as the dielectric. Surface plasmon polaritons, hybrid waves of light and collective electron oscillations, are confined to the metal-dielectric interfaces and squeezed into regions far smaller than the wavelength of light. The team modeled the optical response of silver with the Drude formalism and validated the design using two-dimensional finite-difference time-domain (FDTD) simulations with a 3-nanometer mesh and perfectly matched layer boundaries. As a passive filter, the structure exhibits a Gaussian transmission peak at 1210 nanometers with a peak transmittance of 91 percent, a full width at half maximum of 56 nanometers, and a quality factor of about 21.

Geometry proved to be the decisive lever in tuning performance. Through systematic parametric sweep simulations, the researchers found that the radius of the semi-disk resonators dominates the resonance wavelength, shifting it by 2.22 nanometers for every nanometer of radius change, while the width of the rectangular cavity induces a blueshift at a sensitivity of minus 0.69 nanometers per nanometer, and the cavity length contributes a modest redshift of 0.3 nanometers per nanometer. The coupling gap between the waveguides and the resonator, varied from 0 to 18 nanometers, showed that transmission degrades progressively as the gap widens, because the evanescent field that transfers energy between the waveguide and the cavity decays exponentially with distance. Notably, the optimal configuration is a zero-gap, monolithic design, which sidesteps the notoriously difficult requirement of maintaining sub-10-nanometer alignment during fabrication.

Transforming this filter into memory required integrating a strip of GST, measuring 500 by 190 nanometers, into the central resonator and introducing a second optical pathway. A control signal, delivered from above the chip by a laser, programs the memory: a SET pulse of 50 milliwatts lasting 150 nanoseconds, roughly 7.5 nanojoules, gently heats the material above its crystallization temperature of about 450 kelvin, converting it from the amorphous to the crystalline state. A RESET pulse of 110 milliwatts for 20 nanoseconds, about 2.2 nanojoules, melts the material at roughly 880 kelvin before it rapidly quenches back into the amorphous phase. Crucially, this programming is spatially and functionally decoupled from the readout, which uses a low-power probe signal sent through the MIM waveguide, too weak to disturb the stored phase state.

The readout mechanism exploits the dramatic optical difference between the two phases of GST. In the amorphous state, the refractive index is 3.94 with low absorption, and the device transmits a resonance peak at 1912 nanometers with 95 percent transmittance, corresponding to logic state 1. In the crystalline state, both the real and imaginary refractive indices rise sharply to 6.11 plus 0.83i, absorption soars, and transmission drops to essentially zero, registering logic state 0. The contrast between the states reaches 95 percent, the extinction ratio reaches 25 decibels, and the insertion loss is a remarkably low 0.19 decibels in the amorphous state versus 25.2 decibels in the crystalline state. Because the phase persists without power, the bit is genuinely non-volatile, classifying the device within the PRAM and NVRAM families of memory.

The team went beyond static spectra and performed transient femtosecond-scale analysis using a square excitation pulse. In the amorphous state, the output rises to 95 percent of the input within about 200 femtoseconds after a 7-femtosecond propagation delay, with rise and fall times of 82 and 84 femtoseconds respectively, before ohmic losses drain the signal by roughly 1100 femtoseconds. In the crystalline state, the output settles at only about 4 percent, an OFF regime with minimal leakage. A reference simulation without the GST-loaded resonator confirmed that the MIM waveguides themselves preserve signal integrity with negligible distortion, meaning any temporal modification originates from the light-matter interaction inside the resonator. The researchers note that while these read dynamics reflect the electromagnetic impulse response rather than the slower phase-change kinetics, existing experimental literature supports GST switching frequencies between 1 and 10 megahertz with endurance up to one million cycles.

Perhaps the most forward-looking aspect of the design is its neuromorphic potential. The optical transmittance of the resonator is governed by the complex refractive index of the GST layer, and GST is well documented to undergo fractional crystallization, passing through intermediate states between fully amorphous and fully crystalline. Each intermediate state yields a distinct transmission level, which can be mapped onto an analog synaptic weight. The high-transmission amorphous state corresponds to a potentiated synapse, while the low-transmission crystalline state represents a depressed one. The authors frame the device as a scalable building block for all-optical neuromorphic synapses, potentially enabling spike-timing-dependent plasticity through tailored pulse-programming sequences in future circuits, thereby merging logic and memory on a single photonic platform in a departure from conventional von Neumann architectures.

Practical integration also received attention. The device is compatible with back-end-of-line CMOS processes, relying on standard techniques such as electron-beam evaporation, sputtering, electron-beam lithography, and reactive ion etching. The monolithic zero-gap resonant cavity can be patterned as a single continuous unit, eliminating fragile alignment steps, and sensitivity analysis confirms that performance peaks precisely at this configuration. Ultra-thin passivation layers of silicon dioxide or aluminum oxide can shield the silver from oxidation without compromising plasmonic confinement, while the high thermal conductivity of the silver substrate acts as a passive heat sink that, combined with nanosecond control pulses, suppresses thermal crosstalk. The authors acknowledge that the design deliberately prioritizes high transmission over an ultra-high quality factor, because the active GST layer introduces losses during switching and a strong baseline signal is essential for reliably distinguishing the two logic states. Compared against a broad field of plasmonic and photonic-crystal memories built on GST and Kerr materials, the proposed cell posts the highest transmission contrast in its class while remaining among the most compact, suggesting that light-written, power-free memory at the nanoscale may be moving from concept toward chip-ready reality.

Subject of Research: A non-volatile plasmonic memory based on an MIM waveguide and GST phase-change material for binary logic and neuromorphic computing

Article Title: Design of a non-volatile Plasmonic Memory Based on MIM waveguide and phase-change Materia for binary logic and neuromorphic integration

Article References: Kehtarmanesh, M., Keshavarzi, P., & Danaie, M. (2026). Design of a non-volatile Plasmonic Memory Based on MIM waveguide and phase-change Materia for binary logic and neuromorphic integration. Results in Optics, 25, Article 101141. https://doi.org/10.1016/j.rio.2026.101141

Image Credits: AI Generated

DOI: 10.1016/j.rio.2026.101141

Keywords: plasmonics, phase-change material, GST, non-volatile memory, MIM waveguide, optical memory, neuromorphic computing, photonic integrated circuits, FDTD simulation, optical contrast, synaptic weight, CMOS compatibility

Monolithic 3D integration differs from the chip-stacking approaches used in today’s advanced packaging. Instead of fabricating separate dies and bonding them together with relatively coarse interconnects, monolithic 3D integration builds successive device layers sequentially on the same wafer. Each new tier of transistors is grown and patterned directly on top of the interconnect stack of the tier below. This allows extremely dense vertical connections between logic and memory, dramatically shortening the distances data must travel and opening the door to computing architectures in which memory and processing are woven together in three dimensions. The obstacle has always been thermal budget: conventional silicon processing requires temperatures that would destroy the metal interconnects and devices already in place beneath a new layer, so any channel material added on top must be deposited and processed at low temperatures.

The Purdue team, led by Peide D. Ye of the Elmore Family School of Electrical and Computer Engineering, turned to indium oxide deposited by atomic layer deposition, a technique in which the semiconductor film grows one atomic layer at a time through self-limiting surface reactions. Atomic layer deposition offers exceptional thickness control and superb conformality across large substrates, and the resulting amorphous indium oxide films can be processed at temperatures well within the tolerance of back-end-of-line metallization. Because the films are amorphous rather than crystalline, they sidestep the grain-boundary and lattice-matching problems that plague many alternative low-temperature channel materials, including two-dimensional semiconductors that have attracted enormous attention for the same application.

The demonstration is remarkable for its breadth of device functionality. On the 200-millimeter wafers, the researchers fabricated three tiers of devices spanning ferroelectric field-effect transistors for non-volatile memory, as well as enhancement-mode and depletion-mode field-effect transistors for logic. Ferroelectric transistors hold their stored state without power, enhancement-mode devices switch off cleanly at zero gate voltage, and depletion-mode devices conduct by default, so together they form a complete transistor toolkit suitable for real circuit design. The electrical statistics across the wafers are equally notable. Threshold voltage standard deviations as low as 0.04 volts were achieved, a level of uniformity that rivals commercial silicon devices and indicates that the low-temperature process is genuinely manufacturable rather than a laboratory curiosity. Average electron mobilities reached up to 91.6 square centimeters per volt-second, high enough to support fast switching and strong drive currents in dense vertical layouts.

Uniformity at wafer scale is arguably the central achievement here. Research groups have previously shown promising oxide semiconductor transistors on small chip-scale samples, but moving to a 200-millimeter platform subjects every device to the same statistical scrutiny that foundry engineers apply to silicon. The team systematically characterized how processing variations, including annealing temperatures and capping steps, affected each device family. They found that a surface-capping layer followed by a 300-degree-Celsius anneal substantially improved bias stability, suppressing the threshold voltage drift that can undermine reliability during sustained operation. Statistical distributions of subthreshold swing, threshold voltage, and memory window remained tight across hundreds of measured devices per condition, with sample sizes running into the hundreds for each device type tested.

Thermal robustness was verified layer by layer. Because each tier of devices must survive the processing of the tiers fabricated above it, the researchers subjected finished transistors to the full thermal sequence and re-measured them. Mobility, threshold voltage, and subthreshold characteristics were preserved with negligible shift after the complete stack processing, confirming that indium oxide can endure the cumulative thermal exposure of a multi-tier build. The team also engineered the channel thickness to select device behavior: thinner films of about 1.5 nanometers yielded enhancement-mode operation, while thicker films near 3.0 nanometers produced depletion-mode devices, giving circuit designers the complementary options they need for power-efficient logic within the same material system.

With three functional tiers established, the researchers went beyond device statistics and demonstrated fully functional cross-tier circuits, in which signals travel vertically through inter-tier vias connecting transistors on different layers. This vertical wiring capability is what transforms stacked transistors from a density trick into a genuine architectural opportunity. Logic and memory separated by microns of horizontal wiring in a conventional planar chip can instead sit directly atop one another, connected by short vertical links. The team used a custom process design kit built around compact models of their indium oxide transistors, including a standard cell library of eleven logic gates verified through D flip-flop simulations, to bridge the gap between measured device behavior and large-scale circuit design.

The system-level payoff was quantified in the design of a four-tier 3D computing-in-memory accelerator targeting large-language-model workloads. Computing-in-memory architectures perform matrix operations directly inside memory arrays, sidestepping the energy cost of shuttling data between separate memory and processor units, a bottleneck that dominates the power budget of modern artificial intelligence systems. By vertically interleaving logic and memory tiers made from the same low-temperature oxide platform, the proposed accelerator exploits the short inter-tier connections that monolithic integration uniquely enables. Benchmark simulations showed speed-ups of 1.4 times to 2.9 times over comparable two-dimensional baselines, together with comparable improvements in energy-delay product, a metric that captures both how fast a workload completes and how much energy it consumes.

The significance for the semiconductor industry lies in the convergence of manufacturability and application pull. Data centers running large language models are straining power grids, and the energy cost of moving data between memory and logic has become the defining constraint of AI hardware. A low-temperature, wafer-scale, CMOS-compatible platform for stacking logic and memory in three dimensions offers a way to attack that constraint directly, without abandoning the existing silicon infrastructure. Because the entire integration happens on standard 200-millimeter wafers using back-end-of-line-compatible processing, the approach could in principle be adopted as an additional module within existing foundry flows rather than requiring a wholesale reinvention of the fabrication plant.

Challenges remain before such stacks reach commercial products. The accelerator results reported here come from design and simulation benchmarked against the measured device data rather than from a fully fabricated four-tier chip, and scaling the demonstrated three-tier integration to four or more tiers will demand continued control of yield and variability across the stack. Nevertheless, the demonstration answers the question that has lingered over monolithic 3D integration for years: whether any low-temperature channel material can deliver both the electrical performance and the wafer-scale uniformity that real manufacturing requires. With atomic-layer-deposited indium oxide now shown to do so on an industry-standard substrate, the vertical dimension of computing has moved from concept toward the fabrication line.

Subject of Research: Monolithic 3D integration of atomic-layer-deposited indium oxide semiconductor devices on 200-mm silicon wafers for vertically stacked logic and memory in AI hardware

Article Title: Monolithic 3D integration of atomic-layer-deposited oxide semiconductors on 200-mm silicon wafers

Article References: Niu, C., Long, L., Zheng, L., Du, S., Lin, J.-Y., Nam, K., Lin, Z., Liu, C., Lu, J., Wang, H., Li, H., & Ye, P. D. (2026). Monolithic 3D integration of atomic-layer-deposited oxide semiconductors on 200-mm silicon wafers. Nature Nanotechnology. https://doi.org/10.1038/s41565-026-02276-0

Image Credits: AI Generated

DOI: 10.1038/s41565-026-02276-0

Keywords: monolithic 3D integration, indium oxide semiconductor, atomic layer deposition, 200-mm wafer, back-end-of-line processing, ferroelectric field-effect transistor, computing-in-memory, AI accelerator, large language models, CMOS compatibility, threshold voltage uniformity, three-dimensional chip stacking

The review, authored by Nada Salem, Ahmed Shaker, Mahmoud Ossaimee, Ahmed Saeed, Mohamed Abouelatta, and El-Sayed M. El-Rabaie, takes an unusually integrated approach. Rather than treating device physics, manufacturing, and circuit applications as separate silos, the authors connect the atomic structure of carbon nanotubes directly to transistor behavior and ultimately to commercial viability. This matters because the performance of a CNTFET is not determined by the nanotube alone; contact resistance, tube alignment, density control, metallic-tube removal, and compatibility with existing CMOS manufacturing all shape whether carbon can genuinely replace silicon in a factory setting.

At the heart of the technology lies a deceptively simple material trick. A carbon nanotube is a sheet of graphene rolled into a cylinder roughly one nanometer in diameter, and the precise way it is rolled, defined by its chirality indices (n, m), determines whether it behaves as a metal or a semiconductor. Tubes in which the difference between the two indices is divisible by three are nominally metallic, while the rest are semiconducting. For semiconducting single-walled tubes, the bandgap scales approximately inversely with diameter, following the relation Eg of about 0.84 divided by the diameter in nanometers. That simple formula gives device engineers a powerful tuning knob: choosing the tube diameter effectively sets the threshold voltage, the leakage current, and the ON-state current of the resulting transistor.

The physics inside these devices is equally striking. Because carriers are confined to a one-dimensional channel, transport can approach the ballistic limit, where electrons traverse the channel without scattering. Clean carbon nanotube channels have demonstrated carrier mobilities of roughly 1,000 to 10,000 square centimeters per volt-second, an order of magnitude or more above scaled silicon, with characteristic carrier velocities of 2 to 5 times ten to the seventh centimeters per second against a theoretical Fermi velocity ceiling near 8 times ten to the seventh. Subthreshold swings can approach 60 to 80 millivolts per decade, and ON/OFF current ratios spanning 10^5 to 10^8 have been reported depending on diameter, contacts, and dielectric engineering. These numbers explain why researchers have chased carbon nanotubes since the first CNTFET was demonstrated in 1998.

Architecture has evolved considerably since those early proof-of-concept devices. Back-gated transistors, in which the silicon substrate itself acts as the gate, were simple to build but suffered from contact resistances of a megohm or more and weak electrostatic control. Top-gated designs introduced thin dielectrics deposited by atomic layer deposition, tightening gate coupling and enabling individual devices to be isolated on a single wafer. Wrap-around or gate-all-around structures, demonstrated in 2008, surround the nanotube entirely, suppressing leakage and short-channel effects most effectively. Suspended devices, in which the tube hangs free over a trench, minimize substrate scattering and reveal the intrinsic transport properties of the material, though mechanical instability and limited dielectric options keep them largely a laboratory tool.

Modeling this zoo of devices has produced a rich theoretical landscape. Ballistic models, built on the Landauer formalism, estimate the performance ceiling of ideal short-channel devices. Quasi-ballistic and non-ballistic models add phonon scattering through virtual-source and Landauer-Büttiker approaches, capturing the roughly 30 percent current reduction that dissipative transport imposes in realistic channels. Tunneling-based compact models account for band-to-band tunneling that dominates in small-bandgap tubes under bias, while full non-equilibrium Green’s function formulations solve quantum transport self-consistently with electrostatics, linking device behavior directly to the chiral index of the tube. For circuit designers, SPICE-compatible compact models such as the Stanford virtual-source CNFET model bridge the gap, embedding quantum capacitance, contact resistance, and ambipolar conduction into tools that can evaluate logic, memory, and radio-frequency circuits.

Fabrication remains the decisive battleground. Modern processes grow horizontally aligned nanotube arrays on quartz by chemical vapor deposition at densities near three tubes per micrometer, transfer them to oxidized silicon wafers, selectively remove metallic tubes, and deposit high-k gate stacks of titanium dioxide with titanium-platinum electrodes. The resulting devices show improved ON/OFF ratios and reduced device-to-device variability, and the low processing temperatures make the route compatible with CMOS thermal budgets. On a very different frontier, aerosol jet printing has been used to fabricate working CNTFETs on flexible Kapton substrates using silver ink electrodes and cross-linked polymer dielectrics, opening a path toward wearable and bendable electronics that rigid silicon cannot serve.

The application portfolio is expanding fast. CNTFET biosensors have detected the H1N1 virus, DNA modifications, prostate-specific antigen at concentrations from 5 to 5000 picograms per milliliter, and SARS-CoV-2 spike protein epitopes within minutes, exploiting the nanometer-scale match between tube and biomolecule. In memory research, devices using hafnium oxide gates have achieved write and erase operations with 100-nanosecond pulses, roughly 10,000 times faster than earlier carbon nanotube memory, with retention exceeding four hours and endurance past 18,000 cycles. Digital demonstrations include 1-kilobit six-transistor SRAM arrays built with carbon nanotube CMOS, ternary logic gates that combine CNTFETs with resistive memory, and approximate multipliers for energy-efficient image processing. Wafer-scale synaptic transistors exploit the sensitivity of nanotubes to charged defects, positioning carbon at the heart of neuromorphic computing architectures that dissolve the boundary between logic and memory.

Even with this momentum, the review is candid about the barriers. Chirality-controlled synthesis of high-purity semiconducting tubes at wafer scale remains unsolved, and even small diameter variations shift bandgaps enough to scatter threshold voltages across a chip. Residual metallic tubes create leakage paths, contact engineering at the metal-carbon interface still introduces Schottky barriers and variability, and self-heating in real devices, where nanotube-to-substrate thermal boundary resistance limits heat dissipation, threatens reliability despite the exceptional intrinsic thermal conductivity of individual tubes. Uniform high-k dielectric deposition on chemically inert nanotube surfaces, variation-aware compact modeling, and back-end-of-line integration with existing CMOS flows round out the challenge list.

What emerges from the full picture is a technology standing at a genuine inflection point. The intrinsic material advantages of carbon nanotubes, from near-ballistic transport and diameter-tunable bandgaps to mechanical flexibility and bioscale sensitivity, are no longer in dispute. The remaining work is industrial: scalable purification, wafer-level alignment, stable low-resistance contacts, and standardized benchmarking against silicon and emerging two-dimensional materials. If those pieces fall into place, the authors conclude, CNTFETs are strong contenders to deliver the high-performance, energy-efficient, and miniaturized electronics that the next generation of computing, sensing, and communication systems will demand.

Subject of Research: Carbon nanotube field-effect transistors as post-silicon electronic devices

Article Title: Structure, modeling, fabrication, and applications of carbon nanotube field-effect transistors: a comprehensive review

Article References: Salem, N., Shaker, A., Ossaimee, M., Saeed, A., Abouelatta, M., & El-Rabaie, E.-S. M. (2026). Structure, modeling, fabrication, and applications of carbon nanotube field-effect transistors: a comprehensive review. Results in Physics, 89, Article 108749. https://doi.org/10.1016/j.rinp.2026.108749

Image Credits: AI Generated

DOI: 10.1016/j.rinp.2026.108749

Keywords: carbon nanotubes, CNTFET, field-effect transistors, post-silicon electronics, Moore's law, bandgap engineering, neuromorphic computing, biosensors, SRAM, CMOS compatibility, quantum transport, flexible electronics