Their design, published in Results in Engineering, uses only a single differential differencing gain amplifier, abbreviated DDGA, together with one grounded passive element. Depending on how the transconductance gains of the amplifier are biased, the same topology can behave as a lossless inductor, a positive or negative lossy series inductor, or a positive or negative lossy parallel inductor. Replacing the ordinary grounded capacitor with a grounded fractional-order capacitor extends the circuit into the fractional calculus domain, yielding a fractional-order inductor whose phase response falls between that of a resistor and an ideal inductor.

The DDGA itself is a recently introduced active building block with two differential high-impedance input terminal pairs, labeled p1, n1 and p2, n2, and three output terminals named z, o, and w. All ports exhibit high impedance except the w terminal. The element is characterized by electronically adjustable transconductance gains gmA, gmB, gmC, and gmD, each of which can be tuned by changing a corresponding DC bias current, plus a voltage transfer gain beta between the z and w terminals. In the CMOS implementation, floating current-controlled current sources formed from transistors act as the tunable transconductance amplifiers, and the gain of each unit depends directly on its bias current. This electronic adjustability is what allows one fixed circuit to produce several distinct inductive behaviors without changing a single component.

The mathematics behind the integer-order operation is straightforward. When a grounded capacitor C1 is connected, analysis using Kirchhoff’s current law yields an equivalent input impedance of the form Zeq1 = beta(gmB – gmA)/(gmA gmC) + sC1/(gmA gmC), which is exactly the impedance of a series RL network. If the two gains gmA and gmB are set equal, the resistive term vanishes and the circuit becomes a lossless inductor with equivalent inductance Leq1 = C1/(gmA gmC). If gmA is smaller than gmB, a positive series resistance appears, producing a positive lossy series inductor. If gmA exceeds gmB, the resistive term flips sign, and the circuit emulates a negative lossy series inductor. A parallel configuration built on the same principle behaves analogously, with the conductance term governed by beta(gmA – gmB) and the inductive admittance term set by gmB, gmC, and the capacitor C2. In every case, both the equivalent resistance and the equivalent inductance are electronically controllable through the transconductance gains.

The fractional-order extension replaces the standard capacitor with a fractional-order capacitor, an element whose impedance is proportional to 1/(s^alpha C_alpha), where the fractional order alpha lies between zero and one. Because no ideal fractional-order capacitor exists as a commercial off-the-shelf device, the authors synthesize its behavior over a chosen frequency band using an N-th order ladder Cauer-I RC network. The component values for fractional orders from alpha = 0.1 to 0.9 were tabulated to achieve a magnitude slope of -20 alpha dB per decade and a constant phase angle of -alpha times 90 degrees. Substituting this network into the same DDGA topology produces a fractional-order inductor whose impedance is proportional to s^alpha, giving a phase shift of alpha times 90 degrees that deviates intrinsically from the exact 90 degrees of an ideal integer-order inductor.

All reported performance figures come from PSPICE simulations using TSMC 180-nanometer CMOS parameters with supply voltages of plus and minus 0.9 V, not from fabricated hardware. The passive values and bias currents were chosen so that, for example, the lossless configuration with a 20 pF capacitor and 1 mA/V gains yields an equivalent inductance of 20 microhenries, while the lossy variants produce equivalent resistances of 1 kilohm or -0.5 kilohm with inductances of 10 to 20 microhenries. Transient tests applied a 50 mV peak sinusoidal input at 10 MHz, or 1 MHz for the parallel lossless case. Electronic tunability was demonstrated by varying the bias current IBC through 50, 130, and 310 microamperes, with total static power consumption for the lossless inductor measured at 1.62, 1.95, and 2.64 mW respectively, and 2.43 to 3.45 mW for the lossy series and parallel configurations.

The simulation study also mapped out the usable operating windows. Using a criterion in which the simulated phase must stay within 10 percent of the ideal value, the lossless series inductor operated properly from roughly 1 MHz to 50 MHz, while the positive and negative lossy series topologies spanned approximately 1 kHz to 50 MHz. The parallel variants showed narrower or shifted bands: about 200 kHz to 3 MHz for the lossless parallel inductor, 400 kHz to 300 MHz for the positive lossy parallel case, and 200 kHz to 50 MHz for the negative lossy parallel case. The fractional-order inductor maintained valid behavior from approximately 500 Hz to 1 MHz across fractional orders from 0.1 to 0.9. Time-domain measurements corroborated the phase accuracy: at 10 MHz the lossless simulator produced a measured phase shift of 86.58 degrees against a theoretical 90 degrees, a relative error of 3.80 percent, and the lossy variants showed errors of 1.83 percent and below the 10 percent bound.

Robustness checks added further detail. Sweeping the input amplitude from 5 mV to 250 mV at 10 MHz kept total harmonic distortion below 10 percent, corresponding to a usable dynamic range of 33.98 dB. Temperature simulations from -25 degrees C to 125 degrees C produced less than a 4.2 percent variation in equivalent inductance, an effect the authors attribute mainly to the temperature dependence of carrier mobility and threshold voltage in the DDGA transconductances. Monte Carlo analyses with plus or minus 5 percent uniform variations in capacitors, transconductance gains, and the RC elements of the fractional capacitor network showed tightly clustered frequency responses, indicating low sensitivity to component tolerances. The authors also analyzed non-ideal transfer errors and terminal parasitic impedances analytically, noting that parasitic effects can be minimized by choosing external capacitors much larger than the parasitic capacitances, and that gain errors can be compensated by adjusting the transconductances.

To show practical utility, the team connected their simulators to several application circuits, all again verified in simulation. These included current-mode and transimpedance-mode highpass filters, voltage-mode and transadmittance-mode highpass and inverse lowpass filters with cutoff frequencies of 1.59 MHz, a parasitic resistance cancellation technique exploiting the negative lossy series inductor, and a sinusoidal oscillator built around the negative lossy parallel inductor that started within roughly 40 microseconds, oscillated at a simulated 2.25 MHz, and produced output with 1.68 percent total harmonic distortion. A fractional-order highpass filter demonstrated the fractional inductor, with cutoff frequencies that depend on the chosen order alpha.

The comparison with prior literature underlines why the compactness matters. Many previously reported inductance simulators require multiple active elements, floating passive components, or several external resistors and capacitors, and some consume considerable power, with multi-OTA fractional-order designs reaching up to 20 mW in one cited case. The proposed circuit, by contrast, needs one DDGA, one grounded capacitor or one grounded fractional-order capacitor, and no external resistors, while offering lossless, positive and negative lossy series, positive and negative lossy parallel, and fractional-order operation within a single topology, with power consumption of 2.45 mW for the lossy integer-order configurations and 1.83 mW for the fractional-order one at a 0.9 V supply. The authors caution that these results remain simulation-based; experimental validation with discrete components or prototype IC fabrication, along with physical layout design and post-layout verification, is outlined as future work.

Subject of Research: A single-DDGA active circuit that electronically simulates integer-order and fractional-order inductors, verified through PSPICE simulation

Article Title: Integer- and fractional-order inductance simulators based on only a single DDGA and a grounded capacitor

Article References: Roongmuanpha, N., Shireen, S., Faseehuddin, M., Pukkalanun, T., & Tangsrirat, W. (2026). Integer- and fractional-order inductance simulators based on only a single DDGA and a grounded capacitor. Results in Engineering, 32, Article 113528. https://doi.org/10.1016/j.rineng.2026.113528

Image Credits: AI Generated

DOI: 10.1016/j.rineng.2026.113528

Keywords: inductance simulator, DDGA, fractional-order inductor, active filters, CMOS analog circuits, PSPICE simulation, fractional-order capacitor, Cauer-I RC network, electronic tunability, lossless inductor, analog signal processing, integrated circuits