Modern AI systems rely on thousands of processors, memory devices and networking components operating as a single computational platform. Training a large model requires continuously distributing data, exchanging intermediate results and synchronizing calculations across these devices. In traditional systems, these connections are made with copper traces, cables and electrical transceivers. At relatively short distances, electrical links remain efficient and inexpensive. However, as data rates rise, their physical limitations become increasingly severe. The resistance of conductors converts electrical energy into heat, while capacitance slows the charging and discharging of signals. At higher frequencies, skin effect, dielectric loss and signal reflections further distort the data stream.

The result is a growing communication bottleneck between processors. To compensate for signal degradation, electrical systems often require equalizers, retimers, amplifiers and other signal-conditioning circuits. These components consume power and add latency, particularly when a signal must pass through multiple stages. Electrical links also become more difficult to scale when many high-speed channels are placed close together, because neighbouring wires can interfere with one another through electromagnetic coupling. The problem is especially acute in AI hardware, where the performance of an accelerator is increasingly determined not only by its arithmetic capability but also by how quickly it can access memory and exchange data with other accelerators.

Optical interconnects approach the problem differently by transporting information as light. An electrical data signal is converted into an optical signal by a modulator, transmitted through a waveguide or optical fibre, and then converted back into an electrical signal by a photodetector. Light does not experience the same resistive losses as an electrical current flowing through a metal conductor, and optical channels can carry extremely high data rates over compact physical paths. Multiple wavelength channels can also share the same waveguide through wavelength-division multiplexing, allowing several independent data streams to travel simultaneously. These properties make optical communication attractive not only for long-distance data-centre networks but also for connections between chips in the same computing package.

Co-packaged optics brings the optical transceiver directly beside the electronic switching or computing device rather than placing it at the end of a long electrical connection. In a conventional architecture, a high-speed electrical signal may travel from a processor or switch across a package, through a board and into a separate optical module. Every additional millimetre of electrical routing increases loss and places greater demands on the transmitter and receiver. By positioning photonic components next to the main chip, co-packaged optics can shorten the electrical path and move the conversion from electrical to optical signals closer to the point where data is generated. The optical signal can then travel across the system with lower propagation loss and potentially lower energy per transmitted bit.

The review identifies three interconnected technological domains that determine whether optical compute interconnects can deliver system-level benefits. The first is the electrical subsystem, which includes drivers, receivers, serializers and deserializers, clocking circuits and power-management components. The second is the electro-optical and opto-electronic interface, where modulators encode data onto light and photodetectors recover it. The third is the optical transmission network, consisting of waveguides, fibres, couplers, switches and multiplexing structures. Improvements in only one domain may not be enough. A highly efficient optical modulator, for example, cannot compensate for inefficient driver electronics, poor coupling or excessive thermal overhead elsewhere in the package.

The roadmap described in the study follows the evolution of packaging from two-dimensional arrangements to increasingly integrated architectures. In a 2D co-packaged design, optical engines and electronic chips are placed side by side on a common substrate or package. This approach is comparatively accessible because it builds on established assembly methods, but it can require long connections across the package and may limit the density of optical channels. A 2.5D architecture uses an interposer, a specialised layer that provides dense electrical and optical routing between chiplets. By bringing compute, memory, switching and photonic components closer together, interposers can support shorter links and higher bandwidth densities while preserving some manufacturing flexibility.

The most ambitious stage is three-dimensional heterogeneous integration, in which different materials and devices are stacked vertically. Electronic logic, photonic circuits, laser sources and optical detectors could occupy separate layers optimized for their individual functions. Such integration could dramatically reduce the distance that signals travel and increase the number of connections available within a small footprint. It also introduces difficult engineering problems. Photonic devices often require materials and fabrication processes that differ from those used for advanced logic circuits. Aligning optical structures across stacked layers demands extreme precision, while repairing or testing a multilayer assembly can be more complicated than testing separate components.

Heat is another central challenge. Optical communication may reduce the energy required to move each bit, but the system still contains lasers, modulators, drivers, receivers and high-performance processors that generate heat. Co-locating these components concentrates thermal power in a small area. Temperature changes can alter the refractive index of photonic materials, shift the operating wavelength of resonant devices and reduce the stability of optical links. Lasers and detectors also have temperature-dependent performance. Effective cooling must therefore protect both the electronic circuits and the optical alignment, potentially requiring advanced heat spreaders, microfluidic cooling or new package materials capable of managing heat without disrupting optical operation.

Manufacturing and standardization will determine whether these technologies move beyond demonstrations and into large-scale computing infrastructure. Optical systems must be assembled with precise alignment, tested at high throughput and manufactured with acceptable yields. A defect in a photonic component or an imperfect fibre coupling point can reduce the performance of an entire package. The industry also needs common standards for optical interfaces, control protocols, chiplet communication, thermal specifications and testing procedures. Without interoperability, system designers may be locked into proprietary solutions, slowing adoption and increasing costs. Standardized interfaces could allow processors, photonic engines and memory devices from different suppliers to be combined in modular architectures.

The review presents optical compute interconnects not as a single replacement technology but as a broad architectural shift. The most successful systems are likely to combine electrical and optical links, assigning each connection type to the distance, bandwidth and latency requirements for which it is best suited. Electrical interconnects may continue to dominate very short local routes, while optical channels handle communication between chiplets, packages, racks or distant accelerator clusters. If engineers can reduce conversion losses, control heat, improve manufacturability and establish reliable standards, co-packaged optics could become a foundation for future AI and high-performance computing systems. The race to build faster artificial intelligence may therefore be decided not only inside the processor, but also in the invisible network of light carrying data between its many parts.

Subject of Research: Optical chip-to-chip interconnects and co-packaged optics for high-performance computing and artificial intelligence

Article Title: Co-packaged optics for high-performance computing and artificial intelligence

Article References: Kim, B., Choi, S.H., Zograf, G. et al. Co-packaged optics for high-performance computing and artificial intelligence. Nat Electron (2026). https://doi.org/10.1038/s41928-026-01681-6

Image Credits: AI Generated

DOI: https://doi.org/10.1038/s41928-026-01681-6

Keywords: Co-packaged optics, optical interconnects, photonic computing, chip-to-chip communication, artificial intelligence, high-performance computing, heterogeneous integration, 2.5D interposers, 3D stacking, data-centre technology

The heart of this advancement lies in the design of the neuromorphic processor, which integrates on-chip learning mechanisms using beyond-CMOS components, enabling the system to adjust its synaptic weights in situ. Traditional CMOS-based implementations, constrained by scalability and energy inefficiency, have long challenged the realization of compact and efficient neuromorphic systems. This new approach circumvents these barriers by embracing emerging nanoscale devices that can emulate synaptic plasticity with remarkable precision and low power consumption. The result is a processor that not only computes but also learns continuously, analogous to biological neural networks.

Key to this neuromorphic solution is the innovative hardware architecture that combines standard digital circuits with emerging analog elements representing synaptic functionalities. Unlike previous attempts that relied heavily on software emulation or fixed hardware weights, this processor dynamically updates its synapses through on-device learning algorithms implemented at the circuit level. The learning mechanism is based on spike-timing dependent plasticity (STDP), where the timing of input and output spikes determines synaptic strength modifications. Such integration of learning rules into hardware circuits ensures real-time adaptation and significantly reduces the energy overhead typically associated with training.

The integration of beyond-CMOS devices, such as memristors or phase-change memory elements, lies at the core of the processor’s synaptic arrays. These devices intrinsically possess nonvolatile resistive states, which correspond to synaptic weights, allowing the system to maintain learned information without continuous power consumption. The array structure depicted in the accompanying figure demonstrates how these devices are organized into crossbar arrays, enabling massive parallelism in synaptic operations. Each synapse can be individually programmed and updated, supporting high-resolution weight modulation and dense connectivity reminiscent of biological neural networks.

Another remarkable aspect of the design is the processor’s scalability and compatibility with existing semiconductor manufacturing processes. By carefully selecting materials and device configurations that interface seamlessly with state-of-the-art CMOS foundries, the team ensures that this neuromorphic platform can be produced using current fabrication infrastructure. This hybrid integration strategy avoids costly overhauls while enabling incremental incorporation of beyond-CMOS devices into mainstream processors, fostering a smoother transition toward more intelligent hardware systems.

The on-chip learning circuits utilize novel compact neuron models implemented with mixed-signal techniques, balancing analog and digital domains. These neurons generate output spikes based on accumulated input currents, encapsulating essential neuronal behaviors such as refractory periods and firing thresholds. This biologically inspired modeling contributes to the processor’s energy efficiency by minimizing unnecessary switching activities and exploiting event-driven computing principles. Event-driven processing ensures that computations occur only when relevant signals arise, drastically lowering power consumption relative to clock-driven architectures.

Importantly, the processor’s learning framework supports supervised and unsupervised paradigms, broadening its applicability to diverse machine learning tasks. By embedding learning rules directly at the synaptic device level, the system can autonomously adjust to changing signal patterns, enabling robust performance in noisy and variable environments. This capacity for lifelong learning and adaptation is essential for autonomous agents operating in real-time and unpredictable scenarios, such as drones, robotics, or edge AI applications.

The authors also address the challenges of device variability and endurance which arise with emerging memory technologies. To combat these obstacles, error-correcting circuits and redundancy strategies are integrated at various design layers, ensuring reliable operation over extended usage periods. Such architectural foresight is crucial for practical deployment, given that beyond-CMOS devices often exhibit stochastic behaviors and limited cycling durability compared to conventional transistors. The combined hardware-software co-design approach effectively mitigates these limitations while preserving the processor’s learning agility.

Equally notable is the processor’s impressive energy efficiency, achieved through the interplay of event-driven computation, in-memory processing, and neuromorphic plasticity. Conventional von Neumann architectures suffer enormous energy penalties due to separate memory and processing units, dubbed the memory wall problem. By embedding computational functions within memory arrays and performing synaptic updates locally, this neuromorphic design drastically reduces data movement and thereby power consumption. Performance benchmarks indicate that the processor sustains competitive accuracy on standard neural network tasks while consuming orders of magnitude less energy than traditional digital chips.

The implications of this research extend well beyond incremental improvements in AI hardware. By providing a scalable platform capable of on-chip learning with beyond-CMOS technology, the team paves the way for truly autonomous and energy-frugal smart devices. Applications range from continuous health monitoring wearables and adaptive sensor networks to intelligent prosthetics and beyond, where always-on learning and responsiveness are imperative. As neuromorphic processors evolve, they promise to deliver cognitive capabilities once exclusive to biological brains, directly embedded within physical silicon.

Moreover, this advancement ushers in new design paradigms for computing systems by bridging the gap between device physics and high-level learning algorithms. The processor embodies a holistic integration of hardware and software principles, showcasing how neuromorphic engineering can transform memory devices into computational units that learn and adapt. This synergy could redefine the approach to building AI systems, shifting from power-hungry, centralized models toward distributed, brain-inspired architectures optimized for edge deployment.

Future avenues inspired by this work may include the exploration of novel materials and three-dimensional integration schemes to further enhance synaptic density and connectivity. Such efforts could lead to processors with neuron counts approaching those of small mammalian brains while remaining compact and energy efficient. Additionally, expanding the processor’s learning protocols to more complex and hierarchical schemes might unlock advanced cognitive functionalities akin to those seen in higher-level biological systems.

Ethical and societal impacts are also an intrinsic consideration when advancing neuromorphic technology toward widespread adoption. On-chip learning systems that operate autonomously raise important questions about transparency, control, and security. Ensuring that these intelligent processors act reliably and predictably, especially in safety-critical environments, will be essential. Equally, their potential to enable ubiquitous AI embedded in everyday objects necessitates responsible stewardship to balance innovation with privacy and ethical standards.

Ultimately, the neuromorphic processor presented by Greatorex and colleagues marks a transformative milestone in the journey toward hardware-based artificial intelligence. By harmonizing emerging beyond-CMOS memory devices with biologically inspired circuits and learning frameworks, the research delivers a scalable, efficient, and adaptive computing platform. This work not only accelerates the realization of brain-like machines but also redefines the future landscape of AI hardware, promising systems that learn as naturally and continuously as living brains.

Subject of Research: Neuromorphic processor with on-chip learning integrating beyond-CMOS devices

Article Title: A neuromorphic processor with on-chip learning for beyond-CMOS device integration

Article References:
Greatorex, H., Richter, O., Mastella, M. et al. A neuromorphic processor with on-chip learning for beyond-CMOS device integration. Nat Commun 16, 6424 (2025). https://doi.org/10.1038/s41467-025-61576-6

Image Credits: AI Generated