The research, conducted by Jeong Woo Kim of the Department of Business Administration at Sunmoon University in the Republic of Korea, focuses on a problem that has largely escaped attention in semiconductor production planning: the conversion of die-level output into package-level capacity. In traditional memory manufacturing, a single wafer yields many individual chips that are packaged and tested one at a time. HBM breaks this linear relationship. Because each finished package contains four, eight, twelve, or sixteen stacked DRAM dies, the number of usable packages is always a fraction of the number of dies produced. Planning models that treat this conversion as a simple one-to-one mapping systematically overestimate how many packages a factory can deliver.

To correct this, the study embeds a discrete stacking factor, denoted Sj, directly into a multi-period mixed-integer linear programming model. The stacking factor is restricted to the commercial HBM configurations of 4, 8, 12, and 16 layers, excluding single- and double-layer structures that represent conventional commodity DRAM rather than true three-dimensional stacked memory. By dividing net die output by the stacking factor for each product code, the model ensures that the die-to-package conversion reflects physical reality. This prevents the over-allocation of resources at the packaging stage, a miscalculation that can lead to wasted energy, misused equipment, and unfulfilled customer orders in high-density stacking facilities.

The framework also refines the treatment of turn-around time, the interval between wafer input and the availability of finished dies. Because HBM fabrication involves roughly 200 to 300 process steps across photolithography, etching, and electrical die sorting, total turn-around times range from 30 to 45 days. When this exceeds the length of a single monthly planning period, naive models can mistakenly assume that wafers input in one month are available for packaging in the same month. The proposed model introduces a ceiling-function-based mechanism that calculates how many prior periods must elapse before a wafer becomes available as work-in-process, preserving physical flow consistency across extended lead times and preventing the model from counting inventory that does not yet exist.

Beyond the baseline formulation, the study develops two extension models that address different operational priorities. The first minimizes production disruption by penalizing month-to-month deviations from the previous confirmed production quantity, smoothing output when customer demand fluctuates. The second minimizes the number of unfulfilled product codes, using a priority-weighted penalty to concentrate shortages into fewer periods rather than spreading small deficits across many months. Together, the three formulations give manufacturers a menu of production policies: maximize demand fulfillment, minimize disruption, or minimize the count of unsatisfied orders, each subject to the same stacking and capacity constraints.

To validate the approach, the study applied the models to a simulated six-month production environment with three manufacturing lines and fourteen distinct HBM configurations derived from four wafer types. The baseline model, solved using the CPLEX optimization solver on a standard desktop computer, produced a total of 554,163 chips over the planning horizon while accurately converting die-level output into package-level demand fulfillment. Product codes based on wafer 4, which carries the highest net die yield of 500 dies per wafer, accounted for approximately 77.2 percent of total output, while low-volume configurations based on wafer 3 contributed less than one percent each.

Under simulated demand fluctuation, where customer requests were randomly scaled between 0.7 and 1.7 times their baseline values, the disruption-minimizing extension revealed a striking asymmetry. Wafer-2-based configurations, which represented about 20.9 percent of total output, absorbed 70.7 percent of total production disruption. In contrast, wafer-4 configurations, despite dominating output, experienced only 4.2 percent of total disruption. This suggests that high-volume configurations benefit from inherent production stability, while low-volume, high-layer products are disproportionately vulnerable to demand volatility, a finding with direct implications for how manufacturers allocate flexible capacity.

Shortage analysis further highlighted the role of specialized stacking facilities. Shortages concentrated in a small number of high-layer code-month combinations, coinciding with saturation of the advanced stacking equipment required for products with eight or more layers. The largest single shortage, 14,353 chips for configuration 2-5 in month four, occurred precisely when specialized facility capacity was exhausted. When the shortage-minimizing extension was applied, the total number of unfulfilled code-month instances dropped from twelve to between six and eight, a reduction of 30 to 50 percent, by consolidating multi-period shortages into fewer, larger deficits rather than distributing them thinly across consecutive months.

The study acknowledges several limitations. Physical sub-processes specific to HBM assembly, including through-silicon-via yield loss, hybrid-bonding alignment tolerances, thermal-compression bonding cycle times, and known-good-die pre-screening, were not explicitly modeled. These mechanisms primarily affect the net die and turn-around-time parameters rather than the structural formulation of the optimization model, meaning they could be incorporated in future work without changing the core framework. The author also notes that as the scale of the problem grows with additional wafer types, production lines, or planning periods, hybridizing the exact CPLEX-based formulation with metaheuristic or machine-learning methods could improve computational tractability.

The broader significance of this work lies in bridging a gap between two research communities. Recent studies on HBM have focused intensely on thermal dissipation, hybrid bonding, and structural configuration, demonstrating that stack configuration non-linearly affects manufacturing yield and process stability. Yet these physical and materials-science insights have rarely been translated into macro-level production planning. By embedding commercial stacking constraints directly into a unified manufacturing logistics model, this research offers a template for how the semiconductor industry can plan production with higher fidelity, ensuring that the promise of three-dimensional stacked memory is matched by equally sophisticated planning on the factory floor.

Subject of Research: Optimization of production planning for 3D-stacked high-bandwidth memory manufacturing

Article Title: Stacking-factor-integrated production planning for 3D-Stacked high-bandwidth memory manufacturing: an optimization approach

Article References: Kim, J. W. (2026). Stacking-factor-integrated production planning for 3D-Stacked high-bandwidth memory manufacturing: an optimization approach. Frontiers in Materials, 13, Article 1926885. https://doi.org/10.3389/fmats.2026.1926885

Image Credits: AI Generated

DOI: 10.3389/fmats.2026.1926885

Keywords: HBM, 3D stacking, semiconductor manufacturing, mixed-integer optimization, production planning, through-silicon via, DRAM, AI chips, capacity planning, CPLEX, supply chain, turn-around time

The breakthrough, published in the prestigious international journal Science, was led by Prof. Jianhua Hao, Head of the Department of Physics and Materials, Chair Professor of Materials Physics and Devices and Associate Director of the PolyU-Wuhan Technology and Innovation Research Institute at PolyU. The collaboration included researchers from the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. Dr. Zehan Wu, Research Assistant Professor in the same department, is the first author of the research article. Their work addresses what the International Roadmap for Devices and Systems (IRDS) has identified as one of the most pressing bottlenecks in modern microelectronics, and it does so using a device architecture that the roadmap itself has flagged as the most promising successor to today’s dominant transistor design.

To appreciate why this matters, it helps to understand how the transistors inside every laptop, smartphone, and data centre actually work. Integrated circuits are built from complementary metal–oxide–semiconductor field-effect transistors, or MOSFETs, which switch electrical current by raising or lowering an energy barrier. In the OFF state, charges face a barrier they cannot cross; when a gating voltage is applied, charges gain enough thermal energy to spill over the top of that barrier in a process called thermionic emission. The steepness of this transition, measured by a figure known as the subthreshold swing (SS), determines how much voltage is needed to flip the transistor from OFF to ON. Here nature intervenes: because thermionic emission depends on the thermal distribution of electron energies, the subthreshold swing of any MOSFET cannot fall below 60 millivolts per decade of current at room temperature. That is the Boltzmann limit, and it is not an engineering shortfall but a consequence of statistical mechanics itself.

The consequences of this limit are profound. As chipmakers pack more transistors onto each processor, the 60 mV decade⁻¹ floor forces operating voltages to remain far higher than ideal, which means wasted power, wasted heat, and a hard ceiling on energy efficiency. Advanced MOSFETs typically require gate-voltage ranges of around 800 millivolts to operate, and every millivolt of that overhead is multiplied billions of times across a modern chip. For the artificial intelligence accelerators now driving enormous growth in global electricity consumption, the inability to switch transistors at lower voltages has become one of the defining engineering challenges of the decade. Breaking the 60 mV barrier is therefore not an incremental improvement but a potential inflection point for the entire industry.

The escape route identified by physicists is quantum tunnelling. Instead of forcing electrons to climb over an energy barrier, a tunnelling field-effect transistor (TFET) allows them to pass straight through it, exploiting the quantum-mechanical probability that particles can traverse barriers that would classically be impenetrable. Because tunnelling probability depends on the barrier’s width and height rather than on the thermal energy of the electrons, a TFET can in principle achieve subthreshold swings steeper than 60 mV decade⁻¹ even at room temperature. The IRDS has singled out TFETs as the most promising alternative to MOSFETs precisely for this reason. In practice, however, experimental TFETs have struggled for years with a frustrating trade-off: devices that achieved steep switching typically delivered painfully low output currents, undermining their usefulness in real circuits.

Prof. Hao’s team solved this problem with an elegantly engineered material system. Using pulsed laser deposition (PLD), a technique in which intense laser pulses vaporise a target material so that it recondenses as an ultra-thin film, the researchers fabricated an alternating heterostructure of two-dimensional bismuth (Bi) and indium selenide (InSe) layers. The choice of bismuth is the crucial insight. In its bulk form, bismuth is a semi-metal, a material that is neither a proper conductor nor a proper semiconductor. But when reduced to two-dimensional form with precise control over the layer structure at the nanoscale, bismuth transforms into a semiconductor. This transformation allowed the team to engineer an ideal energy band alignment between the bismuth and the indium selenide, creating exactly the conditions needed for charge carriers to tunnel efficiently from one material into the other through the quantum tunnelling mechanism.

The performance figures reported in the study are striking. The resulting Bi/InSe TFET achieved subthreshold swing values well below the 60 mV decade⁻¹ thermionic limit, and it maintained this steep switching behaviour across six orders of magnitude of current, a range that matters enormously for practical digital logic, where transistors must remain reliably OFF across many conditions rather than only at a single operating point. Remarkably, the device accomplished all of this at room temperature, on standard centimetre-scale silicon substrates, without exotic cryogenic cooling or specialised wafer treatments. The operating gate-voltage range required was only 160 millivolts, a fraction of the roughly 800 millivolts demanded by advanced MOSFETs, translating directly into the kind of power savings that next-generation computing demands.

Just as importantly, the device resolved the long-standing weakness of previous experimental TFETs. The PolyU-led team demonstrated a high output current of up to several microamps per micrometre alongside an exceptionally high ON/OFF current ratio. Output current is not a vanity metric: it determines whether a single transistor can drive multiple downstream logic gates, a capability engineers call fan-out, and whether signals propagate through a circuit with minimal delay. A steep-switching transistor that cannot deliver adequate current would force designers into cumbersome workarounds and erode the very efficiency gains it promises. By combining steep slopes with robust current drive, the Bi/InSe device demonstrates compatibility with existing integrated-circuit design practices and even the potential for a generational upgrade of current chips rather than a disruptive replacement.

The manufacturing dimension of the work may prove as consequential as the physics. Pulsed laser deposition has long been valued in research laboratories for its precision, but questions have lingered about whether it can serve high-precision, wafer-scale production of two-dimensional materials. This study demonstrates the practical viability of PLD for exactly that role, producing uniform ultra-thin heterostructures on silicon substrates that are the backbone of the existing semiconductor industry. Because the device integrates seamlessly with traditional silicon-based manufacturing processes, the researchers argue that their approach provides a scalable roadmap toward energy-efficient microchips, rather than a laboratory curiosity that would require an entirely new industrial ecosystem to deploy. That compatibility with ultra-short channel lengths, which two-dimensional materials are particularly well suited to support, positions the technology for the transistor geometries that future process nodes will demand.

The implications extend well beyond the laboratory bench. Ultra-low-power, high-performance integrated circuits built on tunnelling transistors could reshape the energy economics of artificial intelligence, where specialised hardware already consumes power on the scale of entire cities, and where every reduction in switching voltage compounds across billions of operations per second. Prof. Hao has emphasised that the technology paves the way for the ICs essential to emerging AI chips and advanced semiconductor applications, and the publication of the findings in Science signals that the broader research community regards the result as a landmark. For decades, the Boltzmann limit has stood as an immovable fact of life for chip designers, a boundary drawn by thermodynamics itself. By replacing thermionic emission with quantum tunnelling in a carefully crafted two-dimensional heterostructure, the PolyU-led team has shown that the boundary can be crossed, and in doing so has brought a long-awaited experimental technology a decisive step closer to commercial reality.

Subject of Research: A quantum-tunnelling field-effect transistor based on two-dimensional bismuth and indium selenide heterostructures that overcomes the Boltzmann switching limit in integrated circuits

Article Title: PolyU develops quantum-tunnelling field-effect transistor to overcome barriers to integrated-circuit chip development

Article References: PolyU develops quantum-tunnelling field-effect transistor to overcome barriers to integrated-circuit chip development. (n.d.). Original publication

Image Credits: AI Generated

DOI: Not provided

Keywords: quantum tunnelling, tunnelling field-effect transistor, TFET, two-dimensional materials, bismuth, indium selenide, Boltzmann limit, subthreshold swing, pulsed laser deposition, integrated circuits, low-power electronics, AI chips